STM32 ARMv7

ARMv7
• ARMv7-A
• ARM and Thumb instruction sets
• Virtual address support in the memory management model

• ARMv7-R
• ARM and Thumb instruction sets
• Physical address only in the memory management model

• ARMv7-M
• Thumb instruction set
• Overall size and deterministic operation for an implementation are more
important than absolute performance
ARMv7M
• Highly deterministic operation
• Single/low cycle execution
• Minimal interrupt latency (short pipelines)
• Cacheless operation

• Excellent C/C++ target – aligns with ARM’s programming standards

in this area
• Exception handlers are standard C/C++ functions, entered using
standard calling conventions
• Designed for deeply embedded systems
• Debug and software profiling support for event driven systems
ARMv7M – ARM Cortex M4
• Supports Thumb 2
• Provides a mixture of 32-bit and 16-bit instructions
• Maintains code density with increased flexibility
• Special Support for SIMD & MAC instructions – DSP
• The SIMD operations in the Cortex-M4 handle two 16-bit data or
four 8-bit data in parallel
• QADD8, QADD16

• Pipeline – 3 stage – F,D,Ex

ARM Cortex M4
• State
• Thumb
• Debug Handler
• Modes
• Thread
• Handler Thread Thread
(PVL) (UPVL)
• Access Level CR
• Privileged
• Unprivileged
Processor Register Set
R0
R1
• Registers R0-R12
R2 • General-purpose registers
R3
R4 • R13 is the stack pointer (SP) - 2 banked versions
R5
R6 • MSP, PSP
R7
R8 • R14 is the link register (LR)
R9
R10 • R15 is the program counter (PC)
R11
R12 • PSR (Program Status Register)
R13 (SP)
R14 (LR) • Not explicitly accessible
R15 (PC)
• Saved to the stack on an exception

PSR • Subsets available as APSR, IPSR, and EPSR

 xPSR - Program Status Register
31 28 27 26 25 24 23 20 19 16 15 10 9 8 0

N Z C V Q IT T GE[3:0] IT/ICI ISR Number

• xPSR stored on stack during exceptions

• Condition code flags
• N = Negative result from ALU
• Z = Zero result from ALU
• C = ALU operation carry out
• V = ALU operation overflow
• Q = Saturated math overflow
• IT/ICI bits
• Contain IF-THEN base condition code or Interrupt Continue information

• ISR Number
• Stacked xPSR shows which exception was pre-empted

• T=1
SPECIAL PURPOSE
REGISTERS
Control Register

SPSEL nPRIV
RESET
Reset
• Update values of PC, MSP
• MSP – loaded from location – 0x00
• PC – loaded from location – 0x04 – with LSB set
MEMORY MAP
Processor Memory Map
External Private Peripheral Bus
E00F_FFFF
ROM Table
E00F_F000

UNUSED FFFF_FFFF
(XN)
E004_2000 512MB System
ETM
E004_1000 E000_0000
TPIU
E004_0000

1GB
External
E003_FFFF Peripheral
RESERVED
E000_F000
NVIC A000_0000
E000_E000
RESERVED
E000_3000
FPB 1 GB
External
E000_2000 SRAM
DWT
E000_1000
ITM
E000_0000 6000_0000
Internal Private Peripheral Bus
512MB Peripheral
4000_0000

512MB SRAM
2000_0000

512MB Code
0000_0000
EXCEPTIONS
 Exception Handling
• Exception types:
• Reset
• Non-maskable Interrupts (NMI)
• Faults
• PendSV
• SVCall
• External Interrupt
• SysTick Interrupt

• Exceptions processed in Handler mode (except Reset)

• Exceptions always run privileged

• Interrupt handling
• Interrupts are a sub-class of exception
• Automatic save and restore of processor registers (xPSR, PC, LR, R12, R3-R0)
• Allows handler to be written entirely in ‘C’
Vector Table for ARMv7-M Address Vector #
0x40 + 4*N External N 16 + N
• First entry contains initial Main SP … … …

• All other entries are addresses for exception 0x40 External 0 16

handlers 0x3C SysTick 15
• Must always have LSBit = 1 (for Thumb) 0x38 PendSV 14
• Table has up to 240 external interrupts 0x34 Reserved 13
• Implementation-defined 0x30 Debug Monitor 12
• Maximum table size is 2048 bytes 0x2C SVC 11

• Table may be relocated 0x1C to 0x28 Reserved (x4) 7-10

• Use Vector Table Offset Register 0x18 Usage Fault 6
• Still require minimal table entries at 0x0 for 0x14 Bus Fault 5
booting the core
0x10 Mem Manage Fault 4
• Each exception has a vector number 0x0C Hard Fault 3
• Used in Interrupt Control and State Register 0x08 NMI 2
to indicate the active or pending exception
type 0x04 Reset 1
0x00 Initial Main SP N/A
 External Interrupts
• External Interrupts handled by Nested Vectored Interrupt Controller (NVIC)
• Tightly coupled with processor core

• One Non-Maskable Interrupt (NMI) supported

• Number of external interrupts is implementation-defined

• ARMv7-M supports up to 496 interrupts

INTNMI
INTISR[0]
… NVIC

……
… Cortex-Mx
INTISR[N] Processor Core

Cortex-Mx Integration Layer

 Exception Handling Example
Higher Priority

IRQ1

IRQ2

IRQ3

Base CPU
Time
Core Execution Foreground ISR2 ISR1 ISR2 ISR3 Foreground
(ISR 2 resumes)
Reset Behaviour
Main
5
4
Reset Handler

0x04 Reset Handler Vector

1 0x00 Initial value of MSP r13 (MSP)
2

1. A reset occurs (Reset input was asserted)

2. Load MSP (Main Stack Pointer) register initial value from address 0x00
3. Load reset handler vector address from address 0x04
4. Reset handler executes in Thread Mode
5. Optional: Reset handler branches to the main program
Exception Behaviour
Main
4

3
1
Exception Handler

Exception Vector

1. Exception occurs
• Current instruction stream stops
• Processor accesses vector table

2. Vector address for the exception loaded from the vector table
3. Exception handler executes in Handler Mode
4. Exception handler returns to main
Interrupt Service Routine Entry
• When receiving an interrupt the processor will finish the current instruction for most
instructions – except long
• Processor state automatically saved to the current stack
• 8 registers are pushed: PC, R0-R3, R12, LR, xPSR
• During (or after) state saving the address of the ISR is read from the Vector Table

• Link Register is modified for interrupt return - EXC_RETURN

• FF FF FF F1 – Handler Mode
• FF FF FF F9 – Thread,MSP
• FF FF FF FD – Thread,PSP

• Load IPSR – with Exception No.

• First instruction of IR executed

• the total latency is normally 12 cycles

• ISR executes from Handler mode with Main stack

Example
• Exception 0x10 Raised
• Privileged Thread
Step 1 & 2
Rest of the steps
ISR
NVIC in STM32
• 82 maskable interrupt channels for STM32F405xx/07xx
• Including the 16 interrupt lines of Cortex-M4 with FPU
• 16 programmable priority levels (4 bits of interrupt priority are
used)
• low-latency exception and interrupt handling
• power management control
Interrupt Features
• Wake-up Interrupt Controller (WIC)
• The processor fully implements the Wait For Interrupt (WFI), Wait
For Event (WFE)
• Processor also supports the use of SLEEPONEXIT - causes the
processor core to enter sleep mode when it returns from an
exception handler to Thread mode
NVIC Registers
NVIC Registers
• Interrupt Set Enable Registers - 8 Registers
• Interrupt Clear Enable Registers – 8 Registers
• Interrupt Set Pending Register – 8 Registers
• Interrupt Clear Pending Registers – 8 Registers
• Interrupt Active Bit Register – 8 Registers
• Interrupt Priority Registers – 60 Registers
• Interrupt Control Type Register –Last 4 bits of a 32 – bit register