CMOS

Manufacturing
Process

Digital Integrated Circuits Manufacturing Process EE141

 CMOS Process

Digital Integrated Circuits Manufacturing Process EE141

 A Modern CMOS Process
gate-oxide

TiSi2 AlCu

SiO2
Tungsten

poly
p-well n-well SiO2
n+ p-epi p+

p+

Dual -Well Trench -Isolated CMOS Process

Digital Integrated Circuits Manufacturing Process EE141

 Circuit Under Design
VDD VDD

M2
M4

Vin Vout Vout2

M1 M3

This two-inverter circuit (of Figure 3.25 in the text) will be

manufactured in a twin-well process.

Digital Integrated Circuits Manufacturing Process EE141

 Circuit Layout

Digital Integrated Circuits Manufacturing Process EE141

 The Manufacturing Process
For a great tour through the process and its different steps, check
http://www.fullman.com/semiconductors/semiconductors.html

For a complete walk-through of the process (64 steps), check the

Book web-page

http://bwrc.eecs.berkeley.edu/Classes/IcBook

Digital Integrated Circuits Manufacturing Process EE141

 Photo-Lithographic Process
optical
mask
oxidation

photoresist photoresist coating

removal (ashing)
stepper exposure

Typical operations in a single

photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process spin, rinse, dry
step

Digital Integrated Circuits Manufacturing Process EE141

 Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO2
(d) After development and etching of resist,
chemical or plasma etch of SiO
Si-substrate 2

(b) After oxidation and deposition Hardened resist

of negative photoresist SiO
2
Si-substrate
UV-light
Patterned (e) After etching
optical mask

Exposed resist
SiO
2

Si-substrate Si-substrate

(f) Final result after removal of resist

(c) Stepper exposure

Digital Integrated Circuits Manufacturing Process EE141

 CMOS Process at a Glance
Define active areas
Etch and fill trenches

Implant well regions

Deposit and pattern

polysilicon layer

Implant source and drain

regions and substrate contacts

Create contact and via windows

Deposit and pattern metal layers

Digital Integrated Circuits Manufacturing Process EE141

 CMOS Process Walk-Through
p-epi (a) Base material: p+ substrate
with p-epi layer
p+

SiN
34
SiO (b) After deposition of gate-oxide and
p-epi 2 sacrificial nitride (acts as a
buffer layer)
p+

(c) After plasma etch of insulating

trenches using the inverse of
the active area mask
p+

Digital Integrated Circuits Manufacturing Process EE141

 CMOS Process Walk-Through
SiO
2
(d) After trench filling, CMP
planarization, and removal of
sacrificial nitride

n
(e) After n-well and
VTp adjust implants

p
(f) After p-well and
VTn adjust implants

Digital Integrated Circuits Manufacturing Process EE141

 CMOS Process Walk-Through
poly(silicon)

(g) After polysilicon deposition

and etch

n+ p+

(h) After n+ source/drain and

p+source/drain implants. These
steps also dope the polysilicon.

SiO2

(i) After deposition of SiO 2

insulator and contact hole etch.

Digital Integrated Circuits Manufacturing Process EE141

 CMOS Process Walk-Through
Al

(j) After deposition and

patterning of first Al layer.

Al
SiO
2
(k) After deposition of SiO
insulator, etching of via’s, 2
deposition and patterning of
second layer of Al.

Digital Integrated Circuits Manufacturing Process EE141

 Advanced Metalization

Digital Integrated Circuits Manufacturing Process EE141

 Advanced Metalization

Digital Integrated Circuits Manufacturing Process EE141

 Design Rules

Jan M. Rabaey

Digital Integrated Circuits Manufacturing Process EE141

 3D Perspective
Polysilicon Aluminum

Digital Integrated Circuits Manufacturing Process EE141

 Design Rules

l Interface between designer and process

engineer
l Guidelines for constructing process masks
l Unit dimension: Minimum line width
» scalable design rules: lambda parameter
» absolute dimensions (micron rules)

Digital Integrated Circuits Manufacturing Process EE141

 CMOS Process Layers
Layer Color Representation

Well (p,n) Yellow

Active Area (n+,p+) Green
Select (p+,n+) Green
Polysilicon Red
Metal1 Blue
Metal2 Magenta
Contact To Poly Black
Contact To Diffusion Black
Via Black

Digital Integrated Circuits Manufacturing Process EE141

Layers in 0.25 µm CMOS process

Digital Integrated Circuits Manufacturing Process EE141

 Intra-Layer Design Rules
Same Potential Different Potential
9 2
0
Well or Polysilicon
6
10 2
3 3
Active Metal1
Contact
or Via 2
3 Hole 3
2 2 4
Select Metal2

Digital Integrated Circuits Manufacturing Process EE141

 Transistor Layout
Transistor

3 2

Digital Integrated Circuits Manufacturing Process EE141

 Vias and Contacts
2
4
Via
1 1
5
Metal to
Metal to 1 Poly Contact
Active Contact 3 2

2
2

Digital Integrated Circuits Manufacturing Process EE141

 Select Layer
2
Select
3
2

1
3 3

2 5

Well
Substrate
Digital Integrated Circuits Manufacturing Process EE141
 CMOS Inverter Layout
GND In VD D

A A’

Out

(a) Layout

A A’
n
p-substrate Field
n+ p+ Oxide
(b) Cross-Section along A-A’
Digital Integrated Circuits Manufacturing Process EE141
 Layout Editor

Digital Integrated Circuits Manufacturing Process EE141

 Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

Digital Integrated Circuits Manufacturing Process EE141

 Sticks Diagram

V DD 3

In Out
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
1 “compaction” program

GND

Stick diagram of inverter

Digital Integrated Circuits Manufacturing Process EE141