EMT 357/3

FUNDAMENTAL OF
MICROELECTRONIC FABRICATION

Chapter 3
Overview on IC Manufacturing
 IC Manufacturing

Starting material: Si Wafer

End product: functioning chips

Wafer fabrication: Manufacturing process to create

semiconductor devices in a wafer.

Chip, die, device, circuit, microchip

Refer to patterns on the wafer surface

that form one functioning unit
 IC Manufacturing

IC chip manufacturing is a very complex process. It

involves:

 Circuit design
 Manufacturing material
 Clean room technology, processing, equipment
 Wafer processing technology
 Die testing
 Chip packaging and final test
 IC Manufacturing Flow
Design - Mask info to MASK-SHOP + GDSII file
Mask making
Generate runcard
Wafer Preparation
Basic wafer fabrication process:
1. Adding – ion implantation, diffusion, growth/deposited thin
film
2. Removing – series of steps to selectively mask or selectively
expose potions of wafer surface, wafer clean, etch, CMP
3. Heating – Annealing, reflow, Alloying
4. Patterning or lithography – series of steps to selectively mask or
selectively expose potions of wafer surface
 IC Manufacturing Flow
The semiconductor production process can be divided into two
sequential sub-processes commonly referred to as front-end and back-
end production, both of which contain many steps.
Front-end Production: Wafer Fabrication. Front-end production refers primarily to
wafer fabrication. The formation of the transistors directly in the silicon.
Front-end Processes (individual transistor)
Deposition
 Oxidation
 Diffusion
 Photolithography
 Etch (wet and dry)
 Implantation
 IC Manufacturing Flow
Back-end production refers to the assembly and test of individual
semiconductors. The assembly process is necessary to protect the
chip, facilitate its integration into electronic systems, limit electrical
interference and enable the dissipation of heat from the device.

Backend Process
 Metalization
 Interconnect
Test (Parametric and Functional)
Packaging
Final Test
IC Manufacturing process
 IC Design
The main design considerations are performance, die size (cost of chip
manufacture), design time, (cost of IC design), and testability (cost of testing).
 IC Design: Architecture to Layout
IC design includes architecture design, logic design, and transistor level design.

The application operating system and

divides modules for system.
-puts logic units
such as adders,
gates, inverters,
and registers into
each module.
 Logic Design – Puts logic units such as adders, gates, inverters and
registers into each module and run subroutines in each module .
 Circuit / Transistor Design – Individual transistors are laid out in each
logic unit.
 Layout – To transfer from schematic to layout.
 Layouts of the design are precisely printed on apiece of chromium glass to
make the masks, or reticle.
Mask/recticles are used in photolithography process to transfer the design
patterns to the photoresist temporarily coated on the semiconductor wafers.
VDD

S
pMOS

VIN VOUT

nMOS
S

VSS
IC design flow
Microelectronic fabrication:
from design to wafer
 Circuit Design
1st IC design by hand (Jack
Kilby)
Currently, hundreds of
designers work on single
product to design, validate
and layouted will take
several months to complete
with the help of CAD
tools.
Main considerations;
 performance
 die size
 design time and cost
 testability
 Mask/ Reticle
 After IC design is completed, generated layout image is printed on a
piece of quartz glass coated with a layer of chromium.
 A laser beam projects the layout image onto the photoresist coated
chrome glass surface.
 Photon change the chemistry of the exposed photoresist via a photo
chemical reaction, and later dissolved in a base developer solution.
 A pattern etching removes the chromium at the exposed area.
 Therefore, it transfers the image of the IC layout to the quartz glass.
 This is done at mask shop

Basic structure of photomask

Mask/ Reticle
IC Design: Layout and Masks of CMOS Inverter
When the chrome glass has an image that covers the entire wafer, it is called a mask.
A mask normally transfer the image to the wafer surface in 1:1 ratio.

At least five masks are required to make the simplest MOS transistor.
An advanced IC chip could take more than 25 masks/reticle.
Typical Microelectronic Fabrication Process Flow

 Around 500 process steps to complete IC fabrication

 Involves 20 masking steps
 How to fabricate
simple process MOSFET?
OVERVIEW ON WAFER
FABRICATION
Wafer Fabrication

Objectives
• Define and explain the importance of yield
• Describe the basic structure of a cleanroom
• Explain the importance of cleanroom protocol
• List four basic operations in IC processing
• Name at least six process bays in an IC Fab
• Explain the purposes of chip packaging
• Describe the standard wire bonding and flip-chip
bump bonding processes
 What is Yield

Yield determines whether a fab is making a profit or losing.

It depends on many factors, including people, environment,
Materials, equipment, and processes.

Yield engineer (or yield improvement engineers)

are responsible for improving yield in Ic fabs.
Why Yield is Important
 Definition of yield

There are three different types of yield in IC chip fabrication:

1. Wafer fabrication yield (wafer yield)

2. Wafer sort yield (Die yield)

3. Packaging yield
 Wafer Yield
Wafer yield = output of fabrication process

 The ratio between number of good wafers after

finishing all the process steps, and total number
of starting wafers .
Wafer out

Wafer started
 Wafer Yield/ Fab Yield
Wafer yield = output of fabrication process
Wafer yield = station yield 1 x station yield 2 X …….
Step Wafer in Station yield Wafers Cumulative
out yield

1- Oxidation 1000 99.5 995 995

2- S/D Mask 995 97.0 965 965
3- S/D dopping 965 99.3 958 958
4- Gate Oxide 958 99.0 948 948
5- Metallization 948 99.0 938 938

Calculate overall wafer yield?

 Factor affecting wafer yield
There are three different types of yield in IC chip fabrication:

1. Number of process steps: as number of step increase, yield reduce

50 step process: each step (station yield) = 99.5%
wafer yield = (0.995)50 = 0.75 (75% fab yield)

2. Wafer breakage = wafer handling = automated process

3. Process variation = specification limit

4. Process defects = isolated defects = process/ equipment

-any contamination in chamber/equipment will affect the wafer

5. Mask defects (related to photolithograpy)

= defects in hard mask – dusk, cracks, damaged mask
 Die Yield
 The ratio between number of good dies per total of dies on the tested
wafer after functional probe test.
Good (functioning) dies in a wafer

Dies per wafer

 Die Yield
Factors affecting die yield:

1. Wafer diameter
Increase wafer diameter die, reduce edge dies
Increase die size, increase edge dies
2. Die size (area)

3. Number of processing steps – higher defect density , reduce die yield

4. Circuit density

5. Defect density

6. Crystal defects – during manuf. of silicon wafer/before enter the fab

7. Cycle or process time

 Packaging Yield

The ratio between number of good chips after finishing all the
packaging steps, and total of chips packaged.

Packaged dies that pass electrical test

 Overall Yield

Wafer yield depends mainly on processing and wafer handling.

 Careless handling and robot malfunction could break wafers
 Faulty process such as misaligned during lithography, large amount of
particles, poor process uniformity, etc can also ruin wafers.
How Does Fab make Money
How Does Fab Make (Loss) Money
 Defects and Yield
Relationship between overall yield and killer defect density, chip size,
And number of process steps

Y – overall yield
D – defect density (minimum level determined by facilities)
A – chip area (die size)
n – number of processing steps
 Yield and Die Size
To achieve 100% yield, the killer defect density must be zero for every process step.
At the same defect density and chip size, the more process steps, the lower the yield.
It is also indicates that at the same defect density level, the larger the chip size,
the lower the yield (Figure below)

Illustration of the relationship between die size and die yield.

Yield Curve
 Typical Production Wafer
Some production wafers are designed with test dies, in which transistors and test
circuits are built during wafer processing.

Wafer with test dies

Typical Production Wafer

Wafer with test structure in scribe lines.

 Quiz

1. Write the wafer yield and overall yield

equation.
2. Assume that the die yield for every
process is 89%, the that involved are 250
process steps. Calculate the overall die
yield.
 Why Cleanroom?

 Particles kills yield

 IC Fabrication must in a clean room

 Artificial environment with low particle counts

 Types of contaminants
Types of contaminants in clean room:
1. Particles – particles sources come from workers in
the fab generated by process equipment
processing chemicals.

2. Metal Ions - Sodium is the most common, which is commonly

found in chemical sources.
3. Chemicals – unwanted chemicals – impurities of process
chemicals. Example: Lithography (photoresist),
etching (wet), cleaning wafer
4. Bacteria – particle contaminant

5. Airbone molecular contaminants –contaminants from process

tools or chemical delivery system
 Contaminant problems
Presence of contaminants can cause:

1. Device yield: failure of die increase, cost of yield reduce

2. Device performance: lowering of performance,

lowering of device, lifetime

3. Device reliability: hidden defects found during service

harder to detect
 What exactly is cleanroom?

Cleanroom - area with controlled level of contamination

 First used for surgery room to avoid

bacteria contamination

 Smaller device needs higher grade clean room

 Less particle, more expensive to build

Cleanroom Class
 Cleanroom Class

Illustrates the number of particles per cubit foot of air with different cleanroom classes
 Cleanroom Class (Definition of
Airborne Particulate)

The "cleanest" cleanroom in Federal Standard 209E is referred to as Class 1;

the "dirtiest" cleanroom is a class 100,000. ISO cleanroom classifications are
rated according to how much particulate of specific sizes exist per cubic meter.
Cleanroom Class
Class 10,
Class 1000, Class 100
Class 10000
 Effect of Particles on Mask
Particles can cause many different defects. For instance, particles on the clear mask or reticle
can cause pinholes for negative photoresist or stumps for positive photoresist during the
photolithography process.

-positive photoresist
-negative photoresist
deposited on substrate
deposited on substrate
-exposure to radiation
-exposure to radiation
through shadow mask
through shadow mask
(photomask)
(photomask)
-photoresist chemistry
-photoresist chemistry
altered in the exposed
altered in the exposed
region
region
-the exposed region
-the exposed region
become soluble (positive)
become insoluble
and can be selectively
(negative).
etched
-the unexposed region can
be selectively etched

The effect of a photo mask particle contaminate on the photolithography process.

 Effect of Particles on Wafer
Particle contamination can also cause other problem, such as a broken metal line, or a short
between metal lines.
Particles can block implanting ions and create an incomplete junction during ion implantation,
Which can affect the device performance.
 Cleanroom Structure
The cleanroom usually has a raised floor with grid panels, which allows airstream to flow
vertically from the ceiling to the area underneath the process and equipment area.
Airflow returns to the cleanroom through the high-efficiency particulate air (HEPA) filter.

Main features;
 raised floor
 laminar air flow
 HEPA filters
 higher pressure
 controlled humidity
and temperature

The basic structure of an advanced cleanroom.

Gowning Area of a cleanroom
Typical Wafer Process Flow
doping

or Layering
Typical Process Bay
 Wafer Test

Wafer Test

 Parametric Test (Wafer Acceptance Test Data)

 Functional Test (Die Yield)

Device specifications (Transistor)
Device Specifications (Resistance)
 Functional Test

After finishing all the processes, wafers are transferred for die testing.
Test each die on wafer, in which tiny pins are connected to the bonding pads or bumps on
the chip.
The test programs verify whether each IC chip meets the design requirements.
Failed dies are inked with a dot, and will not picked up for packaging after the die separation.
 Packaging

4 Main Purposes;

 to provide physical protection for the IC chip

 to provide a barrier layer against chemical impurities

and moisture

 to connect the IC chip to the electrical circuit board

 to dissipate heat generated during chip operations

 Chip Bond Structure
Metal or metal-coated ceramic is commonly used as the die-attaching material.
Die attaching is a thermal process, in which solder between the metal-coated
chip back side and substrate surface melts and attaches the chip to the substrate
after the solder condenses when its cool down.

Illustrates the basic structure of the die attaching

 Wire Bonding
After the chip is attached to the lead frame, a soldering machine makes the
connection between bonding pads on the chip and lead pins on the lead frame with
thin metal wires.
A traditional wire-bonding process steps (Figure)
 Wire Bonding

Gold wire is commonly used in the wire bonding process.

Wire Bonding
IC with Bonding Pads
 IC Chip Packaging

The traditional packaging technology with wire bonding of the IC chip

to the lead pins of the chip socket.
 Chip with Bumps
A different packaging technology is becoming widely used in IC
manufacturing.
Flip chip technology forms metal bumps instead of bonding pads
on the IC chip surface.
 Flip Chip Packaging
Advantages of flip chip packaging – it can significantly reduce the
package size

After the IC chip is connected to the lead pins of the chip

socket, the chip and lead frame is ready to be sealed.
Molding Cavity for Plastic Packaging

Plastic packaging uses a molding technique to seal the IC chip and the lead frame
with plastic. After the wire bonding, the lead frame is placed between the top and
bottom chase of the packaging tool.
 Ceramic Seal
Compared with plastic packaging, ceramic packaging provides better protection
against chemical and moisture contamination and better physical protection.
It also has much better stability and higher thermal conductivity.
The main advantage for plastic packaging is its significantly lower cost.
 Exercise
• Write the wafer yield & overall yield equation.
• Assume that the die yield for every process is 89%,
the that involved are 250 process steps. Calculate
the overall die yield.
• In October 2011, the profit margin per month for
Company A was around $50M/month, Calculate the
die yield if the throughput for that month was
8,000 wafer/month and the cost was around $500.
QUIZ