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Chapter 1:
Digital Design Concepts
Part 1
Week 1
Digital and Analog Signals
100
95
90
85
80
75
70
Time of day
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12
A .M . P.M .
Easily Programmable :
Digital systems interface well with computers and are
easy to control with software.
HIGH HIGH
Rising or Falling or Falling or Rising or
leading edge trailing edge leading edge trailing edge
LOW LOW
t0 t1 t0 t1
Actual pulses are not ideal but are described by the rise time,
fall time, amplitude, and other characteristics.
Overshoot
Ringing
Droop
90%
Amplitude tW
50%
Pulse width
10%
Ringing
12
Propagation Delay
Definition 1
(tPHL+tPLH)/2
Definition 2
1 1
The clock is a basicf timing T that is an example of a
signal
T f
periodic wave.
1 1
T 313 ps
f 3.2 GHz
Pulse Definitions
Volts
Pulse
width
Amplitude (A) (tW)
Time
Period, T
Timing Diagrams
1
Computer Printer
0
0
t0 t1
Basic Logic Functions
Two
binary A= B Outputs
numbers
B
A< B
4 5 6 0
1 2 3
0 . +/–
Calculator keypad
Binary input
7-segment display
Basic System Functions
Multiplexer Demultiplexer
A D
Data from Data from Data from Data from
A to D B to E C to F A to D
∆t1 ∆t1
∆ t1 ∆ t2 ∆ t3 ∆t1
B E
∆t2 ∆t2
∆t3 ∆t3
C F
Switching Switching
sequence sequence
control input control input
Basic System Functions
Counter Parallel
output lines Binary Binary Binary Binary Binary
code code code code code
1 2 3 4 5 for 1 for 2 for 3 for 4 for 5
Input pulses Sequence of binary codes that represent
the number of input pulses counted.
Serial bits
on input line
Initially, the register contains onlyinvalid
0101 0 0 0 0 data or all zeros as shown here.
SN 74 ALS 00 N
Pin 1
Standard Chips
Fixed OR
Programmable array and
AND array output logic
Group of 8 logic cells Memory block
Interconnection
wires
Initial design
Simulation Redesign
No
Design correct?
Yes
Successful design
Programmable Logic
Devices
Field Programmable
Gate Arrays
PROM, Programmable
ROMs
Block diagrams of simple programmable logic devices
(SPLDs).
• Altera’s QuartusII
• Xilinx ISE
• Lattice
Basic PLD design flow Design Entry
• Schematic
• Source Codes (HDL,
hardware description
language)
Functional Simulation
- verify that the circuit
functions as expected
Synthesis
-Converts schematic or
HDL codes into logic
gates
circuit
Timing Simulation
-Considers propagation
delay of the circuit