Experiment-2

Aim: To write VHDL code for universal Gates circuits: NAND, NOR, XOR and observe the
waveform and synthesize the code with technological library with given Constraints.
Apparatus: Modelsim PE Student Edition 10.1 Software.
Theory: Logic gates are the basic components in digital electronics. They are used to create digital
circuits and even complex integrated circuits. For example, complex integrated circuits may bring
already a complete circuit ready to be used – microprocessors and microcontrollers are the best
example – but inside them they were projected using several logic gates.
NAND Logic:
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all
NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on
the output. The small circle represents inversion.

Figure 2.1. Symbol of NAND gate.

Table 2.1. 2 input NAND gate truth table

1
VHDL Code for NAND Logic:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NAND_LOGIC IS
PORT(X: IN STD_LOGIC; Y: IN STD_LOGIC; Z: OUT STD_LOGIC);
END NAND_LOGIC;
ARCHITECTURE BEHAVIORAL OF NAND_LOGIC IS
BEGIN
PROCESS(X,Y)
BEGIN
IF(X = '1' AND Y = '1')
THEN
Z <= '0';
ELSE
Z <= '1';
END IF;
END PROCESS;
END BEHAVIORAL;

i
Figure 2.2. Simulation waveform results of NAND logic

2
NOR Logic:
This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR
gates are low if any of the inputs are high.
The symbol is an OR gate with a small circle on the output. The small circle represents inversion.

Figure 2.3. Symbol of NOR gate.

Table 2.2. 2 input NOR gate truth table

VHDL Code for NOR Logic:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NOR_LOGIC IS
PORT(X: IN STD_LOGIC; Y: IN STD_LOGIC; Z: OUT STD_LOGIC);
END NOR_LOGIC;
ARCHITECTURE BEHAVIORAL OF NOR_LOGIC IS
BEGIN
PROCESS(X,Y)
BEGIN
IF(X = '0' AND Y = '0')
THEN
Z <= '1';
ELSE
Z <= '0';
END IF;
END PROCESS;
END BEHAVIORAL;
3
 Figure 2.4. Simulation waveform results of NOR logic

XOR Logic:
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two
inputs are high. An encircled plus sign ( ) is used to show the EOR operation.

Figure 2.5. Symbol of XOR gate.

Table 2.3. 2 input XOR gate truth table

4
VHDL Code for XOR Logic:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY XOR_LOGIC is
PORT(X : IN STD_LOGIC; Y : IN STD_LOGIC; Z : OUT STD_LOGIC);
END XOR_LOGIC;
ARCHITECTURE BEHAVIORAL of XOR_LOGIC is
BEGIN
PROCESS (X,Y)
BEGIN
IF(X = Y )
THEN
Z <= '0';
ELSE
Z <= '1';
END IF;
END PROCESS;
END BEHAVIORAL;

Figure 2.6. Simulation waveform results of NOR logic

Results: VHDL code for the universal gates circuits is written, the waveform is observed and the
code is synthesized with the technological library and is verified.