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Design of stopwatch through digital logic design

Article · December 2019

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Hafiz Abdur Rehman Uzair Mir


Ghulam Ishaq Khan Institute of Engineering Sciences and Technology Ghulam Ishaq Khan Institute of Engineering Sciences and Technology
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STOPWATCH
Mir M. Uzair, Hafiz Abdur Rahman,, Digital Logic Design Lab (EE-221L) Fall 2018, GIKI, SWABI.

count with each clock, displaying 1 to 9 in its seven segments.


Abstract—Contents of this report show the algorithm on how to As soon as 10 counts was incremented by IC a high to low
design stopwatch using integrated circuit technology, the IC used signal was obtained from its pin 5 which indicates the
in the respective stopwatch. It IC circuitry comes up with completion of ten increments.
asynchronous counter and binary to seven segment decoders in
single and complete package. The basic concept around which
the project emphasizes are combinational logic circuit concept i.e. The pin 5 was connected to the clock pin of the next 4026 IC.
D-Flip Flop. The devised stopwatch have Minute, Second and milliseconds Therefore whenever 10 counts
sections, which changes with 100 Hz frequency. Project serves the main purpose was completed by the 7 segments, the high to low signal at the
of applying technique and skills garnished during recent logic lab and course pin 5 will feed a single clock pulse input to the second IC and
lectures. The core combinational logic concept is fully implemented at hardware therefore the corresponding 7 segments will be incremented
as well as software level to help us coping out with day to day challenges thriving one value. For a digital clock we must reset second IC when it
in electronic world to bring the life more at ease with help of electronics circuitry. reaches to number 6 because we want seconds count up to
This project aims to enhance our skills in creating efficient and complex circuits. "59” therefore we used IC 7408 (Dual input AND Gate

Keywords: IC 4026, Timer IC 555, Seven Segment Display, Combination B. Design Overview
Logic Circuit, 7408 Dual Input AND GATE, Proteus/Multism.

System design consists of Top down approach [5]. This


system mainly performs two functions i.e. Digital clock and
I. INTRODUCTION Stopwatch. These functions are implemented using counter
module, stopwatch module and display module.
A Stopwatch displays the time digitally and start, stop and
reset time. Instead of using the rotary mechanism of
electromechanical clock, it uses digital counters to count
Counter module consist of second, minute, hour counter which
are updated by internal clock signal. Internal clock signal is
generated on the completion of every counter and it will be
milliseconds, second and minute. It can stop and start with the updated by preceding counter. The stopwatch module displays
same button and reset on the other switch, it doesn’t reset until up to 60 minutes. It has separate clear and start switch.
it’s been stopped. The seconds reset at 60 seconds and pass the Display module is nothing but seven segment common anode
carry to minutes. It can count up to 99 minutes. display. A switch is provided to choose between Digital clock
and stopwatch Top module combines Counter Module,
Stopwatch Module and Display Module.
II. LITERATURE REVIEW

A. Working

The working of the circuit starts with the 555 timers where it
was wired as a monostable Multilibrary. The 555 timers
generate clock pulse after a second and output of 555 is
connected to pin 1 of IC 4026 which is a seven-segment
display decade counter which is used to drive a 7-segment
display with input clock pulse. Here the clock pulse was
obtained from the monostable multilibrary and fed into the pin
1 of first IC 4026. Pin 2 was usually grounded since giving
high signal to this pin will inhibit the input clock signal to pin
1 and pin 3(Enable Clock) is always taken High.

Initially when the circuit is switched ON the 7 segments will


indicate "00:00:00" count and as soon as the negative trigger
was given to 555 high pulse will be obtained from pin 3. The
high pulse was fed to first IC and therefore it increments its
2

C. Components Required

Material Quantity
1. 4017 IC 1
2.4026 IC 8
3. 7411 IC 4
4. 555 IC 1
5. 470K OHM 25
6. Switches 3
7. Capacitor 1 .5µF 1
8. 5 Volt DC Supply 1

D. 4026 IC
The IC 4026 is an IC which can perform the function of both
a counter as well a 7-segment Driver. One single IC can be E. Seven- Segment Display
used to count form zero (0) to nine (9) directly on a Common
Cathode type 7-segment display. The count can be increased A Digital Decoder IC, is a device which converts one digital
by simply giving a high clock pulse; also, more than one digit format into another and one of the most commonly used
(0-9) can be created by cascading more than one 4026 IC. So, devices for doing this is called the Binary Coded Decimal
if you have a 7-segment (CC) display on which you have to (BCD) to 7-Segment Display Decoder.
display numbers that are being counted based on some
condition then this IC will be a perfect choice. A standard 7-segment LED display generally has eight (8)
input connections, one for each LED segment and one that
Pins Configurations: acts as a common terminal or connection for all the internal
display segments. Some single displays have also had an
additional input pin to display a decimal point in their lower
right- or left-hand corner.
The Common Cathode Display (CCD) – In the common
cathode display, all the cathode connections of the LED’s are
joined together to logic “0” or ground. The individual
segments are illuminated by application of a “HIGH”, logic
“1” signal to the individual Anode terminals.
Internal Circuitry: Schematics:

Timing Diagram:
3

Internal Circuitry:

F. 7411 Three Input AND GATE


7411 is triple input AND gate. It is used to apply condition of
59 on minutes and second and apply the condition of 24 on
hour.
1-Hertz Frequency Schematic:
Schematic:

G. 555 Timer
III. CONCLUSION
The 555 is basically a monostable Multi-vibrator. The
important characteristics of a Monostable Multi-vibrator is as The designed Stopwatch provides excellent result on the basis
long as the pin 2 receives a positive trigger the output at pin 3 of performance when compared to any standard stopwatch, the
will be of low state. And when negative trigger was fed into little variation in the frequency of the clock by 555 timers is
due to the generation of ripple carry in the cascaded circuitry
the pin 2, the output at the pin 3 will go high for a specific
of multiples 4026 asynchronous counter, The clocking output
period of time. This time was decided by the Resistor and
from the 555 timer astable multi-vibrator circuit will not be
Capacitor connected with it. You can see my post "How to
properly use 555 timer" for help, link is given at the end of stable all the time, because the change in temperature will
page. affect the frequency of the output clock [1].
The power consumption in CMOS is quite a sound and it
handle with great intelligence compare to TTL. I had a
problem using 4017 decade counter to stop the 4 th 4026
decoder at “6” so we used an and gate instead.
4

IV. ACKNOWLEDGEMENTS

We would like to pay gratitude to course Instructor Arbab Rahim Khan, due
to his phenomenal lectures at EE221 course; made us able to use
combinational circuit logic efficiently, which assisted us applying those
logics and concepts in day to day life digital electronic circuitry designing.
We are thankful to our course-mate Muhammad Ibrahim khan for providing
his expertise time and again to help coping out the bugs in our designed
circuitry. Last but the least our hardworking Lab Engineer Muhammad Adil
deserves great appreciation for his welcoming response throughout the
project designing timeline.

REFERENCES

[1] Thomas L.Floyed , “Digital fundamentals,”.


[2] EE221 Lab Manual,Giki,Swabi,
[3] T. Instruments, “http;//www.ti.com,” 2017 [Online]
http://www.ti.com/lit/ds/symlink/ne555.pdf
[4] Spec, “electro-tech-online.com,” 28 Octuber 20115
[5] T. Instrument, available: http://www.ti.com/lit/ds/symlink/cd4026b.pdf

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