Temas de Clase

Electronic Technology Department
School of Industrial Engineering

University of Vigo
List of Topics, Chapters and Exercises – Academic Year 2018-2019
Topic 6 – Linear Regulators
• Electronics Devices and Circuits Theory

Boylestad and Nashelsky
• Chapter 15
◦ Examples 15.8, 15.9, 15.10, 15.12 and 15.15
◦ Exercises 19, 20, 21 and 22
Topic 7 – AC to DC Converters
• Power Electronics, D. Hart, 2011, McGraw-Hill

• Chapter 3
◦ Examples 3-1, 3-2, 3-5, 3-7, 3-8, 3-10
◦ Problems 3-1, 3-2, 3-4, 3-5, 3-8, 3-9, 3-13, 3-14, 3-23, 3-24, 3-25, 3-26
• Chapter 4
◦ Examples 4-6
◦ Problems 4-1, 4-2, 4-8, 4-23
Topic 8 – AC to AC Converters
• Power Electronics - Circuits, Devices and Applications, Muhammad Rashid, Pearson

• Chapter 6 - AC Voltage Controllers
◦ Examples 6.01, 6.02 and 6.03
◦ NOT examples 6.04 to 6.07
◦ Example 6.08, 6.09, 6.10 and 6.11
◦ Problems 6.01, 6.02 and 6.03
Topic 9 - DC to AC converters
• Power Electronics - Circuits, Devices and Applications, Muhammad Rashid, Pearson

• Chapter 8 – Inverters
◦ Examples 8.1, 8.2, 8.4
◦ Use of diagrams in Fig. 8-10, 8-12 and 8-14
◦ Problems 8.1, 8.2, 8.3, 8.4, 8.5, 8.6, 8.7, 8.8 and 8.9
Topic 10 - DC to DC Converters
• Electronic Devices and Circuits, Cathey, Schaum

• Chapter 10 – Switched Mode Power Supplies
◦ Examples 10.2, 10.3, 10.4
◦ Solved Problems 10.2, 10.3, 10.4, 10.10, 10.13
◦ Supplementary Problems 10.16, 10.17, 10.23
◦ The bulletin (in Spanish)
10/03/2016
CHAPTER 1 :
Introduction to microcontrollers
1. Introduction
2. Microcontroller components
3. Memory architectures
4. Instruction Set architectures
5. Selection criteria
Escuela de Departamento de
Ingeniería Industrial Tecnología Electrónica
1. Introduction
• COMPUTER:
• Digital electronic system (fixed hardware) capable of executing a program.
• Program: a sequence of instructions, written to perform a specified task on a computer
(digitally encoded).
Keyboard,
screen,
mouse,audio
system, etc.
Human
Serial, inter-
Parallel,
Ethernet, face Hard disk,
etc floppy disk,
CD, etc.
Communi
Communi- Storage
g
Control
C nt l
cation
elements Unit
Software
Introduction
execution system
Digital I/0, Control
analog I/O. elements
Industrial Electronics System Design 2
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• Basic concepts
• Bistable: 1 bit memory cell

• Register: m-bit group of bistables
• Word
W d size:
i size
i off the
th register
i t in
i bits,
bit for
f instance
i t 8 bits
bit
• Memory: group of registers
• Size: n locations of m bits, for instance 8kx8
• Bus: shared connection among digital elements
• Only one element writes to the bus at each instant
• Third-state or high impedance gate:
E S
Introduction
C
• Semiconductor digital memories:
• Electronic devices for the storage of digital data
• Storage capacity: n locations x size of location
• Locations  memory addresses  binary combinations (address bits)
• n bits for address, data of m bits (m = 8  Byte)  size 2n x m
• n = 10, 210 = 1024 ≈ 103  1k / n = 20, 220 ≈ 106  1M / n = 30, 230 ≈

109  1G / n = 40,
40 240 ≈ 1012  1T
Introduction
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• MICROCOMPUTER:
• Computer in which the control unit is based around a microprocessor
Address bus m Bits (8,16,32)
m m m
INPUT Peripherals
CPU MEMORY AND
OUTPUT
p n p n p n
Data bus n Bits (8,16,32)

Control bus
In charge of reading and executing the

instructions of a program stored in a When integrated in a chip:
memory. When integrated in a chip => INTEGRATED MICROCOMPUTER
MICROPROCESSOR
Introduction
Process control Other

applications
Industrial Electronics System Design MICROCONTROLLER 5
• MICROCONTROLLERS APPLICATIONS:
• Integrated microcomputer designed for proccess control applications
Cars
Computing
Communications
Tool-machine
Consumer electronics
Introduction
Toys
Instrumentation
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• MICROCONTROLLERS MAIN CHARACTERISTICS:
• Input/output resources: ability to operate with the process

• Number of digital inputs/outputs.
• Number of analog inputs/outputs.
• Ability to detect events (interrupts).
• Ability to communicate: distributed control systems.
• Small size: reduced number of pins (multifunction).
• Availability of a range of devices: they are selected in function of the needs of

the application without changing the tools of programming or debugging.
• Operating security: watch and detection resources of a failure.
• Power: low power applications.
• Protection of intellectual property: protection of unwanted readings of the

program memory.
Introduction
2. Microcontrollers components
Oscillator
Timers/counters Interrupt Parallel Serial Analog

management I/O I/O I/O
Microcontroller componeents
Address,, data and control buses
Watchdog ROM program RAM data memory

memory
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CPU => Microprocessor = It gathers the elements to execute a program
Instruction Register
(IR)
Accumulator (ACC)
Control
Unit
Arithmetic
Logic Unit Status Register
(ALU)
Data address
register
Instructions too big -> how to reduce their size
• Instruction:
Operation Address
Code Field
Result Next
Operation 1st 2nd
instruction to
Code Operand Operand Address
execute
Address Address Add
Address
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• Remove field of address of next instruction to execute :

– Program -> It is often listed in continuous addresses
– Next instruction pointer = PROGRAM COUNTER
• Counter register able to point at any address in program memory
– Branch or jump instructions become necessary
Result Next
Operation 1st 2nd
instruction to
execute
Address Address Address
• Remove field result address:

– Storage of results in one of the operands
– It requires hardware for that

– Data transfer instructions become necessary
Result Next
Operation 1st 2nd
instruction to
execute
• Remove 2nd operand address:

– All operations are made with a predefined register
– Operand register = ACCUMULATTOR.
• Adequate size to store temporally the biggest possible operand
– Data transfer instructions become necessary
Result Next
Operation 1st 2nd
instruction to
execute
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Memory :
• Random access.
• Active (RAM) -> Data to be processed
• Passive (ROM, EPROM,PROM,OTP,FLASH) -> program
• Protection of unwanted readings of the program memory
I/O Elements:
• They are necessary to control a process
• Digital I/O, parallel:
• Independent terminals to read or write binary signals. They are usually
programmable in whether they are outputs or inputs
• Parallel groups of bits to read or write binary combinations
• Digital I/O,
I/O serial:
• They are usually used to communicate between processors
• They follow standardized protocols such as (RS232, I2C, USB, etc)
• Analog I/O:
• Resources to read or write analog signals
Timer unit:
• Resources for measuring time
• Typical applications:
• Timing generation (clock, delay, etc)
• Measuring signal period, frequency or phase
• Event counter
Interrupt manager:
• Resources for the detection of asynchronous events
Multifunction terminals:
• Downsizing encapsulation -> less terminals
• Often
Of applications
li i ddo no use all
ll I/O resources
• A terminal can be used for different functions (not simultaneously)
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3. Memory architectures
Harvard architecture Von Neumann architecture
Program Program
Memory Memory
µprocessor Data
Memory
Data
Memory µprocessor
More terminals Less terminals

Memory architectures
Overlapping of the fetch and

execution cycles of an
instruction
Industrial Electronics System Design

Pic Microcontrollers15
4. Instruction Set Architectures

• Operation code => Binary value that tells the control unit what to do
• Options (that modify the inner workings of the processor):
– Complex Instruction Set Computer - CISC:
• Operations do a lot of things with a single code
• The decoding and executing circuits of the instructions have to be complex to do
a lot of things
• Instructions are more similar to a high level language and therefore easier to
program
– Reduced Instruction Set Computer – RISC:
ures
• Operations do simple things for each code

Instruction Set architectu
• Circuits are more simple because instructions do less things

• Address modes are also simpler which contributes to the simplification of the
hardware
• Simpler operations execute faster
• They are usually associated with Harvard memory organizations and instruction
pipelining
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5. Selection criteria
• Operating frequency: typically from 1 MHz to 25 MHz, but they can go
up to GHz
• Higher frequency gives faster speed but higher cost
• Word size: typically 8, 16, 32 up to 64 bits
• Bigger size gives higher processing power and speed but also higher
cost
• Memory organization: increasingly often Harvard
• Harvard more efficient and faster than von Neumann but requires
duplicated memories and higher cost
• Instruction set
• RISC more efficient and faster than CISC
• Low power modes for portable applications
Selection criteria
• Peripherals depending on the application
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CHAPTER 2 :
Microcontroller characteristics
1. Introduction
2. Arithmetic and logic unit
3. Control unit. Pipelining
4. Program memory
5. Stack memory management
6. Data memory
7. Peripherals
1. Introduction
• Characteristics of the PIC18F45K20:
• HARVARD architecture
• Program memory-> 12, 14 o 16 bit positions
• Data
D memory -> bytes
b (8 bi
bits))
• RISC instruction set
• Transfer and arithmetic/logic operations based in the use of an

accumulator (Work register).
• Two step pipelining:.

• All instruction execute in one instruction cycle (4 oscillator cycles) unless it
is a jump instruction
• Stack memory in dedicated memory space without Stack Pointer.

Introduction
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• Peripherals dedicated to proccess control: timers/counters, digital I/O,

analog I/O, serial communications, compare and capture unit, interrupt
management.
• Watch-Dog timer
• Protection against undesired memory access

Introduction
2. Arithmetic and logic unit

• ALU-> Arithmetic and logic instructions
Typical structure PIC structure
Data
memory Data
memory
W register
Arithmetic and logic unitt
ACC
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• PIC 18F45k20 structure
Address field of a
instruction
Multiply:
• 8 x 8 (bits) -> 16 bits
ALU:
• ADD
• SUB
• INC, DEC
• AND Internal data bus
• OR
• XOR
• Negate
Modifies STATUS
STATUS register
Memorizes the result of operations (arithmetic, logic or transfer)
7 -
6 -
5 -
4
N: Negative bit. It indicates whether the result was negative (two’s complement).
N
1 = Result was negative. 0 = Result was positive
Overflow bit. It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of
3 OV the result) to change state (two’s complement).
1 = Overflow occurred for signed arithmetic. 0 = No overflow occurred
2
Zero bit. 1 = The result of an arithmetic or logic operation is zero.
Z
0 = The result of an arithmetic or logic operation is not zero
Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions). 1 = A carry-out
1 DC from the 4th low-order bit of the result occurred. 0 = No carry-out from the 4th low-order bit
of the result
Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions). 1 = A carry-out from
0 C the Most Significant bit of the result occurred. 0 = No carry-out from the Most Significant bit
of the result occurred
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3. Control unit. Pipelining

• Synchronous sequential system in charge of generating all the
signals that control the processor
Instruction from the Address field of a
program memory instruction
Instruction register
Control Unit
Control unit. Pipelining
Fetch and execution of an

instruction
Instruction cycle and execution

• 2-level pipeline
• Instruction cycle (CM) -> 4 mail oscillator cycles (OSC1)
PC=PC+1
TCM Fetch next instruction selected by the PC
Control unit. Pipelining
Execution
Execution
Fetch Execution
Fetch Execution
Fetch
PIC18F45K20 -> i=2 (due to the internal memory organization in 8 bits)
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4. Program memory
• 32KByte FLASH memory
• Instructions:
• Organized
g in bytes.
y
• Located on even addresses (LSB=0 ).
0000h Reset
0008h High priority interrupt
0018h Low priority interrupt
Internal memory
7FFFh
8000h
Program memory
External memory
1FFFFFh
Management of constant data

values stored in program memory Data Bus
Program Counter (PC)
Program memory
address bus
Stack memoy and stack

Program memory
pointer
Program memory data bus for
instructions and constants
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5. Stack memory management

• Stack memory -> It stores the return addresses of call
instructions
Da
Da Call to a subroutine
Da+1
Db
Db+1 Da+1 D
K
Dc Dp
ment
Return from a
Db Call to a subroutine
subroutine
Da+1
Stack memory managem
Dc+1
Dd Db+1
Db+1
Dd+1
Call to a subroutine
• LIFO (Stack)
• 31 memory locations of 21 bits
• STKPTR (Stack Pointer) (5bits):

• Contains
C t i address
dd off the
th last
l t occupied
i d location
l ti
• It stores the address of the next instruction to execute in
case of a routine call
• Flags a full or an empty stack
ment
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• TOS register (Top-of-Stack):

ment
6. Data memory
• 4K static RAM 8 bits (registers).
• Organized in 16 banks of 256 locations -> BSR (Bank Select

Register)
• Contains:
• SFR (special function register) -> CPU status and control and
peripherals.
• GPR (General Purpose Register) -> for variables or data.
• Addressing modes: Direct, Indirect e Indexed.

Data memory
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Data Memory Bus
Address Memory Bus for the Data

memory
Bank Select Register
Indirect addressing
registers
Address field
of the
i
instruction
i
Data memory
Access Bank
95 first memory
locations in RAM
Memory
CPU registers and

peripheral control
Data memory
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SFRs for CPU and peripheral control

dir. registro dir. registro dir. registro dir. registro
FFFh TOSU FD7h TMR0H FAFh SPBRG F87h
FFEh TOSH FD6h TMR0L FAEh RCREG F86h
FFDh TOSL FD5h T0CON FADh TXREG F85h
FFCh STKPTR FD4h FACh TXSTA F84h PORTE
FFBh PCLATU FD3h OSCCON FABh RCSTA F83h PORTD
FFAh PCLATH FD2h HLVDCON FAAh EEADRH F82h PORTC
FF9h PCL FD1h WDTCON FA9h EEADR F81h PORTB
FF8h TBLPTRU FD0h RCON FA8h EEDATA F80h PORTA
FF7h TBLPTRH FCFh TMR1H FA7h EECON2 F7Fh ANSELH
FF6h TBLPTRL FCEh TMR1L FA6h EECON1 F7Eh ANSEL
FF5h TABLAT FCDh T1CON FA5h F7Dh IOCB
FF4h PRODH FCCh TMR2 FA4h F7Ch WPUB
FF3h PRODL FCBh PR2 FA3h F7Bh CM1CON0
FF2h INTCON FCAh T2CON FA2h IPR2 F7Ah CM2CON0
FF1h INTCON2 FC9h SSPBUF FA1h PIR2 F79h CM2CON1
FF0h INTCON3 FC8h SSPADD FA0h PIE2 F78h SLRCON
FEFh INDF0 FC7h SSPSTAT F9Fh IPR1 F77h SSPMSK
FEEh POSTINC0 FC6h SSPCON1 F9Eh PIR1 F76h
FEDh POSTDEC0 FC5h SSPCON2 F9Dh PIE1 F75h
FECh PREINC0 FC4h ADRESH F9Ch F74h
FEBh PLUSW0 FC3h ADRESL F9Bh OSCTUNE F73h
FEAh FSR0H FC2h ADCON0 F9Ah F72h
FE9h FSR0L FC1h ADCON1 F99h F71h
FE8h WREG FC0h ADCON2 F98h F70h
FE7h INDF1 FBFh CCPR1H F97h F6Fh
FE6h POSTINC1 FBEh CCPR1L F96h TRISE F6Eh
FE5h POSTDEC1 FBDh CCP1CON F95h TRISD F6Dh
FE4h PREINC1 FBCh CCPR2H F94h TRISC F6Ch
FE3h PLUSW1 FBBh CCPR2L F93h TRISB F6Bh
FE2h FSR1H FBAh CCP2CON F92h TRISA F6Ah
FE1h FSR1L FB9h PSTRCON F91h F69h
FE0h BSR FB8h BAUDCON F90h F68h
Data memory
FDFh INDF2 FB7h PWM1CON F8Fh F67h

FDEh POSTINC2 FB6h ECCP1AS F8Eh F66h
FDDh POSTDEC2 FB5h CVRCON F8Dh LATE F65h
FDCh PREINC2 FB4h CVRCON2 F8Ch LATD F64h
FDBh PLUSW2 FB3h TMR3H F8Bh LATC F63h
Industrial
FDAhElectronics
FSR2H System Design
FB2h TMR3L F8Ah LATB F62h 17
FD9h FSR2L FB1h T3CON F89h LATA F61h
FD8h STATUS FB0h SPBRGH F88h F60h
7. Peripherals
Peripherals
Data bus
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Data Bus
Peripherals
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Chapter 3 :
Programming a microcontroller.
Instruction set of the PIC18F45K20
1. Introduction
2. Instruction structure
3. Addressing modes
4. PIC18F45K20 instructions
5
5. Instruction size and duration PIC18K45F20
6. Addressing modes PIC18F45K20
7. Instruction structure PIC18F45K20
8. Operating codes PIC18F45K20
1. Introduction
• Programming a microcontroller -> To specify to the control
unit the sequence of actions to be made
• Related topics:
– Instruction coding:
• Control unit-> Synchronous sequential system
• Instruction -> Zeros and ones
• Numeric system -> Hexadecimal
– Abstraction level:
• How far are the instructions from the human language
• Programming languages
Introduction
Industrial electronic systems design 2
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• Machine language:
– Group of binary combinations assigned to an operating code
– Advantage ->
> Optimization of the number of instructions for a specific
task
• Execution time
• Program memory locations
– Disadvantages:
• Absolute memory locations necessary for programming
• Codes not easy to remember and removed from human language
Introduction
• Assembly language:
– Symbolic language. Each operating code has a symbol (mnemonic)
that makes it easier to remember
– Directly related with the instruction set of the processor
– Assembler -> Translates to machine language
– Related concepts:
– Source code -> Object code
– Relocatable code <-> Absolute code
– Assembler <-> Assembler + Linker
Introduction
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• Assembly language:
A program code maybe formed by the following elements separated by blank
spaces or tabulations:
– Program instructions
– Pseudo-Instructions (Directives).
Instructions for the coding process.
They are not executable code.
– Controls
Keywords for the assemble control.
They are not related to the code.
– Labels
They are names associated
Th i t d to
t code
d lines
li that
th t store
t the
th address
dd att which
hi h those
th lines
li are.
– Comments
Introduction
Assembler language example: Controls
Labels
Directives
Instructions
Comments
Introduction
Absolute machine code Assembler program

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• High level language:

– Language nearer to human language
– Programming methodologies ( Structured, object oriented)
– Microprocessor independent
– C
Compiler
il -> Optimizes
O ti i the
th machine
hi code:
d
• Memory size
• Execution time
Introduction
2. Instruction structure
Operation Operands
code (address)
It tells what is the object of the

It tells the micro what to do: operation:
• Data transfer Addressing modes
• Arithmetic
ih i or logic
l i
operations
Instruction structure
• Jumps or breaks
• Others
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3. Addressing modes
• It specifies where is the data with which operates.
• Effective address-> Data address specified by the addressing
mode.
• Several addressing modes -> Programa optimization
(Constants, Tables, lists, etc ).
• Modes:
- Implicit
- Immediate or literal
- Absolute
Ab l t o direct
di t
- Indexed
Addressing modes
- Relative
- Indirect
4. PIC18F45K20 instructions
- 75 basic + 8 (recursivity, program stack)
- High orthogonality (all hardware resources are accessed

the same way).
–Classification according to operands:

• BIT oriented
• Byte oriented
• Literal
• Sequence control
ns
PIC18F45K20 instruction
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5. Instruction size and execution time

(PIC18F45K20)
• Instruction types according to size:
 16 bits (single word instructions).
Instruction size and execcution time (PIC18F45K20))
 32 bits (double-word instructions)
• Instruction cycle (IC)-> 4 oscillator cycle. 4MHz -> IC=1us
• Execution time:
 16 bits instructions execute in one IC unless:
o Test instructions with p
positive result -> 2 IC.
o Instructions that change the PC -> 2 CI
 32 bits instructions execute in two IC unless:
o Test instructions with positive result -> 3 IC.
6. Addressing modes in the PIC18F45K20

4 addressing modes:
- Implicit
I li it (Inherent)
(I h t) :
NO operand.
Addressing modes in thee PIC18F45K20
- Literal (Literal) :
-> Immediate => Constants
-> Absolute => Absolute address
->
> Relative
R l ti => > relative
l ti jumps
j
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-Direct
->Absolute -> full 4 K address field
->Absolute page
A
According
di tot S bit in
i the
th instruction:
i t ti
• S=0 -> Access Bank
• S=1 -> BSR (Bank Select Register) -> 8 bit address
12 11 8 7 0
BSR Operand (7:0)
- Indirect
Indirect address (pointer)
FSR (file select registers)(0,1 o 2)

(12 bits registers –2
2 bytes size H and L)
L).
In order to use the indirect addressing mode the instructions

must refer to the following virtual register:
-INDFx -> The address is specified by the FSR content
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6. PIC18F45K20 instruction structure
Operation code Operands

n structure
What to do To whom
• Byte oriented:
• 2 or 4 byte size
operands
2 Byte
15 9 8 7 0
Operation code d a f
Result location:
d = “0” loads in WREG Register address
d = “1” loads in f Register location:
a = “0” in “Access Bank”
n structure
a = “1” BSR selected

4 Bytes
15 12 11 0
Opcode f -> registro fuente

15 12 11 0
1 1 1 1 f -> registro destino

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• Bit oriented
operands
15 12 11 9 8 7 0
Operation code bit a f

n structure
3-Bit address
Register address
R i
Register location:
l i
a = “0” in “Access Bank”

a = “1” BSR selected
• Immediate address
operands
15 8 7 0
Operation code k
n structure
Constant
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• Jump or sequence break instructions:

• Absolute address (20 bits)
15 12 11 7 0
Operation code Jump address(7:0)

15 12 11 0
1 1 1 1 Jump address(19:8)
“Fast” mode in jump or subroutine return:

n structure
s = “0” register contents are not stored

s = “1” register contents are stored
15 12 11 8 7 0
Operation code s Jump address(7:0)

15 12 11 0
1 1 1 1 Jump address(19:8)
• Jump or sequence break instructions:
15 11 10 7 0
Operation code Address jump(10:0)
15 8 7 0
n structure
Operation code Address jump(7:0)

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7. Classification according to operation code

5 groups:
n code
PIC18F45K20 Classification according to operation
• Memory/Register transfer
• Arithmetic operations
• Logic operations
• Jumps and sequence breaking
• Other
Register load/transfer opcodes:

Mnemonic and Machine code Status bits
operands Operation Cycles 15 0 C DC Z OV N
BCF f, b, a
Bit Clear f 1 10 0 1 bbb a f f f f f f f f
BSF f, b, a
Bit Set f 1 10 0 0 bbb a f f f f f f f f
n code
CLRF f, a Clear f 1 01 1 0 101 a f f f f f f f f x

LFSR f, k
, Move literal (12‐bit) 2nd word
( ) 2 11 1 0 111 0 0 0 f f k k k k
to FSR(f) 1st word 11 1 1 000 0 k k k k k k k k
MOVF f, d, a WREG=f (d=0); f=f (d=1) 1 01 0 1 00d a f f f f f f f f x x
MOVFF fs, fd Move fs (source) to 1st word 2 11 0 0 f f f f f f f f f f f f
fd (destination) 2nd word 11 1 1 f f f f f f f f f f f f
MOVLB k Move literal to BSR<3:0> 1 00 0 0 000 1 0 0 0 0 k k k k
MOVLW k Move literal to WREG 1 00 0 0 111 0 k k k k k k k k
MOVWF f, a Move WREG to f 1 01 1 0 111 a f f f f f f f f
POP ‐ Pop top of return stack (TOS) 1 00 0 0 000 0 0 0 0 0 0 1 1 0
PUSH ‐ Push top of return stack (TOS) 1 00 0 0 000 0 0 0 0 0 0 1 0 1
SETF f, a Set f 1 01 1 0 100 a f f f f f f f f
SWAPF f, d, a Swap nibbles in f 1 00 1 1 10d a f f f f f f f f
f -> Register address

a -> 0: f in Access Bank; 1: f in page selected by BSR
d -> 0: result loaded in WREG; 1: result loaded in f
k -> immediate
b -> bit selected for operation
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Arithmetic opcodes:
Mnemonics and Machine code Status bits
operands Operation Cycles 15 C
0 DC Z OV N
ADDLW k Add literal and WREG 1 0 0 0 0 1 11 1 k k k k k k k k x x x x x
ADDWF f, d, a Add WREG and f 1 0 0 1 1 0 1d a f f f f f f f f x x x x x
n code
ADDWFC f, d, a Add WREG and CARRY bit to f 1 0 0 1 1 0 0d a f f f f f f f f x x x x x

COMF f, d, a Complement f 1 0 0 0 1 1 1d a f f f f f f f f x x
DAW ‐ Decimal Adjust WREG 1 0 0 0 0 0 00 0 0 0 0 0 0 111 x

DECF f, d, a Decrement f 1 0 0 0 0 0 1d a f f f f f f f f x x x x x
INCF f, d, a Increment f 1 0 0 1 0 1 0d a f f f f f f f f x x x x x
MULLW k Multiply literal with WREG 1 0 0 0 0 1 10 1 k k k k k k k k
MULWF f, a Multiply WREG with f 1 0000 0 01 a f f f f f f f f
NEGF f, a Negate f 1 0110 1 10 a f f f f f f f f x x x x x
SUBFWB f, d, a Sub f from WREG with borrow 1 0101 0 1d a f f f f f f f f x x x x x
SUBLW k Subtract WREG from literal 1 0 0 0 0 1 00 0 k k k k k k k k
SUBWF f, d, a
f, d, a Subtract WREG from f
Subtract WREG from f 1 0101 1 1d a f f f f f f f f x x x x x
SUBWFB f, d, a Sub WREG from f with borrow 1 0101 1 0d a f f f f f f f f x x x x x

k -> immediate
Logic opcodes:

operands Operation Ciclos 15 0 C DC Z OV N
n code
ANDLW k AND literal with WREG 1 0000 101 1 k k k k k k k k x x

ANDWF f, d, a
f d a Add WREG and f
Add WREG and f 1 0001 01d a f f f f f f f f x x
BTG f, b, a Bit Toggle f 1 0111 bbb a f f f f f f f f

IORLW k Inclusive OR literal with WREG 1 0000 100 1 k k k k k k k k x x
IORWF f, d, a Inclusive OR WREG with f 1 0001 00d a f f f f f f f f x x
RLCF f, d, a Rotate Left f through Carry 1 0011 01d a f f f f f f f f x x x
RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01d a f f f f f f f f x x
RRCF f, d, a Rotate Right f through Carry 1 0011 00d a f f f f f f f f x x x
RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00d a f f f f f f f f x x
XORLW k Exclusive OR literal with WREG 1 0000 101 0 k k k k k k k k x x
, , Exclusive OR WREG with f
XORWF f, d, a 1 0001 10d a f f f f f f f f x x

k -> immediate
12
10/03/2016
Jumps and sequence break opcodes:

Unconditional jumps (PC = Jump effective address)
n code
Mnemonics Machine code Status bits

and operands Operation Cycles 15 0 C DC Z OV N
BRA n Branch Unconditionally 2 1 1 1 0 0nnn nnnn nnnn

GOTO k Go to address 1st word 2 1 1 1 0 1111 k k k k k k k k
2nd word 1111 k k k k k k k k k k k k
Bit 7 Bit 0
Bit 19 Bit 8
BRA -> Relative jump (PC)+2

n ->
> 2’s
2’ complement
l t ->
> 1024 ≤ n < 1023
Effective address = (PC) + 2 + 2*n
GOTO -> Absolute jump

k -> 0≤ k ≤ 1048575
Effective address <20:1> = k ; DE<0> = 0 (2MBytes)

Conditional jumps -> PC is loaded if the condition is true
Jumps in which the conditions are the Status bits
n code
Machine code
Machine code Status bits
Status bits
Mnemonics
Mnemonics
BC n Branch if Carry 1 (2) 1 1 1 0 0 0 1 0 n n n n n n n n
BN n Branch if Negative 1 (2) 1 1 1 0 0 1 1 0 n n n n n n n n
BNC n Branch if Not Carry 1 (2) 1 1 1 0 0 0 1 1 n n n n n n n n
BNN n Branch if Not Negative 1 (2) 1 1 1 0 0 1 1 1 n n n n n n n n
BNOV n Branch if Not Overflow 1 (2) 1 1 1 0 0 1 0 1 n n n n n n n n
BNZ n Branch if Not Zero 1 (2) 1 1 1 0 0 0 0 1 n n n n n n n n
BOV n Branch if Overflow 1 (2) 1 1 1 0 0 1 0 0 n n n n n n n n
BZ n Branch if Zero 1 (2) 1 1 1 0 0 0 0 0 n n n n n n n n
2 cycles if branch
Relative jump (PC)+2
n -> 2’s complement -128 ≤ n < 127
Effective address = (PC) + 2 + 2*n
13
10/03/2016

Break related to an instruction operand:
operands Operation Cycles 15 0 C DC Z OV N
n code
BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1 0 1 1 bbb a f f f f f f f f

BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1 0 1 0 bbb a f f f f f f f f
CPFSEQ f, a
f a Compare f with WREG skip =
Compare f with WREG, skip = 1 (2 or 3)
1 (2 or 3) 0 1 1 0 001 a f f f f f f f f
CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3) 0 1 1 0 010 a f f f f f f f f

CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3) 0 1 1 0 000 a f f f f f f f f
DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0 0 1 0 11d a f f f f f f f f
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0 1 0 0 11d a f f f f f f f f
INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0 0 1 1 11d a f f f f f f f f
INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0 1 0 0 10d a f f f f f f f f
TSTFSZ f, a Test f, skip if 0 1 (2 or 3) 0 1 1 0 011 a f f f f f f f f
In case of a break, the instruction can take 2
or 3 cycles depending on the following
instruction
instruction.
no Test yes Program
condition
Instruction 1 Break instruction
Instruction 1
Options:
Instruction 2 BRA
Instruction 2
GOTO

Subroutine call and return:
n code

CALL k, s Call subroutine 1st word 2 1 1 1 0 110s k k k k k k k k
2nd word 1 1 1 1 k k k k k k k k k k k k
RCALL n Relative Call 2 1 1 0 1 1nnn nnnn nnnn
RETFIE s Return from interrupt enable 2 0 0 0 0 0000 0001 000s
RETLW m Return with literal in WREG 2 0 0 0 0 1100 mmmm mmmm
RETURN s Return from Subroutine 2 0 0 0 0 0000 0001 001s
k -> 0≤ k ≤ 1048575 n -> 2’s complement from -1024 ≤ n < 1023
EA <20:1> = k ; EA<0> = 0 Effective address = (PC) + 2 + 2*n => PC
(2MBytes) => PC = DE
CALL => it stores the return address in the stack => TOS= (PC)+4
RCALL => it stores the return address in the stack=> TOS= (PC)+2
Return => PC = (TOS)

Option “FAST” (s=1) => in the call STATUS, WREG and BSR are stored
in a register stack. A Return reloads the stored value. Only 1 level.
14
10/03/2016
Other opcodes:

n code
and Operation Cycles 15 0 C DC Z OV N

CLRWDT ‐ Clear Watchdog Timer
g 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
NOP ‐ No Operation 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
NOP ‐ No Operation 1 1 1 1 1 x x x x x x x x x x x x
RESET Software device Reset 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x x x x x
SLEEP Go into Standby mode 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
8. Instruction set summary

Instruction set summary
15
10/03/2016

16
Chapter 4 :
Microcontroller peripherals
1. Introduction
2. Transfer control
3. Basic parallel I/O concepts
4. Parallel I/O in the PIC18F45K20
5. Peripheral connection examples
6. Basic timer structure
7. Timer/counter in the PIC18F45K20
8. Interrupts
9. Interrupts in the PIC
1. Introduction
• Data transfer
• Classification:
– How is it done:
• Parallel: as many lines as bits to transfer. High number of lines, high
speed, short distances. (< 15m).
• Serial: one line in which each bit is sent one after another. Slow,
longer distances, modulation.
– Transfer control:
• Processor which controls the transfer.
• Transfer synchronization:
– Synchronous transmission (clock)
Introduction
– Asynchronous transmission
Industrial Electronic Systems Design 2

2. Transfer control
• Two synchronous circuits have to synchronize
• Classification according to whom controls the transfer:
– Microprocessor controlled:
Transfer is made by the execution of instructions.
• Microprocessor initiated
– Synchronous
– Stop and wait
– Polling.
• Peripheral initiated:
– Interrupt.
– Peripheral controlled:
Transfer control
The microprocessor doesn’t execute instructions.

• Direct memory access (DMA).
3. Basic parallel I/O concepts
• Parallel output
• Basic-> D flip-flop
• Port -> A group of flip-flops
• Address selection
Data bus
Address bus
Processor Pi Address
Registe Register
r
Basic parallel I/O concepts
Address
Control signals circuit
Write
Peripheral Peripheral
Pi Pj
• Parallel input.
• Basic element -> Tristate buffer
• Input port -> Group of buffers
• Address selection
Data bus
Address bus
Processor Pi address
Basic parallel I/O concepts
Address
Control signals circuit
Read
Peripheral
Peripheral Pj
Pi
4. Parallel I/O structure in the PIC18F45K20
• 4 Ports of 8 bits and 1 of 4
bits terminals
• Multifunction
• 3 registers control the port:
• TRIS -> “1” -> Input;
“0” -> Output).
• PORT -> Read
Parallel I/O structure in the PIC18F45K20
• LAT -> Write
• They handle up to 25mA

(source or sink)

• Electrical characteristics:
• Terminal with diode to Vdd and Vss (overvoltage protection)
• Input:
- TTL compatible (VIL , VIH ,IIL ,IIH )
- Schmitt Trigger (ST) (option).
• Output (CMOS compatible ):

- VOLMax =0.6V, IOL = 8.5mA (Vdd=3V)
- VOHMin =Vdd-0.7V, IOH = -3mA (Vdd=3V)

PortA
• Bidirectional, 8 bits
• TRISA-> one bit for each terminal =>“1”I / “0”O.

• PORTA -> each bit shows what it is at the terminal (input)
• LATA-> each bit controls the voltage output. It can be read and
written.
• RA4 Schmitt Trigger input, TTL compatible others
• As CMOS output
• Multifunctional terminals:
• RA<3:0> y RA5 -> Analog inputs.
• RA<5:0> -> Capture and compare unit (CCU) I/O.
• RA4 -> TMR0 external clock
• RA6 y RA7 -> main oscillator
PortB
• Bidirectional 8 bits
• TRISB-> one bit for each terminal =>“1”I / “0”O.

• PORTB -> each bit shows what it is at the terminal (input)
• LATB-> each bit controls the voltage output. It can be read and
written.
- Input:
- Optional weak pull-up
- WPUB register to select the bit and RBPU bit from INTCON2 register to
activate it
- Output: CMOS

• RB<4:0> -> analog input (default value)
• RB<4:0> -> CCU outputs
• Interrupts:
- RB<2:0> (INT0, INT1, INT2) inputs
- RB<4:7> Interrupt on change of value of those bits

PortC
• TRISC-> one bit for each terminal =>“1”I / “0”O.

• PORTC -> each bit shows what it is at the terminal (input)
• LATC-> each bit controls the voltage output. It can be read and
written.
• Optional Schmitt Trigger
• Timers management (RC<1:0>)
• CCU (RC<2:1>)
• Serial communications (SPI, I2C,USART) (RC<7:3>)

PortD
• TRISD-> one bit for each terminal =>“1”I / “0”O.

• PORTD -> each bit shows what it is at the terminal (input)
• LATD-> each bit controls the voltage output. It can be read and
written
• Optional Schmitt Trigger
• CCU(CCP) (RD<7:5>)
• Parallel port

5. Peripheral connection examples
• Switch
Pull-up-less pin Pull-up pin
Vc Vc
PIC PIC
Vdd Vdd
R
RA1 RB1
PE PE
Vss Vss
Peripheral connection examples
Switch bouncing

• LED Vc
LED:
“0” activated R1 -VFmax -> 2,7V
PIC -IFmax -> 30 mA
Vdd
D
Terminal:
RD1 -VOHmin -> VDD- 0,7V
-VOLmax -> 0,6V
Vss -IOmax -> 25mA
If Vc =3,5V and IF=5mA
“1” activated Vc
Vc  VF  VOL 3,5  2,7  0,6
R1    40ohm
PIC IF 0,005
Vdd
V  VF (3,5  0,7)  2,7
R 2  OH   20ohm
R2 IF 0,005
RD2
D
Vss

• Loads connected to 220Vac
Buffer circuit:
+V
R1
220Vac
L
RD2
R1 R2
+V
R2
RD3
Circuit Circuit
1 2

6. Basic timer structure
• Impulse train generation:
– Frequency
– Duty cycle
– Modes
• Square wave.
• Pulse Width Modulation (PWM).
• Real time clock
• Synchronization:
– Modes:
• Precision in time.
• Connection time delay.
• Switch-off time delay.
• Interval timer
• Time measuring:
Basic timer structure
– Modes:
• Period.
• Frequency.
• Duty cycle.
• Phase.
Timer / Counter:
Data bus
RELOAD REGISTER
Ext Reload
control
Reload
OF Reload
control CONFIGURATION
control
REGISTER
Ext ON/
Counter OFF Overflow flag
Oscillator COUNTER
Ext signal
Basic timer structure
Int. signal Timer/Counter mode

7. Timers/Counter in the PIC18F45K20
• 4 timers (TMR0, TMR1 , TMR2 y TMR3).
• Up counter of 8 and 16 bits
• Programmable prescalers.
Timers/Counter in the PIC18F45K20
• CCU controlled
• Interrupt generated by the overflow (from FFFFh to 0000h)

(synchronization with software)

Timer 0 (TMR0)
• Up counter (Timer0 incrementing is inhibited for two instruction
cycles following a TMR0 register write.)
• Software selectable operation as a timer or counter in both 8-bit

or 16-bit modes
• Selectable clock source (internal or external)
• Dedicated 8-bit, software programmable prescaler
• Edge select for external clock
• Interrupt-on-overflow

TIMER0 BLOCK DIAGRAM (8-BIT MODE)
Prescaler select
Edge selection
External clock
synchronization
Timer/Counter
select
External pin Prescaler

(/256, /128, /64, /32
/16, /8, /4, /2)
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
• TMR0H is not the actual high byte of Timer0 in 16-bit mode; it
is actually a buffered version of the real high byte of Timer0
• TMR0H is updated with the contents of the high byte of Timer0

during a read of TMR0L

T0CON: Timer 0 control register
7 TMR0ON Timer0 On/Off Control bit
6 T08BIT Timer0 8-bit/16-bit Control bit, 1 = Timer0 is configured as an 8-bit timer/counter

0 = Timer0 is configured as a 16-bit timer/counter
Timer0 Clock Source Select bit
5 T0CS
1 = Transition on T0CKI pin, 0 = Internal instruction cycle clock (CLKOUT= fosc/4)
4 T0SE Timer0 Source Edge Select bit, 1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
3 PSA Timer0 Prescaler Assignment bit, 0 = Timer0 prescaler is assigned.

1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler,
2 T0PS2
Timer0 Prescaler Select bits:
111 -> 1/256 011 -> 1/16
1 T0PS1 110 -> 1/128 010 -> 1/8
101 -> 1/64 001 -> 1/4
100 -> 1/32 000 -> 1/2
0 T0PS0

8. Interrupts
• Asynchronous event that requires the attention of the microprocessor:
• Break from the execution program sequence in order to attend the interrupt
• Subroutine execution
• Transfer: Microprocessor controlled and peripheral initiated
• Response time ( Latency )
• Associated concepts:
• Interrupt detect
• Interrupt source identity
• Interrupt priority
• Interrupt inhibition
• Interrupt erasure
Interrupts

9. Interrupts in the PIC
• Vector identification:
• Vector 008h -> High priority Interrupt
• Vector 018h -> Low priority interrupt
• “high” can interrupt “low”
• Interrupt source identification-> Polling
• 3 bits associated to each interrupt

• Flag Bit -> event flag
Interrupts in the PIC
• Enable Bit -> interrupt enable

• Priority Bit -> interrupt priority

• Identification of interrupt source
• 4 -> Timer overflow(TMR0, TMR1, TMR2, TMR3)
• 3 -> External edge triggered terminal
• Parallel port write
• AD end of conversion
• 2 -> EUSART Tx and Rx
• 4 -> CCU
• Oscillator failure
• EEPROM/Flash writing end
• Collision on bus
• Low power detection

INTCON: Interrupt control register
GIE Global Interrupt Enable bit. When IPEN = 0: 1 = Enables all unmasked interrupts, 0 = Disables
7 all interrupts including peripherals. When IPEN = 1: 1 = Enables all high priority interrupts
/GIEH 0 = Disables all interrupts including low priority.
PEIE Peripheral Interrupt Enable bit. When IPEN = 0:1 = Enables all unmasked peripheral interrupts
6 0 = Disables all peripheral interrupts. When IPEN = 1: 1 = Enables all low priority interrupts
/GIEL 0 = Disables all low priority interrupts
5 TMR0IE TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt , 0 = Disables the TMR0 overflow interrupt
INT0 External Interrupt Enable bit
4 INT0IE
1 = Enables the INT0 external interrupt, 0 = Disables the INT0 external interrupt
RBIE RB Port Change Interrupt Enable bit

3 1 = Enables the RB port change interrupt, 0 = Disables the RB port change interrupt
TMR0 Overflow Interrupt Flag bit. 1 = TMR0 register has overflowed (must be cleared by
2 TMR0IF software), 0 = TMR0 register did not overflow
INT0 External Interrupt Flag bit, 1 = The INT0 external interrupt occurred (must be cleared
1 INT0IF by software), 0 = The INT0 external interrupt did not occur
RB Port Change Interrupt Flag bit(1), 1 = At least one of the RB<7:4> pins changed state
0 RBIF
(must be cleared by software), 0 = None of the RB<7:4> pins have changed state

RCON: Reset control register
7 IPEN Interrupt Priority Enable bit, 1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (Mid-Range Compatibility mode)
INTCON2: Interrupt control2 register

PORTB Pull-up Enable bit, 1 = All PORTB pull-ups are disabled, 0 = PORTB pull-ups are
7 RBPU enabled provided that the pin is an input and the corresponding WPUB bit is set.
External Interrupt 0 Edge Select bit,

6 INTEDG0
1 = Interrupt on rising edge, 0 = Interrupt on falling edge
External Interrupt 1 Edge Select bit
5 INTEDG1
External Interrupt 2 Edge Select bit

4 INTEDG2
3 - Unimplemented: Read as ‘0’

TMR0 Overflow Interrupt Priority bit

2 TMR0IP
1 = High priority, 0 = Low priority
1 - Unimplemented: Read as ‘0’
RB Port Change Interrupt Priority bit

0 RBIP
1 = High priority, 0 = Low priority
TEMA 5:
INDUSTRIAL COMMUNICATIONS
1.
1 Introduction
2. Elements of a communication system
3. Radio electric spectrum
4. Time vs. Frequency
5. Noise and communications
6
6. Analog and digital comm
communications
nications
7. Design considerations
1. Introduction
Introduction
1
Introduction
2. Elements of a communications system

• Source
– Analog or digital
– Voice
V i from
f 0 Hz
H to 3 Khz
Kh
– Hi-Fi music 20 Hz to 20 KHz
nications system
– Video 0 Hz to 4,2 MHz

• Transmitter
• Communications channel
Elements of a commun
– Air,
Ai cable,
bl fiber
fib optic,
ti etc…
t
– Modulation
• Process by which a signal adapts to the
transmission channel
2
• Receiver
• Modulation schemes
– E(t)= Ec sen(ct +  )
–= 2 f
• Bandwidth
– I = k t B, I information, k constant based in the
nications system
modulation process, t time y B channel bandwitdh

• Frequency division multiplexing
– Radio and TV
• Time
Ti di division
i i multiplexing
lti l i
– Digital communications
– Transponders
• Distortion
– Harmonic distortion
– Intermodulation distortion
– Non-linear frequency response
– Non-linear pphase response
p
– Noise
– Interference
nications system
• Digital vs. analog systems:

– Analog transmission:
• Infrastructure
• Better use of bandwidth
– Digital transmission:
• Better against noise and distortion
• Compression and security
• Amplifiers vs. repeaters
3
3. Radio electric spectrum
Radio electric spectrum
m
v=f
Radio electric spectrum
m
4
4. Time vs. frequency
• Any signal can be represented in time or in frequency

• Fourier series
– A periodic signal can be represented as the sum of a number of sin-s or
cos-s at multiples of the base frequency
Time vs. frequency

Time vs. frequency
5
• Fourier series are only valid for periodic signals
• Real communications signal are not periodic but transient
• Fourier transform
• It can be considered a generalization of the series
• It gives us the frequency representation of a transient signal
Time vs. frequency
Fourier Transform
• V(t) has a finite number of max and min in a finite time

Time vs. frequency
• V(t) has a finite number of finite discontinuities in a finite time

• V(t) must be absolutely integrable
6
• Filtered signals
– Real bandwidth is alwaysy limited
– Limited bandwidth distorts signals
– Often this kind of distortion is not important because high
frequency components are small
– In practice, bandwidth and distortion require a compromise,
for example, voice in POTS
Time vs. frequency
5. Noise and communications
•Noise
– Random variations that alter communications
– It cannot be avoided
•External noise
– Equipment
– Atmospheric
Noise and communicattions
– Spatial
•Internal noise: thermal, shot, partition, pink, transit-time
noise
7
•Thermal or white noise
– It is produced by the chaotic movements of electrons in a
conductor due to heat
– Equal value at all frequencies
– PN =kk T B,
– PN noise power in watts
– K Boltzmann constant 1,38 10-23 J/K
– T temperature en K
– B bandwidth in Hz
– Solution: reducing either T or B or both

– Noise voltage
– P=V2/R,
– VN=2VL=2(kTBR)
•Shot noise IN= 2qI0B

It is also equal
q at all frequencies
q
– Characteristic of active devices

– IN noise current RMS
– Q magnitude of the charge of an electron 1.6 10-19 C
– I0 dc bias current in Amperes
– B bandwidth
•Partition noise
– Characteristic of three terminal devices
8
• Signal-to-noise ratio
• This ratio is more important than the noise absolute value
• Noise figure
•Equivalent noise temperature

– Teq = 290 (NF – 1)
9
• Cascaded amplifiers
– Friis
Friis’ formula
6. Analog and digital communications

mmunications
Analog and digital com
10
mmunications

mmunications
11
mmunications
Channel capacity
• Shannon-Hartley theorem
– C = 2 B log2 M
• C: information capacity in bits per second
• B: bandwidth in Hz
mmunications
• M: number of levels transmitted

• Shannon limit
– C = B log
og2 ((1 + S/N)
• C: information capacity in bits per second

• B: bandwidth in Hz
• S/N: signal-to-noise ratio (as a power , not in decibels)
• Log2 N= log10 N / log10 2
12
• Bit is the amount of information of a symbol of ½ probability
• Bit rate is the transmission rate in bits pper second
• Symbol is an element of a source alphabet. For instance, an
ASCII symbol or a symbol from a pass-band simulation
mmunications
• A symbol can be represented in bits

• Symbol rate or baud rate is the transmission rate in symbols
per second
• Message is sequence of symbols
7. Design considerations
• Transmission rate: time and bandwidth related
• Transmission medium: type of modulation
• Base Band base: dedicated line
• Pass band: wireless, non-dedicated media
• Transmission quality
• SNR
• Signal power
• Communication types
• Analog
Design considerations
• Digital
• Synchronous/asynchronous
• Serial/paralell
13
Andrés Augusto Nogueiras Meléndez – aaugusto@uvigo.es
Design of Industrial Electronic Systems
Introduction to Power Electronics
Rev. 2020-02-28
What is Power Electronics?
●
Electrical
Engineering
– Electronics
– Power
– Control
●
Joining these
disciplines is
Power
Electronics
Design of Industrial Electronics Systems 2

What is Power Electronics?
●
Power flowing,
in a controlled
fashion,
through a set of
Electronics
devices, with
high efficiency

What is Important in Power Electronics?
●
Efficiency is the most important parameter when
evaluating power electronics circuits among them

●
Efficiency is the most important parameter when
evaluating power electronics circuits among them

●
There is no power electronic converter without control

●
Efficient power electronic converters are always made with
switching semiconductors → the faster, the better

●
Efficient power electronic converters can include any kind
of electronic components

●
Efficient power electronic converters only include some
electronic components

How complex can the PEC be?
●
Complexity is determined by the application and the
control circuits capacity

How are Power Converters Clasified?
Rectifiers
DC AC
SMPC Frequency
( buck Changer
boost
etc.) Cicloconverters
DC AC
Inverters

How Power Converters Operate?
I+
Positive
Inverter
Source
Load
Load
Returns
Consumes
Energy
II I Energy
V‒ V+
Negative III IV
Inverter
Source
Load
Load
Returns
Consumes
Energy
Energy
I‒

Linear Regulators
Rev. 2020-02-28
Index
●
Introduction
●
AC Recitifiers
●
Filtering
●
Linear Regulators
Design of Industrial Electronics Systems

Introduction to Linear Power Sources
●
The vast majority of electronic circuits need one or more power sources,
providing different levels of dc voltage for operational purposes
●
Power obtained from batteries
– High cost
– Limited operational time
– Accepted when the power demand is low or during short periods of time
●
Power obtained from the grid (conventional or smart)
– It's the most frequent primary source
– Alternating voltages with different levels and frequencies
– A circuit is needed to transform grip power into dc voltage

Introduction to Linear Power Sources
●
Time line
– 1970: linear regulators, big size power sources
– 1980: first switchmode regulators, small size for the same power, first
issues with electromagnetic noise
– 1990: faster MOSFET transistors, resonant converters, more issues with
EMI, IGBT transistors, more integrated circuits for power sources on the
market
– 2010: SiC transistors are introduced, facing new opportunities
●
Linear regulators are used mainly in applications where noise levels
(undesired harmonics) are important on the power distribution

Linear Power Sources
●
Voltage transformation: change the AC voltage level to a more convenient
●
Rectifiying: transform alternating electrical current (AC) into direct
electrical current (DC)
●
Filtering: reduce the output voltage ripple, so it is more close to ideal DC
●
Regulation: control the output voltage, when changes occur in the input
voltage level, on the load or in the temperature
●
Isolation: electrically separate the input and the output of a power source.
Not to be confused with insulation.

Linear Power Sources
●
Transformer: the purpose is to change voltage level from the AC line to a
more appropriate level
●
Rectifier: change AC voltage from the secondary side of the transformer to
a pulsating positive voltage
●
Filter: passive elements to attenuate the pulsating rectified voltage, so it
becomes closer to a DC voltage
●
Voltage Regulator: active circuit to keep the output voltage constant when
the input voltage changes, or when the load changes, or when the
operating temperature varies

Linear Power Sources - Rectifiers
●
Half wave rectifier with a resistive
load
●
Use Fourier transform to analyze
the output voltage
●
DC = average value
●
AC = Sum of sine and cosine
terms
●
Efficiency of the rectifier
●
Ripple Factor of the output wave

●
Half wave rectifier with a resistive
load
Vm
V DC = π
V ∞
2V
V AC = sin ( ω t )− ∑ cos ( n ω t )
2 2
n=2, 4 … ( n −1 ) π
P DC
η= ≈0,405
P AC
2 2
RF=
√ V AC −V DC
≈1,21
V DC
●
Full wave rectifier from a center
tap transformer with a resistive
load
●
Bigger transformer and less
voltage drop in diodes
●
Full wave rectifier with a diode
bridge and resistive load
●
Smaller transformer and double
voltage drop in diodes

●
Both produce the same output
voltage

●
And the same output voltage
implies that
2Vm
V DC = π
4V 4V 4V
V AC =− cos ( 2 ω t ) − cos ( 4 ω t ) − cos (6 ωt )−…
3π 15 π 35 π
P DC
η= ≈0,8105
P AC
2 2
RF=
√ V AC −V DC
≈0,483
V DC
Linear Power Sources - Filters
●
The rectified voltage is not DC, it is a pulsating voltage with a single
polarity
●
The load should only receive DC, thus the need for a filter
DC should pass
AC should not pass

●
Possible solutions
– A series element that has high AC impedance and low DC impedance
f =0 Hz ⇒ X L=0[Ω]
X L= j ω L= j2 π f L
f =high ⇒ X L =∞ [Ω]

●
Possible solutions
– A parallel element that has low AC impedance and high DC impedance
1 1
X C =− =−
jωC j2 π f C
f =0 Hz ⇒ X C =∞[Ω]
f =high ⇒ X L =0 [Ω]

●
Possible solutions
– A parallel element that has low AC impedance and high DC impedance
– A combination of both

Linear Power Sources – Capacitor Filter
●
Most common solution
●
This solution avoids the use of heavy and voluminous inductances for low
frequencies ~ 50 Hz to 400 Hz
●
Complex analysis
– Non linear behavior (due to diodes)
– It is not possible to apply the superposition principle
●
Output voltage can be modeled as a combination of sinusoidal and
exponential functions

●
In order to solve this, a linear approach is made of the output voltage
●
The discharge ratio of the output voltage is considered constant, as
RC>>T/2
●
Also it is accepted that the capacitor charges instantaneously
●
The ripple voltage (Vr) is often specified (given) as a requisite of the circuit
that is the load

● VO average value is known

●
The ripple voltage (Vr) is often specified as a requisite
● RL is also known (the load circuit)
VO IO VO IO
V r= = ⇔ C= =
2 f RLC 2 f C 2f R L V r 2 f V r

●
The ripple voltage (Vr) decrease as the output capacitor increases
●
As consequence, the diodes operates during shorter times
●
And the input current peak increases

Voltage Regulation
●
The system made of a transformer, a rectifier and an output filter can be considered a power source
of constant output voltage if
– The load does not consume too much current
– The load is not sensitive to network and / or load variations
●
In order to achieve a better output voltage quality a linear regulator can be included
– Stability can be improved by means of an electronic device (often a Zener diode)
– There is no control loop (no feedback)
– Operation is based on clamping of the output voltage

Voltage Regulation
●
The linear regulator circuits have some limitations
– The precision of the output voltage is directly dependent on the characteristics of
the electronic devices used
– They need a control loop to compensate the possible variations due to load and
semiconductor variations
●
Linear Regulators → keep the output voltage constant
– They have a feedback loop for this purpose

Voltage Regulation
●
The are two kinds of regulators: parallel (shunt) and series
– The first drains a current in parallel to the load
●
Zener regulator and Shunt regulator
– The second drops a voltage in series with the load
●
This is the widely adopted topology

Block Diagram of a Linear Regulator

●
Reference of Voltage
– Provides a constant voltage reference (temperature and input voltage stabilized)
– A circuit based on Zener diodes is used
– Simples solution: Zener diode and resistor

●
Output Voltage Sample Circuit
– Provides a signal proportional to output voltage
– It is usually build by a voltage divider, that samples output
voltage

●
Error Detector (Error Amplifier)
– Compares the sampled output voltage with the
reference voltage, and then adjust the control element
behavior
●
Control Element (Series Regulating Device)
– Receives a control signal from the error detector to be more or less
conductive
– It is often a NPN transistor connected between the input and the output of
the regulartor

Linear Regulator Circuit
Control
Element
Error
Amplifier
Voltage Voltage
Reference Sampling

Linear Regulator – Voltage Reference
●
Simple circuit
● Choosing RZ wisely to
neglect the effect of input
ripple
●
Can be replaced by more
complex and stable
circuits

Linear Regulator – Voltage Sampling
●
Simple circuit
●
Current through resistors
should be negligible
compared with the load
current ⇒ R1 and R2 should
have higher value than
load

Linear Regulator – Voltage Sampling
●
Simple circuit
●
Current through resistors
should be negligible
compared with the load
current ⇒ R1 and R2 should
have higher value than
load
●
If output voltage should be
adjustable, then a
potentiometer can be
added

Linear Regulator – Error Amplifier
●
Powered from a non regulated
source
●
Must have an internal regulation
circuit to be unaffected of
external power variations
●
The output voltage range is
limited to input voltage minus
the semiconductors drop
●
To guarantee that the EA
operates properly
– VO(EA) < VCC – 2V
– Vi > VO + VBE + 2V

Linear Regulator – Control Element
●
Works always on active
region
●
Acting as a controlled
resistor

●
Works always on active
region
●
Acting as a controlled
resistor
●
The base current needed
on the transistor is
provided by the error
amplifier
IE VO I O (max)
I B= ≈ β⩾ −1
β +1 ( β +1)R L I B(max)

●
If the output current is high,
then a Darlington pair is used
●
The control element (the
transistor) should withstand
– The maximum output
current
– The maximum voltage
drop between input and
output
– The power dissipation to
these two conditions
simultaneously

Example of Linear Regulator

Efficiency of a Linear Regulator
I O≈ I i
●
This converter can only provide an output V O⋅I O
voltage that is lower that the input η =
voltage V i⋅I i
VO V i −V CE
●
Efficiency is directly related with input η ≈ ≈
voltage Vi Vi

Overcurrent Protection
●
When the IL current is high enough then
● If IL < IL(max) then the output voltage the Q3 transistor enters in active region,
remains constant with a VO value “stealing” current from the error amplifier,
and thus limiting Q1 and Q2 base current.
● If IL > IL(max) then the output voltage ●
This way, the output current becomes
drops, even taking a zero value smaller.
● 0 < V < VO(nom)
O
●
The maximum output current is fixed by
●
If the output is shortcircuited, then the R3 value
● P ≈ IL(max) · Vi
O
V BE 3(on)
I O (max)=
R3
Overcurrent Protection – Foldfack Circuit
● State of transistor Q3 is now determined

●
This circuit allows two effects: not only by the output current (R3), also
●
Limit the output current by the output voltage (R5 and R6)
●
Limit the voltage drop across the ●
At low output current, the current-limit
control element, thus reducing transistor Q3 is cutoff
the power dissipation (heat
generation)
● Any increase in IL will increase the voltage
across R3 and R5, and Q3 will progressively
be turned on.

Integrated Linear Regulators
●
Use of regulator circuits in AC/DC converters (power sources)
●
The first generation was made with general application components (discrete)
●
Increase of demand for specific applications (TTL circuits = +5V) made
possible build integrated regulators with just three terminals
– Low cost and easy to use in any system
●
Some time later, adjustable linear regulators were implemented in similar
fashion
– Low cost, easy to use in any system and more felxibility
●
Integrated Linear Regulators can be classified as
– Regulator ICs of multiple terminals
– Regulator ICs of three terminals
– Fixed output voltage: positive and negative
– Adjustable output voltage: positive and negative

Three Terminals IC Linear Regulators
●
Three terminals single IC with all
elements to obtains a regulated DC
voltage
●
Practical, simple and cheap way to
have DC power sources
●
Two big groups
– Fixed output voltage, that can be IN OUT
positive or negative GND
– Adjustable output voltage, that IN OUT
can be positive or negative ADJ

●
IC Regulators from series 78XX
provide posive voltages and
series 79XX provide negative
voltages
●
Last two digits indicate the
value of output regulated
voltage
●
Many manufacturers provide
these parts under different
codes
– LM78XX → National
Semiconductor, Fairchild
– UA78XX → Texas Instruments
– MC78XX → ON
Semiconductors

●
IC Regulators have all the
functions needed to provide
constant DC output voltage,
plus
●
Output current limitation, and
consequently, power
limitation
●
Thermal protection → the
element can be powered off
to provide protection
●
Internally compensated error
amplifier
●
A highly stable and low noise
voltage reference circuit

Three Terminals IC Linear Regulators Encapsulates

Three Terminals IC LR Electrical Characteristics

Three Terminals IC Positive Linear Regulators
Positive Regulators
●
No external component is to be
disregarded or omitted
●
The source can be from a
previously regulated source or
from a non regulated source
●
The input voltage must be
between 2 to 3 volts higher than
the output voltage. This requisite
is provided by the manufacturer

Three Terminals IC Positive Linear Regulators
Protects the regulator Protects the regulator if

from C2 discharge if the the output voltage
source VI fails reverses
Only needed if the Keep the output

source is far from steady when load
the regulator changes occur

Three Terminals IC Negative Linear Regulators
Series 79XX
●
Similar to series 78XX, but for negative voltages
●
Input capacitor C1 and output capacitor C2 are mandatory for stable operation
●
Another capacitor can be placed in parallel with the load, very close, to increase
regulation stability
●
All capacitors must be closest as possible to the integrated circuit

Linear Regulators

Linear Regulators

Linear Regulators – Symmetric Voltage Source

Linear Regulators – Increase Output Current
Increase the output current of the circuit
●
Adding a transistor and a resistor
●
The transistor provides almost all the current to the output
●
The linear regulator keeps the output voltage constant
●
The voltage gap between the output and the input is increased
● Vgap = V + voltage of the regulator
EBQ1

Linear Regulators – Increase Output Voltage
R2
V O =V O r
( )
1+
R1
+I Q⋅R 2 V O =V O r +V Z
Increase the output voltage of the circuit
●
Adding an external sampling network
●
It is mandatory to let the quiescent current flow (~ 8,5 mA)

Linear Regulators – High Input Voltage
If the input voltage is higher than the maximum at the regulator input
●
Generally for the LM series, the maximum voltage is around 35 V (for 79XX, -35 V)
●
The input circuit is a regulator before the input
● This solution can also be used to reduce heat dissipation on the IC, even when V < V
I Imax

Adjustable IC Linear Regulators
Basic Characteristics
●
The resistive sampling network is not
integrated, as it is in the fixed ones
●
The output voltage value is
stablished by external addition of two
resistive elements connected at the
Adj terminal
●
The quiescent current should return
through the output, so this must be
allowed
●
A minimum amount of output current
is needed for correct operation
●
It should be at least a few mA

Vo(min) Vo(max Io(max) Io(min) Iadj(min) (Vi-Vo)min (Vi-Vo)max

[V] ) [V] [mA] [mA] [mA] [V] [V]
500
LM317 1,2 37 1000 3,5 0,1 3 40
1500
LM350 1,2 32 3000 3,5 0,1 3 35
LM338 1,2 32 5000 3,5 0,1 3 35
500
LM337 -1,2 -37 1000 2,5 0,1 -3 -40
1500
LM333 -1,2 -32 3000 5 0,1 -3 -35

Basic Usage
●
Add the resistive sampling network at the
output of the circuit
● The minimum current I implies a
adj
maximum value for R1
●
Worst case scenario: when there is no load
●
All current from regulator flows through the
resistors
●
A minimum output current of 10 mA is
mandatory
●
Less output current implies higher output
voltage
● Under normal conditions, I is depreciated
adj
R2
V O =V REF
( )
1+
R1
+I A⋅R2

Adjustable IC Linear Regulators – Circuit
Protects the regulator Allows the discharge of

from CO discharge if the Cadj if the output voltage
source VIn fails decreases or if the output
is shortcircuited
Only needed if the Keep the output

source is far from Minimizes the output steady when load
the regulator voltage ripple changes occur

Linear Regulators - Conclusions
●
Few components
●
Reliable and robust
●
No EMI problems
●
Low efficiency
●
Bulk and heavy
Recommended Examples and Exercises
●
Chapter 15 - Electronics Devices and Circuits Theory,
Boylestad and Nashelsky
– Examples 15.8, 15.9, 15.10, 15.12, 15.15
– Exercises 19, 20, 21 and 22

AC to DC Converters
(Rectifiers)
Rev. 2020-03-08
Index
●
Introduction
●
Single Phase Half Wave Circuit
●
Fourier Transform - Harmonics
●
Single Phase Full Wave Circuit
●
Three Phase Rectifiers
●
Multiple Phase Rectifiers

Classes of AC / DC Converters
Single phase
Three phases
Uncontrolled
Semicontrolled
Controlled
Diodes
Thyristors
MOSFETs
IGBTs
Control can be
Analog
Digital
Output Filter

Classes of AC / DC Converters
Rectifier
Rectifier and Inverter = Power can flow in both directions
+V +V +V
I I IV I
+I +I +I
-I -I -I
II III II
-V -V -V

Fourier Series
∞
f (t)=a0 + ∑ [ an cos ( n ω0 t ) +bn sin ( n ω 0 t ) ]
n=1
T
2
1
a0 =
T
∫ f (t )dt
T
−
2
T
2
2
an =
T
∫ f (t )cos ( n ω 0 t ) dt
T
−
2
T
2
2
bn =
T
∫ f (t)sin ( n ω 0 t ) dt
T
−
2

Fourier Series
∞
f (t)=a0 + ∑ C n sin ( n ω 0 t + θ n )
n=1
2 2
C n= √ a n +bn
an
θn =tan
−1
( )
bn
a0 is a constant that is the average value of f(t) and represents a dc voltage or current
C1 is the amplitude of the term at fundamental frequency ω0
C2, C3,… are the amplitudes of the harmonics that have frequency 2ω0, 3ω0,...

rms Values
●
The root mean square value of f(t) can be computed from
the Fourier series:
2
Cn
√
∞ ∞
F rms =
√∑ F
n=0
2
n ,rms
2
= a +∑
0
n=0
( )
√2

Single Phase Rectifier with Resistor Load
V V
vO (t)=
{
V m sin ω t
2V ∞
0 <t <
T
2
<t <T
1
2
v O (t )= πm + m sin ( ω t ) − π m
2
∑
n =2,4,6. ..
( (n−1)⋅(n+1)
cos (n ω t)
)
+V
I
+I
-I
-V
2 2
Vm I m⋅R V 2m I 2m⋅R
PO =P avg=V avg⋅I O = = P I =P rms =V rms⋅I rms = =
π 2⋅R π2 4⋅R 4

vi
vO
iO
+V
I pO
+I
-I
-V
PO PO Pi
η= = ≈40,52 % PF= =0,707 RF=121 %
P i P rms S

Single Phase Rectifier with RL Load

Single Phase Rectifier with RL Load
●
This circuit signals are
not easy to solve by
analytical means
●
The equations involve
a steady state
equation and a
transient state
equation combined
●
Solved by numerical
methods (simulations)

Single Phase Rectifier with RL Load and Vdc

The Freewheeling Diode



The Freewheeling Diode – L/R → ∞

The Freewheeling Diode – L/R → ∞

Full Bridge Rectifier

V
Vpm
V/I
Vsm
IOm
2
V O = π ⋅V sm
t
V D( peak )=−V sm PO


Full Bridge Rectifier with Inductive Load

Full Bridge Rectifier with High Inductive Load
4 1 1 1
[
i s (t )=I O⋅π sen ω t + sen 3 ω t + sen 5 ω t + sen 7 ω t +…
3 5 7 ]

Full Bridge Rectifier with Capacitive Filter

Full Bridge Rectifier with Capacitive Filter
V m⋅π Vm
Δ V O≈ =
ω RC 2f RC
1
C≈
2 f R V m /Δ V O


Three Phase Rectifier

Three Phase Rectifier

Three Phase Rectifier - Currents

Multiphase Rectifiers
●
Using the same topological ideas of three phase rectifiers,
multiphase circuits can be derived

Selection of the Multiphase Rectifier
●
Type and demands of the load
●
Power of the full system (input, output and efficiency)
●
Available rectifier devices
●
Degree of electrical protections
●
Cost of implementation and operation
Number of Uo/Umx
phases
2 0.64
3 0.83
6 0.95
12 0.989
20 0.996

Selection of the Multiphase Rectifier
Efficiency of the n η (%)

rectifier vs the 2 81.05
number of phases
3 96.8
6 99.8
12 99.989
20 99.9989
Use factor of the n FU

associated
transformer vs the 2 0.573
number of phases 3 0.664
6 0.551
12 0.404
20 0.312

Association of Rectifiers - Series

Association of Rectifiers - Parallel

Association of Rectifiers – Series / Phase Shifted

Losses in Rectifiers
●
Resistive losses due to real conductors
●
Losses in the transformer
– Losses in the cooper windings
– Losses due to parasitic currents in the iron core
– Can be reduced if better design and construction
techniques are applied, but the cost is higher
●
Losses in the semiconductors, as the threshold voltage
drop is higher in power devices
●
Losses due to the non ideal switching of semiconductors

Recommended Lectures and Exercises
Power Electronics - Daniel W. Hart
Chapter 3: Half-Wave Rectifiers + The Basics of Analysis
Examples 3.01, 3.02, 3.05, 3.06, 3.07 and 3.08
Exercises at the end of the chapter that matches previous examples
Chapter 4: Full-Wave Rectifiers + Converting ac to dc
Examples 4.01, 4.03, 4.04, 4.08 and 4.12
Exercises at the end of the chapter that matches previous examples

AC to AC Converters
(AC Controllers, Cycloconverters)
Rev. 2020-03-08
Index
●
Introduction and Classification
●
AC Switches
●
AC Regulators
●
Cycloconverters

Can change
Individually
Voltage
Frequency
Both simultaneously

AC/AC Converters - Definitions
AC / AC Converter
AC power, mono or three phase AC power, with different voltage and /

or frequency and / or phase
Two different converters, depending on the output frequency
●
Equal: AC voltage controllers
●
Different:
●
AC inverter (higher or lower frequencies)
●
Cycloconverter (only lower frequencies)
If the input frequency is lower than the output
Rectifier CL Inverter

Controlled Rectifier
●
By means of use of a controlled rectifier = SCR, thyristor

Controlled Rectifier

Full Controlled Single Phase Rectifier

Full Controlled Single Phase Rectifier

On – Off Control - Principles
Can change the

amount of cycles that
are transferred from
the input to the output
Applied on systems with

a high mechanical or a
high thermal time
constant

●
Two controlled interrupters, in parallel, in opposite
directions


The input voltage can be described by
v S=V m sen ω t
If the interrupter conducts current during an

integer number (n) of cycles. Then it is off
during another integer (m) number of cycles.
The rms output voltage is described by
Vmn Vm
V o [rms ]= ⋅
√
= ⋅√ k
√ 2 n+m √ 2
k is the ratio between the number of on and total

(on + off) cycles

√ n+m
=√ k
13
Phase-Control Method
● The power flux is controlled by delaying the fire angle of the thyristor T 1
● The control range is limited by the presence of D1

● The output voltage (rms) can only varies between VS and VS / √2

●
The voltage and current are not symmetric → there is a DC voltage level → saturation
of the magnetic components → not used

1
1 sen 2 α √2 V S
V O (rms)=V S
[ (
2π
2 π−α+
2 )] 2
V O (dc )=
2π
( cos α−1 )

Bidirectional Phase-Control Method
●
To avoid the problems derived from the non zero average
(dc) input current, a bidirectional control (full control)
should be used

●
There are specific thyristors designed for this kind of
applications → higher currents and voltages

●
Lights control on monophasic equipments
●
Regulation (compensation) of reactive power
●
Low speed control for big AC motors

●
Trigger of thyristors must always be
symmetric
●
Trigger circuits must be isolated among
them, due to the coincidence of anodes and
cathodes
1
1 sen 2 α
V O (rms)=V S
[(
π π−α+ 2 )] 2

Common-cathode bidirectional full wave switch
●
Makes the trigger circuit simpler, as can be the same for both thyristors (common cathode)
●
The switch efficiency is lower, as the voltage drop is the sum of two semiconductors

Single Controlled Switch
●
The trigger circuit is different is a thyristor or an IGBT is used
●
The efficiency of the switch now is even lower, as three semiconductor are involved in each
conducting path


●
The trigger pulses must always be symmetric
●
The load current will be positive and
negative
●
The current through the controlled switch is
always positive

Bidirectional Phase-Control Circuit with Inductive Load
●
The trigger pulses must always be
symmetric → avoid DC current
●
The trigger circuits must be isolated
among them, due to the connection of
anodes and cathodes

●
The thyristors will drive positive
current as reversed biased
●
Can’t place freewheeling diodes

●
The β angle can only be found by
successive approach methods or by
simulations
●
Once the β value has been found, it is
possible to find the other voltages and
currents in the circuit


Single-Phase Transformers Tap Changers

Single-Phase Transformers Tap Changers
Output voltage applied to the RL load could be
• V1
• V1 + V2

Cycloconverters
Allows, with a simple combination of two back-to-back converters, convert one

AC source into another, with different RMS and frequency values.
Both, RMS and frequency, are lower than the original.
Positive Converter Negative Converter
L
o
a
d

Cycloconverters
Allows to convert one AC source into another, with different RMS and
frequency values

Cycloconverters
Allows to convert one AC source into another, with different RMS and
frequency values

Three-Phase Cycloconverters



AC PWM Control
Positive
Half-cycle
freewheeling

AC PWM Control
Negative
Half-cycle
freewheeling

AC PWM Control

AC Control – Matrix Converters
●
All switches are bidirectional
●
Converts directly AC to AC

AC Control – Matrix Converters
●
Any input phase can be connected, at any given instant, to one of the
phases of the load → The voltage can be chosen from the input

●
Power Electronics – Circuits, Devices and Applications,
Muhammad Rashid
●
Chapter 6 – AC Voltage Controllers
●
Examples 6.1, 6.3, 6.8 and 6.9
●
Problems similar to the examples

DC to AC Converters
(Inverters)
Rev. 2020-03-27
Index
●
●
Principle of Operation
●
Monophasic Inverters
– Half Bridge
– Full Bridge
●
Three Phase Inverters
●
Control of Monophasic Inverters

The output is an
alternating current,
generated with the
desired
voltage
and
frequency
The source is a and both can be changed
continuous voltage or
current source

Semiconductors
Diodes (as auxiliary

devices)
MOSFETs
IGBTs
Thyrisitors
The source is a
current source

Fast frequency and

low/middle power (up to
10 KVAr)
Diodes (as auxiliary

devices)
MOSFETs
IGBTs
The source is a
current source

Single phase inverters

●
Square wave
●
Resonant
●
Voltage or Current
Applications
AC motors control of
speed and/or torque
Uninterrupted Powers
Sources
The source is a Electronic Lightning (CFL)

current source Three phase inverters are
derived from SPI

IAC L UAC
IAC
UL
Inverter
UAC UR
UDC + R
Filter
UAC Autonomous Inverter

IAC Could be operated in the four quadrants without
restrictions in frequency
During certain moments, power flows from the
t source to the load
During other moments, power should flow from
the load to the source
PAC
Non autonomous inverter
The electrical network is the load (power → ∞)
Frequency is stablished by the grid
t A controlled rectifier with α > 90º.


Energy Source
DC Voltage

The capacitors helps create a voltage

divider and with the switching
current peaks

Resistive Load

Top Switch and

Freewheeling diode

Bottom Switch and

Freewheeling diode

Freewheeling diodes
for inductive loads

Principle of Operation – Semiconductors
All capacitors are fully loaded, at half the input

voltage


voltage
The sequence is
Turn on Q1


voltage
The sequence is
Turn on Q1 – Turn off Q1

Dead Time


voltage
The sequence is

Dead Time
Turn on Q2


voltage
The sequence is

Dead Time
Dead Time

Operating frequency is fO = 1/TO
Current from the DC source is continuous, never

is interrupted
If there are dead times, then the current is non iS

continuous
VS
2R
t
Current from the DC source is always positive,

despite voltage applied to the load changes
from positive to negative, and from negative to
positive
This circuit is known as half-bridge inverter iS
VS
2R
t
The RMS output voltage is

VS
V O=
2
The output voltage (instantaneous) is
∞ 2V S This analysis is only valid for resistive
vO= ∑ nπ
sin ωt loads. Vast majority are inductive!
n=1,3,5. ..

If the operational frequency is
L
T O / 2≫
R
and the load is highly inductive, the current
through is almost sinusoidal
First Q1 is on, between θ1 y TO/2

The current increase from 0, at first exponentially
and then in a sinusoidal manner

Principle of Operation - Semiconductors
The Q1 switches off at TO/2
The D2 diode start conducting, and the applied

voltage changes polarity → the energy flows from
the load to capacitor C2
When the current becomes zero, Q2 is switched to

on state

Principle of Operation - Semiconductors
Q2 is tuned off at TO
The diode D1 start driving current and the

voltage across the load switched → power flows
from the load to C1
The cycle repeats

Principle of Operation – Electrical Characteristics
Current is almost sinusoidal

Voltage is still square shaped
Harmonics are obviously present!

V O1
I S= I O cos θ 1
VS

For an RL load
∞ 2VS nωL
iO= ∑
n=1,3,5. .. n π √ R ²+ ( n ω L ) 2 (
sin ( n ω t −θn ) , where θn =arctan
R )
For an RL load, the fundamental output

power component can be described as
2
2VS
PO =
[√ 2
2 π √ R +( ω L )
2
] R

Harmonic Factor of the nth

V On
HF n = , for n>1
V O1
Total Harmonic Distortion
1 ∞ 1 /2
THD=
V O1 ( ∑
n =2,3 ,4...
V
2
On
)
Distortion Factor
2 1 /2
V On V On
1
[ ( )]
∞
DF = ∑ 2
DF n = 2 for n >1
V O1 n=2,3 ,4... n V O1 n

Full Bridge Inverter
●
Also known as Voltage Source Inverter (VSI) or H bridge
●
Made up with four controlled switches and four freewheeling diodes

●
This circuit does not need the capacitors for voltage splitting
●
The purpose is switching current peaks

●
There is no connection between the capacitors and the middle node
of the switches leg

Full Bridge Inverter - Semiconductors
● When Q1 y Q2 are on
– Vab = VS
– Q1 y Q2 drive current if iO is positive (flows from a to b)
– D1 y D2 drive current if iO is negative (flows from b to a)

– Vab = -VS
– Q3 y Q4 drive current if iO is negative (flows from b to a)
– D3 y D4 drive current if iO is positive (flows from a to b)

– Vab = 0 V (the applied)
– Q1 y D3 drive current if iO is positive (flows from a to b)
– D1 y Q3 drive current if iO is negative (flows from b to a)

The RMS output voltage is
V O =V S
The output voltage (instantaneous)
∞ 4V S
vO= ∑ nπ
sin n ω t
n=1,3,5. ..

The current for an RL load (instantaneous) is
∞ 4V S nωL
i O= ∑
n=1,3 ,5... n π √ R²+ ( n ω L ) 2
sen ( n ω t −θn ) , donde θ n=arctan ( R )
For a highly inductive load, the output current can be assumed as sinusoidal
V O1 V O1
i S (t )= I O cos θ1− I O cos(2 ω t −θ 1)
VS VS

●
From single phase inverters


Control of Inverters
●
Control of inverters implies control of output voltage to compensate
– Input voltage changes
– Select the output voltage
– Maintain a ratio between voltage and frequency (AC motors)
●
Other requisites are
– Regulate the output frequency
– Inject harmonics
●
These conditions can be fulfilled by means of Pulse Width Modulation
(PWM)

Single Pulse Width Modulation
●
A single pulse on each half cycle
●
The width of the pulse establishes the
output voltage
● AC is the carrier signal, that

establishes the output voltage
frequency
● Ar is the reference signal, that

establishes the pulse width δ
●
Modulation index
Ar
M=
Ac

●
Modulation Index
Ar
M=
Ac
●
The RMS voltage at the output of the
convert is
δ
V O=V S π √
● If Ar changes between zero and the
peak value of Ac → the pulse width δ
varies between 0 y π → the RMS ouput
voltage varies between 0 y VS

●
Example 00 of PSIM
●
Example 01 of PSIM

●
Applying Fourier transform to the
output voltage
∞
4 VS nδ
vO= ∑ sen sen n ω t
n =1,3,5... nπ 2
●
No cosine terms
●
Only odd terms

●
output voltage
∞
4VS nδ
n =1,3,5... nπ 2
●
No cosine terms
●
Only odd terms
●
Plot of the firsts harmonics against
the modulation index

●
output voltage
∞
4VS nδ
n =1,3,5... nπ 2
●
No cosine terms
●
Only odd terms
●
●
The lowest DF implies
●
Null third harmonic
●
Not full output voltage

●
output voltage
∞
4VS nδ
n =1,3,5... nπ 2
●
No cosine terms
●
Only odd terms
●
●
If a first harmonic of 60% level is
wanted, then
●
The 3rd harmonic will be 25%
●
The 5th and the 7th are 10%

Multiple Pulse Width Modulation
●
How to reduce the harmonic
content of the output signal?
● If the carrier frequency fC
increases, then the other
harmonics will be displaced to
higher frequencies
A
f
● The output frequency fO is
established by the change of
polarity in the modulator

●
This kind of modulation is
known as Uniform Pulse
Width Modulation (UPWM)
●
The number of pulses per
cicle that can be obtained is
fc mf
p= =
2fo 2
●
The ratio between
frequencies is given by the
mf index

●
If δ is the pulse width, then
the RMS value of the output
voltage is given by
p⋅δ
V O =V S √ π
●
The number of pulses and
the width of them is
conditioned by the switching
speed of the transistors

●
From the plot of the harmonics
amplitudes for a five pulses
UPWM
– There is no modulation index
value that makes zero any of
the harmonics
– The fundamental harmonic
value is similar to the single
pulse modulation
– The third harmonic always has
a non zero value

●
PSIM demo 02

Sinusoidal Pulse Width Modulation
●
If the pulse width (δ) is changed
along the modulation cycle, it is
possible to reduce even more the
harmonic content
●
Comparing a triangular and a
sinusoidal carrier
– The pulses width varies
– The harmonic content is reduced
●
The output voltage RMS value can be
changed by changing the reference
amplitude
2p 1 /2
δm
V O =V S (∑ )
m=1
π

●
The distortion factor get significant
reduction → the output signal is more
closer to be like a sinusoidal
●
This modulation removes all harmonics
equal or lower than 2p - 1 → the higher
the switching speed of semiconductors
is, then higher number of pulses can be
produced, and lower the harmonics
●
The practical effect is that the distance
between fundamental and harmonics
frequencies becomes bigger
A

●
PSIM examples 03 and 04

Phase-Shift Modulation for Full Bridge Inverter
●
The converter operates like two half bridge converters
working back-to-back on different phase

●
If both legs of the
converter operates in
opposition (180°), then
the output voltage is a
full square wave
●
This is similar to the
single pulse modulation
with δ = 1

●
If one of the legs of the
opposition, but with a
delay of α
●
Now this is similar to
the single pulse
modulation with δ ≤ 1

●
If one of the legs of the
opposition, but with a
delay of α
●
Now this is similar to
the single pulse
modulation with δ ≤ 1
●
The phase of the output
voltage is relative to
the control loop time

●
Power Electronics – Circuits, Devices and Applications,
Muhammad Rashid
●
Chapter 8 – Inverters
– Topics 8.1 to 8.6.3 and 8.6.5
●
Examples 8.1, 8.2 and 8.4
●
Problems similar to the examples

DC to DC Converters
Rev. 2020-04-20
Index
●
●
●
Buck Converter (Reducer)
●
Boost Converter (Elevator)
●
Buck-Boost Converter
●
Control of DC to DC Converters

The output is another

continuous voltage with
the desired
voltage
that can be
lower
or
The source is a
continuous voltage or higher
current source

Introduction
What is a DC to DC converter?
UDC DC to DC Rn
Converter
Primary Source: Batteries, Load: any other

DC Generator, Photovoltaic component or circuit that
panels needs DC voltage

How could DC voltage be transformed?
●
Basic idea: applying the DC input at regular intervals, so the
average output voltage is reduced analog to the desired DC
voltage
UDC PWM Sample

Network
Rn
VO
UDC
t on
V O (average )= ⋅U DC =d⋅U DC =δ⋅U DC
T
ton toff t

How could DC voltage be transformed?
●
Basic idea: Filtering the output voltage to have a smooth DC
voltage at the output
UDC PWM Sample

Network
Rn
VO Low
UDC VP Pass VO Rn
UDC Filter

How to implement the low pass filter?
●
Using a capacitor in parallel with the load
VO
UDC
Low
UDC VP Pass VO Rn
Filter
IDC
UDC VP C VO Rn
n
It is a bad practice (generates EMI noise)

●
Using a capacitor in parallel with the load and a series inductor
Ln
UDC
Low
VP Pass VO Rn UDC VP Cn VO Rn
Filter
●
It is also a bad practice, as the current through the inductor gets
interrupted abruptly
●
When the switch opens, the inductor generates high voltage that
can damage the semiconductor

●
Adding a diode to freewheel the inductor current solves the
problem
Ln
UDC
Low
VP Pass VO Rn UDC VP D Cn VO Rn
Filter
The circuit becomes the buck converter

It reduces higher input voltage to lower values

DC to DC Converters
Switch Mode Power Converters – PWM Converters
Single Controlled Switch Multiple Controlled

Switches
Not Isolated Isolated
Buck (reduce) Forward Push-Pull
Boost (elevate)
Flyback Half Bridge
Buck-Boost
Čuk Full Bridge
Čuk
SEPIC
SEPIC
ZETA ZETA

DC to DC Converters

Switches
Boost (elevate)
Flyback Half Bridge
Buck-Boost
Čuk Full Bridge
Čuk
SEPIC
SEPIC
ZETA ZETA

Operation Modes
IL
●
Continuous Current OM (CCM)
– The current through the
magnetic element never
becomes zero
t
ton toff
●
Discontinuous Current OM (DCM) IL
– The current through the
magnetic element is zero
during part of the switching
period
ton toff t

Operation Modes
iL(t) i L (t) R1
●
An increase in the output
resistance means a decrease
of the output current IO
● Decrease of IO means also a t
iL(t)
decrease of IL, peak and i L (t )
R2 > R1
average
● Slopes of IL are independent
t
from IO
iL(t)
●
All show OM are CCM i L (t )
RCRIT > R2 > R1
●
This last one is the critical
t

Operation Modes
●
Any resistor value higher iL(t)
i L (t )
RCRIT
than the critical one makes

the lower peak negative
What happens then? t
iL(t)
M1 L R3 > RCRIT
i L (t )
M2
D
t
iL(t)
M L
i L (t) R3 > RCRIT

Operation Modes
● Any change in IO makes iL(t)
i L (t )
RCRIT
the same change in the

average value of IL
●
When operating in DCM, as t
iL(t)
the current can not go i L (t )
R3 > RCRIT
negative, the average
output current increases,
and the output voltage and
t
output current increase too iL(t)
i L (t) R3 > RCRIT

Operation Modes with Changes
IL
●
Increasing the value of the
inductance makes the current peaks
increase t t
t
o o
n T ff
IL
●
Decreasing the frequency makes
also the peaks higher, but keep the
same slopes t t
t
o o
IL n T ff
●
Reducing the output current
(increasing the output resistance t t
t
value) lowers the average value of o o
the current through the inductance n T ff

Conditions for Analysis of the Swithching Converters
●
The input voltage is constant
●
The switching devices are ideal, having instantaneous turn on and
turn off, and no losses and no power dissipation
●
The inductances and capacitors are also ideal, and have no power
losses
●
The capacity of the output filter capacitor is so big that the voltage
across its terminals can be assumed as constant. (This hypothesis
is not applied when the output voltage ripple is calculated.)
●
The values of voltages and currents (peaks, averages), and the
conversion ratios are calculated assuming certain initial conditions
in all reactive elements (operating under permanent regime)
●
Analysis will be made in both continuous and non continuous mode
Buck Converter
M L
VGM ton = δ·T
UDC D C R L VO
t
IL
M L
T 2T t
UDC D C RL VO IM
along δT
M L t
ID
UDC D C RL VO
along (1-δ)T t

Buck Converter – CCM Analysis
●
On circuits operating under steady state
L VL=0V
– The average voltage on inductors is zero
Circuit on
– The average current through capacitors is zero UDC Steady
State IC=0A
T iL(t) i L (t)
v L (t )
i L (t=T )=i L (t =0)+∫ dt ⇒i L (t =T )=i L (t =0)
0 XL
t
T vC(t) v C (t)
v C (t =T )=v C (t =0)+∫ i C (t )⋅X C dt ⇒ v C (t =T )=v C (t =0)

0

VGM ton = δ·T
●
If the semiconductors are real
IM VM IL L IO VM
U DC +V D
M VL IM
UDC D C R L VO iO
VD
−U DC +V M
VM IL L IO ID
iO
M VL VL U DC−V M −V O
UDC D C R L VO
−( V O +V D )
ID IL IO
Δ IO

M L VGM ton = δ·T
UDC D C R L VO VL
U DC −V M −V O
−( V O +V D )
IL IO
●
Under CCM, current through transistor and diode
Δ IO
must be the same
●
That implies that the current on the inductor
remains (on average) constant
(U DC −V O )⋅t on=V O (1−t on )
●
And the voltage across the inductor changes from
positive to negative (U DC −V O)⋅δ⋅T =V O (1−δ )⋅T
●
The product of voltage and time must be the U DC⋅δ⋅T =V O⋅T
same during ton and toff (δ and 1-δ)
The transfer function is independent from the
VO
●
=δ (1)
load of the converter (1) U DC
The current across the capacitor is zero, thus the
VO
●
(dc) output current is the average inductor

current (2)
I O = =I L(avg ) (2)
RL

M L VGM ton = δ·T
UDC D C R L VO VL
U DC −V M −V O
−( V O +V D )
IL IO
●
Find the maximum and minimum of inductor
Δ IO
currents as function of know data
ΔI ΔV L
Δ V L =L⋅ ⇒ Δ I =I Lmax −I Lmin = ⋅Δ t
Δt L
U DC −V O V O I Lmax + I Lmin
I Lmax − I Lmin= ⋅t on (1); V O =δ⋅U DC (2) and I L = = (3)
L RL 2
1 T 1 T
I Lmax =δ⋅U DC
[ + ⋅(1−δ )
RL 2 L ] I Lmin =δ⋅U DC
[ − ⋅(1− δ )
RL 2 L ]
M L VGM ton = δ·T
UDC D C R L VO VL
U DC −V M −V O
−( V O +V D )
IL IO
●
Δ IO
1 T 1 T
I Lmax = δ⋅U DC
[ + ⋅(1− δ)
RL 2 L ]
I Lmin= δ⋅U DC
[
− ⋅(1−δ )
RL 2 L ]
T⋅R L
The frontier to DCM is when I Lmin=0 A ⇒ Lmin =
2 ( )
⋅(1−δ )
It is the minimum value of the inductance that keeps the converter

operating in the continuous conduction mode

M L IL IO
Δ IO
IC +Δ Q
UDC D VC C R L VO Δ IO
2
Δ IO
−Δ Q −
2
VC
VO
●
Capacitor value for a given ripple voltage ΔVO
●
The output ripple is independent from the
load resistor value
ΔQ 1 1 Δ I T
●
The ripple can be smaller if Δ V O=
C
=
C 2 2 2 ( , )
The switching frequency fS is increased 1 1
– f C= , and f S =
2π√LC T
– The turn on time δ is increased V O ( 1−δ ) T 2
then Δ V O =
● +/-ΔQ is the shadowed area on IC plot 8 LC
2
Δ V O π2 f
●
C value is picked bigger than the calculated and relatively
VO
= ( 1−δ ) C
2
2
fS ( )
1 Δ I 1 1 U DC δ ( 1− δ ) T
C min ⩾ =
8 ΔVO f S 8 ΔVO L

Electrical characteristics for the main switch (transistor) and freewheeling diode
VM VD Vγ
U DC +V D VAK
V M (DS ) −U DC +V M ( DS)
IM Δ IO
IO ID IO
Δ IO
Transistor Diode
V DSS > U DCmax +V γ V RRM > U DCmax −V DS

ΔI ΔI
I DM ⩾I Omax + I FSM ⩾I Omax +
2 2
I D ⩾ I Omax|δ
min
I Favg⩾ I Omax|( 1−δ )
min

Electrical maximum values are not absolute. When operating the real circuit, under real
circumstances, the switching semiconductors must be able to withstand higher current and
voltage peaks due to the parasitic elements of the components
V DS peak
U DC +V D
0V

Buck Converter – DCM Analysis
IM VM IL L IO VGM ton = δ·T
M VL δ’·T
UDC D C RL VO
t
IL
along δT
VM IL L IO
t
M VL T
VL U DC −V M −V O
UDC D C RL VO
along δ’T ID −( V O +V D )
VM IL L IO
ID
M VL
t
UDC D C RL VO
The transistor drives current during δ·T
along (1-δ-δ’)T ID The diode drives current during δ’·T
The capacitor holds the voltage during
the remaining time
Buck Converter – DCM Analysis
VGM ton = δ·T
●
Under DCM the current through the
δ’·T
inductor goes to zero
●
A similar analysis of the product of voltage IL
t
and time can be applied (same areas)
(U DC −V O )⋅δ⋅T =V O⋅δ '⋅T t

T
U DC⋅δ⋅T =V O⋅( δ + δ ' )⋅T VL U DC −V M −V O
VO
= δ (1) −( V O +V D )
U DC δ + δ '
ID
and the output current is
VO
I O = =I L(avg ) (2) t
RL
The transistor drives current during δ·T
The diode drives current during δ’·T
The capacitor holds the voltage during
the remaining time
Can we have a different converter?
SC, δ, ton Ln SNC, 1-δ, toff Ln
UDC Cn Rn VO VO Rn Cn SC UDC
SNC
Buck Power Flow Converter Power Flow
Interchanging the VO ⇌ UDC, the δ ⇌ 1-δ, and the switches

Ln
SC This switch must be controlled, to avoid permanent short circuit

Can we have a different converter?
SNC, 1-δ, toff Ln Ln SNC, 1-δ, toff
VO Rn Cn SC UDC UDC SC Cn R n VO
Converter Power Flow Mirroring the converter Boost Power Flow
L D
UDC M C RL VO
Replacing the ideal switches with the controlled transistor and the freewheeling diode
the boost (elevator) converter is obtained

Boost Converter – CCM Analysis
IL L ID D IO
VGM ton = δ·T

VL IM VD
UDC M VM C RL VO
i L (t) t
IL
IL L D IO
VL IM
VD T 2T t
UDC M C RL VO IM
i M ( t)
along δT
IL L ID D t
IO
ID i D (t)
VL
UDC M VM C RL VO
t
along (1-δ)T

IL L ID D IO
VGM ton = δ·T
VL IM VD
UDC M VM C RL VO VL
U DC −V M
−( U CM −V O +V D )
IL IO
●
Δ IO
must be the same
●
U DC⋅t on=−(U DC −V O )⋅(1−t on )
●
positive to negative U DC⋅δ⋅T =−(U DC −V O )⋅(1−δ )⋅T
●
The product of voltage and time must be the U DC =V O⋅(1−δ )
The transfer function is independent from the
VO 1
●
= (1)
load of the converter (1) U DC 1− δ
VO
●
(dc) output current is the average diode current

(2) I O= =I D (avg ) (2)
RL

IL L ID D IO
VGM ton = δ·T
VL IM VD
UDC M VM C RL VO VL
U DC −V M −V O
−( V O +V D )
IL IO
●
Δ IO
ΔI ΔV L
Δ V L= L⋅ ⇒ Δ I =I Lmax −I Lmin= ⋅Δ t
Δt L
U DC U DC 2⋅U DC
I Lmax − I Lmin= ⋅t on (1); V O = (2) and I Lmax + I Lmin= 2
(3)
L 1− δ R L ( 1−d )
1 δ⋅T 1 δ⋅T
I Lmax =U DC⋅
[ 2
+
R L ( 1−δ ) 2 L ] I Lmin=U DC⋅
[
R L ( 1− δ )
2
−
2L ]
IL L ID D IO
VGM ton = δ·T
VL IM VD
UDC M VM C RL VO VL
U DC −V M −V O
−( V O +V D )
IL IO
●
Δ IO
1 δ⋅T 1 δ⋅T
I Lmax =U DC⋅
[ 2
+
R L (1−δ ) 2 L ] I Lmin =U DC⋅
[R L ( 1−δ )
2
−
2L ]
T⋅R L
2
⋅δ⋅(1−δ )
2
( )
It is the minimum value of the inductance that keeps the converter
operating in the continuous conduction mode

Boost Converter – Capacitor Analysis
IL L ID D IO
VGM ton = δ·T

VL IM VD
UDC M VM C RL VO
t
IL
CCM
DCM
If I Lmin⩾I O , then
T 2T t
Δ QC V O δ T
C= = ⋅ IC I Lmax + I O
Δ V O Δ V O RL
CCM
I Lmin + I O
If I Lmin < I O , then −I O

2
Δ QC V O L 1 (1− δ )⋅T t
C= = ⋅ ⋅δ
ΔVO ΔV O 2 R⋅(1−δ )(+
2L ) IC
I Lmax + I O
The limit between these two situations is given by DCM
L min −I O
t
I Lmin =I O ⇒ Ll i m = δ

VM ton = δ·T VM ton = δ·T

V O +V γ V O −V DS
V DS −V γ
t t
IM IM
Δ IO Δ IO
t t
Transistor Diode
V DSS > U DCmax +V γ V RRM > V O−V DS

I Omax Δ I I Omax Δ I
I DM ⩾ + I FSM ⩾ +
1−δ 2 1− δ 2
1 I Favg ⩾I Omax
I Davg⩾ I Omax⋅
1− δ
Can a converter boost and buck?
M L L D IO
UDC D C VI M C RL VO
Buck Boost
VO VO VI
U DC
= ⋅
( )( )
= δ
V I U DC 1− δ
δ 1-δ
M L D IO L IO
UDC UDC
D M C RL VO 1-δ δ C RL VO

Can the number of switches be reduced?
A L B
UDC VL
Along δ
δ
A L B 1-δ IO
UDC
1-δ δ C RL VO
A L B
VL
C RL VO
If the output voltage polarity is reversed,
Along 1-δ
then the switches can be grouped

Can the number of switches be reduced?
A L B
UDC VL
The Buck – Boost Converter
Along δ
δ 1-δ IO
A
UDC
L C RL VO
B L A IO
B
VL
C RL VO
Note that the output voltage polarity is
Along 1-δ reversed, compared with the buck and with
the boost converters

The Buck – Boost Converter – CCM Analysis
IM M D ID IO
IL VGM ton = δ·T

UDC
VL L C RL VO
i L (t) t
IL
IM M D IO
IL
UDC T 2T t
VL L C RL VO IM
i M ( t)
t
M D ID IO
ID i D (t)
IL
UDC
VL L C RL VO
t

IM M D ID IO
VGM ton = δ·T
IL
UDC
VL L C RL VO VL
U DC −V M
−( V O −V γ )
IL IO
●
Δ IO
must be the same
●
U DC⋅t on=−V O⋅(1−t on)
●
positive to negative U DC⋅δ⋅T =−V O⋅(1− δ )⋅T
●
The product of voltage and time must be the U DC⋅δ=V O⋅(1− δ)
VO
●
The transfer function is independent from the = δ (1)
load of the converter (1) U DC 1−δ
VO
●
(dc) output current is the average diode current

(2) I O = =I D (avg ) (2)
RL

IM M D ID IO
VGM ton = δ·T
IL
UDC
VL L C RL VO VL
U DC −V M
−( V O −V γ )
IL IO
Δ IO
ΔI ΔV L
Δ V L= L⋅ ⇒ Δ I =I Lmax −I Lmin= ⋅Δ t
Δt L
U DC
I Lmax − I Lmin= ⋅t on (1); V O =U DC⋅ δ (2) and I Lmax + I Lmin=2⋅U DC⋅ δ
2
(3)
L 1− δ R L ( 1−d )
1 T 1 T
I Lmax =U DC⋅δ⋅
[ 2
+
R L ( 1− δ ) 2 L ] [
I Lmin=U DC⋅δ⋅ 2
−
R L ( 1− δ ) 2 L ]
IM M D ID IO
VGM ton = δ·T
IL
UDC
VL L C RL VO VL
U DC −V M
−( V O −V γ )
IL IO
Δ IO
1 T 1 T
I Lmax =U DC⋅δ⋅
[ +
R L ( 1−δ )2 2 L ] [
I Lmin =U DC⋅δ⋅ −
R L ( 1− δ )2 2 L ]
T⋅R L
2
⋅(1−δ )2 ( )

The Buck - Boost Converter – Capacitor Analysis
IM M D ID IO
IL VGM ton = δ·T

UDC
VL L C RL VO
t
IL
CCM
DCM
If I Lmin⩾I O , then
T 2T t
Δ QC V O δ T
C= = ⋅ IC I Lmax + I O
Δ V O Δ V O RL
CCM
I Lmin + I O
If I Lmin < I O , then −I O

2
Δ QC V O L (1− δ )⋅T t
C= = ⋅
(
δ
Δ V O Δ V O 2 R⋅(1−δ )
+
2L ) IC
I Lmax + I O
The limit between these two situations is given by DCM
L −I O
I Lmin =I O ⇒ Ll i m = min t
δ

VM ton = δ·T VD ton = δ·T

U DC +V O +V γ U DC +V O −V DS
V DS −V γ
t t
IM ID
Δ IO Δ IO
t t
Transistor Diode
V DSS> U DCmax +V O +V γ V RRM > U DC +V O−V DS

I Omax Δ I I Omax Δ I
I DM ⩾ + I FSM ⩾ +
1− δ 2 1−δ 2
I Davg ⩾I Omax⋅ δ I Favg ⩾I Omax
1− δ

DC to DC Converters

Switches
Boost (elevate)
Flyback Half Bridge
Buck-Boost
Čuk Full Bridge
Čuk
SEPIC
SEPIC
ZETA ZETA

Čuk Converter

SEPIC Converter

ZETA Converter

Forward Converter
V O N1
= ⋅δ
V S N2

Flyback Converter
V O N1 δ
= ⋅
V S N 2 1−δ

Multiple Switches Converters

●
Voltage Control Mode (VCM): A single control loop is used
●
The output voltage is controlled by means of changes in the duty cycle (δ) to
compensate changes in the input voltage or in the load
●
Can be made at constant or variable frequency
Input Voltage Output Resistance
Reference + Power Output

Regulator PWM
Voltage Circuit Voltage
–
Feedback
Circuit

●
Voltage Control Mode (VCM): A single control loop is used

●
Current Control Mode (CCM): Two control loops are needed
●
External loop (slow): controls the output voltage
●
Internal loop (fast): samples the current through the main switch or the inductor,
converts it to voltage and compares with the internal feedback voltage
●
Different methods are used
– Average current
Output
PWM
– Peak current Power Voltage
Circuit
Current Loop
Feedback
Circuit Voltage Loop

Recommended Chapter and Exercises
●
Theory and Problems of Electronic Devices and Circuits, 2 nd
edition, J. Cathey, Schaum McGraw Hill, 2002
●
Chapter 10 – Switched Mode Power Supplies
– Topics and exercises 10.1 to 10.5
– Problems 10.1 to 10.8, 10.10, 10.11, 10.13 and 10.14
– Supplementary problems that are similar to previous

Reliability of Electronic Components, Circuits,

Systems and Installations
Part 1 - Introduction and Definitions

Rev. 2021-02-09
Index
●
Objectives
●
Introduction to RAMS technologies
●
Concepts
– Reliability
– Availability
– Maintainability
– Safety
●
Relation between concepts
●
Why is Reliability interesting?

Objectives
●
The objectives of this topic are:
– Understand what reliability is and how it is related with other engineering
topics
– Definition of reliability, maintainability, availability and safety
– Describe the relationship between these concepts
– Understand how to mathematically describe the reliability
– Understand how failure rates of components and systems are calculated
– Understand how the different reliability variables are related and how they
describe reliability
– How different variables of reliability analysis are obtained for components and
systems

How To Use The Slides
●
The slides of this topic contain a wide abstract of all involved
concepts
●
The important definitions, related with the main concepts, are
shown in blue color along the text
●
When moving from definitions towards a mathematical model, a
statistics measured variable or a process of experimental sampling
and quantification, it is indicated in red color along the text
●
If based on the concepts, and supported by a mathematical
development a set of actions or an applied engineering method is
achieved, it is indicated in green color along the text.
●
This set of slides does not substitutes the bibliographical references

Introduction
●
More complex
electronic
components
●
The functions
embedded into a
single
component have
increased
●
System on Chip
(SoC) are state of
the art

Introduction
●
The size of
electronic
components
(transistors) get
smaller
●
The amount of
components into a
single integrated
circuit get also
increased, as the
die size keeps the
same

Introduction
●
The circuits are more complex and with increasing functionality
●
The die size is reduced, and the packaging also gets reduced
●
The electronic systems have larger and heterogeneous modules
●
Industrial facilities with larger quantities of heterogeneous systems
●
More competition on industrial and consumer markets
●
The products (components, equipments, systems or facilities)
should withstand the technical specifications for a established time
●
These requisites got reflected into warranties and technical
operative conditions
●
These functional requisites, along a specified time and with
warranties generate the reliability specification
Introduction
●
The demand that a product should be operative and functional
whenever is needed exists
●
This demand is the origin of the availability specification
●
The availability depends on the type of maintenance applied to the
products that can go under a reparation procedure
●
This is the root for the maintainability concept
●
In many applications, the process or the machine can go into a
dangerous situation if the control or any part of it fails
●
Due to this, it is necessary that the control does not fail. Or, if it fails,
it does not suppose a risk for the facilities, the people or the
environment
●
From these conditions arises the concept of safety specifications
Introduction
Reliability Confiabilidad
Availability Disponibilidad
Maintainability Mantenibilidad
Safety Seguridad
RAMS Technologies
Confiabilidad
Reliability
• The reliability starts as consequence of the need to

quantify the availability and maintenance along the
life time of the quality of a product
• The safety of a product is related with its operational
requisites and the operative environment
• There are different definitions of quality that can be
applied to RAMS technologies

Reliability and Quality
• The reliability can be explained as the quality of a product
• “Quality is satisfy the client demands”, K. Ishikawa
• This is not the same as have a high quality level
• “Quality is conformance to requirements, meaning both the
product and the customer's requirements”, P. Crosby
• Know perfectly which are the requirements
• "The quality of a product is the (minimum) loss imparted by the
product to the society from the time product is shipped" (Bryne and
Taguchi, 1986)
• Is to be efficient along all the stages of production
• This implies that the quality of the product is defined since the
beginning of the design process

Reliability and Probability
●
According with the Electrotechnical International Committe (EIC):
– The reliability is the probability that a component, a circuit or a

system achieves its function, under specific conditions and during
a concrete time
– The reliability is quantified as a probabilistic item (0~1)
– The reliability represents the quality of an item along time
●
Acording to MIL STD 721C
– Reliability is the probability that an item will perform its intended

function for a specific interval under stated conditions

Reliability and Defects
• Any component, circuit, system or equipment, developed by
an human being, can operate in a different way to which it
was conceived, due to imperfections
• These imperfections are non predicted variations of its
characteristics
• Defect → its presents difficulties the normal operation
• Fault → as consequence of defect/s, wrong operation or out
of tolerance behaviors happens
• Error → it is the quantification of the fault's effect
• Breakdown → is how the error shows up

Reliability and Defects
• A failure is defined as the loss of capacity to perform

its mission (a certain task) of a component, a circuit,
a system or an installation.
• The failures can be classified, taking into account
the life span of an element
– Early failures (infant mortality)
– Random
– Wearout failures

Reliability
• Since when the reliability has to be taken into account?
• The reliability specifications have to be taken into account
since the first stages of the design
• It is necessary to make research a priori in order to predict
the reliability
• This research allow us to choose the best fitted design, and
then predict the number of components, circuits or systems
that will work properly at a certain moment under a
established operating conditions
• Prior knowledge → Predictive methods → Better design
decisions → Improved prediction of future operating failures

Reliability - Stages
●
There are three stages along the life of a product
●
The predicted reliability is calculated (estimated) based on
a mathematical model. This model is defined from the
design technical specifications of the system and the
estimated reliability of the components on the system.
• Is the predicted reliability for the design stage and it allows
us
• Know if a certain design meets the reliability
specifications
• Compare different design alternatives
• Analyze the effect of different design choices

Reliability - Stages
• The estimated or intrinsic reliability is measured by specific
tests made on a prototype
• The obtained reliability is to be check against the predicted
reliability
• The operational reliability is measured along the life span of
the product. It depends on the real use conditions and the
logistic support
• During the life span (use of product), the data collected
gives the real reliability of the product
• The predicted reliability model is improved from this set of
data

Reliability and Costs
• There is a relationship between reliability and cost of a
product that is the most adequate
• What is the reliability level to be applied when designing,
manufacturing and maintaining a product?
• The solution seems to be the reliability level that keeps the
costs at the minimum
• That implies that an equilibrium point of a reliability vs cost
model has to be found

• The total costs of the manufacturer is described as the sum
of first inversion (prior to deliver) and the operating costs
(post deliver, post sales)
• The first inversion is, among other factors, the sum of
research costs, engineering costs, development costs,
manufacturing and supervision costs
• The operating costs is, among other factors, the sum of the
costs of logistics, transport, installation, first start,
warranties and costs derived from the good practice with
the clients

Costs during the development
Costs
The costs increase as the reliability increase

because
●
The research, design and development
hours increase
●
The selected components are better
●
The manufacturing costs also increase
Reliability
0 1

Costs during development
Costs Costs during operation
The costs of operation decrease as

the reliability increase because
●
Less failures
●
Less reparations
●
Lower warranty costs
Reliability
0 1

Sum of costs
Reliability
0 1

Sum of costs
Sales price
Reliability
0 1

Sum of costs
Sales price
Reliability
Reliability at
0 Minimum Cost 1

Sum of costs
Sales price
Reliability
Desired
0 Reliability 1

Reliability and Redundance
• What happens if a component, circuit or system fails?
• The drastic solution is to change it for another (same type)
• A spare system is one that is inactive (stored), waiting to be
put into operation (into service) when the active system
fails
• The reliability of a system made up by two components, one
in operation and another in storage, is the probability that
the operational unit works correctly during a time t and the
spare unit does not fail when replacing the broken one
• This kind of systems is said to be redundant
• The reliability of a system with redundancy is higher than
the reliability of a system with no spare parts

Reliability and Maintenance
• What happens when we know that component, circuit or
system is going to fail?
• Inmediatly the following questions arise:
– Is the warranty still valid? Does it still applies?
– When it fails, how long will it take to find the failure?

– How fast can the system be fixed?
– Are there spare parts available?
– Maintenance procedures should be scheduled to prevent
a failure?
– How often will be necessary to replace some
components?

Reliability and Repair
• What happens if a component, circuit or system fails?
• Another solution is to repair (fix) the equipment, replacing
the components that are broken (failed)
• The spare parts are analog to a redundant part
• The reliability of a systems that can be repaired is higher
than the reliability of a non repairable system
• The time to repair a system is the time that goes since the
failure is present, or detected (preventive), until the system
is fixed or replaced

Maintainability
• The maintainability is defined as the probability that a
system with a failure can be repair in a certain time, to be
put in the initial reliability
•
• The corrective maintenance is the set of operations made
when a fail shows up
– The system must be put to an initial state of operation
– It must be able to perform the designed functions

– This type of maintenance is unavoidable

Maintainability
• The preventive maintenance is defined as a set of periodically applied
operations or applied with specific criteria
• Their mission is to reduce the probability of a failure
• The preventive maintenance checks and replace components and elements
before they reach the end of life
• The preventive maintenance tasks should be chosen and programmed as
– Time-based maintenance
– Age-based maintenance
– Usage-based maintenance
– Condition-based maintenance
– Opportunity-based maintenance
– Design-out maintenance

Maintainability
• The predictive maintenance is a set of tasks of test and measure
of certain variables or elements of a system
• The objective of the predictive maintenance is to predict the
failure before it happens
• This kind of maintenance helps detecting the prone elements to
failure and program its replacement in the best possible time
• It also allows to
– Improve the preventive maintenance
– Reduce the corrective maintenance

– Increase the reliability of the system

Maintainability and Availability
• The applied maintenance to a system increases its reliability
• This implies that the system will be available during longer
time to perform its function
• From this another important concept arises
• The availability of a component, circuit, system or equipment
is the probability that it works properly, at a certain time and
under certain operative conditions, being this probability
related with the maintainability of the item itself
• If there is maintenance, then the reliability increases, and as
consequence the availability also increases

Reliability and Safety
• If a component has a non null probability of failure along its life
span, then probably a failure will be the cause of a loss of safety
• The safety is defined as the capacity of a component, a circuit, a
system or an equipment, when a failure appears or an incorrect
operation is made, not to reach a state that can produce damages
to the process it participates, to its enviroment or to the human
beings using it
• This definition of safety is sometimes given as functional safety
• Another way to define safety is to quantify the probability that a
component, a circuit, a system or an equipment performs its
proper functions or fail, in a way it does not compromise the
operation of other systems

Safety
• There are industrial facilities that have operational parameters that implies a
high level of safety
– Chemical, petrochemical and pharmaceutic plants

– Power generation and distribution facilities
– Mining quarries
– Transport of flammable substances (pipelines, etc.)
– Food industry
– Water treatment facilities (drinking, desalinization, waste water, etc.)
– Transport of people and living stock
– Tunnels of highways and trains
– Industrial processes involving dangerous (flammable) materials

Safety and Standards
●
As stated in the (not valid) standard EN 292-1, the safety of a machine it
is the inherent capability to fulfill its function, to be transported,
commissioned, adjusted (calibrated), maintained, disassembled and
removed in the indicated use conditions in the machine instructions
manual, without causing harm or damages to health
●
From this definition and the previous concepts, we can refiner that there
are
– Dangerous applications machines
– Highly available machines
– High safety machines
– Long life span machines
●
The current standard is ISO EN 12100:2010 Safety of machinery - General
principles for design - Risk assessment and risk reduction (ISO 12100:2010)

Safety and Failures
●
If a machine or an industrial process is controlled by an
electronic system, then we can have
●
Degree of failures in the machine
– Normal failure
– Dangerous failures
●
Failure in the electronic system
●
External failures over the machine
●
All (known) failure conditions should lead to a safe condition

Importance of RAMS
●
A M.Sc. / Engineer must be capable of designing, testing, put to
production (manufacturing) and maintain a product
●
To do these task, should
●
Know how long must the product operate and with which
reliability
●
Which will be its (desired/achieved) availiability
●
Which will be its (desired/achieved) maintainability
●
How many spare parts are needed along the life span
●
Which failures can affect the safety, to minimize them and/or
prevent the consequences

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Electronic Technology Department

School of Industrial Engineering

List of Topics, Chapters and Exercises – Academic Year 2018-2019

Topic 6 – Linear Regulators

• Electronics Devices and Circuits Theory

• Power Electronics, D. Hart, 2011, McGraw-Hill

• Power Electronics - Circuits, Devices and Applications, Muhammad Rashid, Pearson

• Power Electronics - Circuits, Devices and Applications, Muhammad Rashid, Pearson

• Electronic Devices and Circuits, Cathey, Schaum

• Bistable: 1 bit memory cell

• Semiconductor digital memories:

• Electronic devices for the storage of digital data

• Storage capacity: n locations x size of location

• Locations  memory addresses  binary combinations (address bits)

• n bits for address, data of m bits (m = 8  Byte)  size 2n x m

• n = 10, 210 = 1024 ≈ 103  1k / n = 20, 220 ≈ 106  1M / n = 30, 230 ≈

Industrial Electronics System Design 4

Address bus m Bits (8,16,32)

Data bus n Bits (8,16,32)

In charge of reading and executing the

Process control Other

Industrial Electronics System Design 6

• MICROCONTROLLERS MAIN CHARACTERISTICS:

• Input/output resources: ability to operate with the process

• Ability to communicate: distributed control systems.

• Small size: reduced number of pins (multifunction).

• Availability of a range of devices: they are selected in function of the needs of

• Operating security: watch and detection resources of a failure.

• Power: low power applications.

• Protection of intellectual property: protection of unwanted readings of the

Industrial Electronics System Design 7

Timers/counters Interrupt Parallel Serial Analog

Address,, data and control buses

Watchdog ROM program RAM data memory

Industrial Electronics System Design 8

CPU => Microprocessor = It gathers the elements to execute a program

Industrial Electronics System Design 9

Instructions too big -> how to reduce their size

Industrial Electronics System Design 10

• Remove field of address of next instruction to execute :

• Remove field result address:

– It requires hardware for that

Industrial Electronics System Design 11

• Remove 2nd operand address:

Industrial Electronics System Design 12

Industrial Electronics System Design 13

Industrial Electronics System Design 14

More terminals Less terminals

Overlapping of the fetch and

Industrial Electronics System Design

4. Instruction Set Architectures

• Operations do simple things for each code

• Circuits are more simple because instructions do less things

• Peripherals depending on the application

Industrial Electronics System Design 17

• RISC instruction set

• Transfer and arithmetic/logic operations based in the use of an

• Two step pipelining:.

• Stack memory in dedicated memory space without Stack Pointer.

Industrial Electronics System Design 2

• Peripherals dedicated to proccess control: timers/counters, digital I/O,

• Protection against undesired memory access

Industrial Electronics System Design 3

2. Arithmetic and logic unit