EEM336 Week02 Addr Modes

Week 2
Launchpad introduction
Addressing modes
Machine instruction execution over buses
MSP430 Instruction format
Week 2: Addressing Modes 1
MSP-EXP430FR5969 Launchpad

Features
• MSP430 ULP FRAM technology based
MSP430FR5969 16-bit MCU
• 64KB FRAM / 2KB SRAM
• 16-Bit RISC Architecture up to 8-MHz FRAM
access/ 16MHz system clock speed
• 5x Timer Blocks
• Analog: 16Ch 12-Bit differential ADC, 16Ch
Comparator
• Digital: AES256, CRC, DMA, HW MPY32
Features
• EnergyTrace+[CPU State]+[Peripheral State]
available for ultra-low-power debugging
• 20 pin LaunchPad standard leveraging the
BoosterPack ecosystem
• 0.1 Farad Super Capacitor for standalone
power
• Onboard eZ-FET emulation
• 2 buttons and 2 LEDs for User Interaction
• Back-channel UART via USB to PC
Buzz words about the launchpad
• RISC: Reduced instruction set computers
• FRAM: multicycle programmable flash ROM
(firmware)
• Boosterpack: TI makes extensions available for
launchpads (e.g. LCD screen)
• Timers: For timing related tasks, these modules
are used.
• SuperCap: Super capacitor for batteryless
applications.
Buzzwords
• ADC: Analog to digital conversion
• DMA: Direct memory access
• AES256: cryptography
• UART: serial port
• I2C : communication technology connecting
CPU to other integrated circuitd
• Debugging: Hardware debugging by executing
instructions one by one
• eZ-FET: a USB-based on-board emulation
solution for MSP430 microcontrollers
How do we use the launchpad?
• We encourage to obtain a launchpad by yourself
from Farnell’s Turkish subsdiary
• You are supposed to obtain MSP-BNDL-
FR5969LCD (MSP430FR5969 LaunchPad
Development Kit with Sharp ® Memory LCD
BoosterPack Bundle ~$30)
• Otherwise, we will give you one launchpad.
You will use for lab works and you are
supposed to bring it back before the end of the
term.
MSP-BNDL-FR5969LCD
LCD Launchpad
Where do we start?
• Download the following pdf file and read
carefully.
http://www.ti.com/lit/ug/slau535b/slau535b.pdf
• Go to Code composer Studio section on TI’s

web site:
http://www.ti.com/tool/CCSTUDIO
• Download the latest version and install for

MSP430 microprocessor family
• Watch the following videos (only first three is
enough for now)
https://training.ti.com/msp-exp430fr5969-workshop-part-6-msp430fr5969-mpu
https://training.ti.com/search-catalog/field_language/EN/categories/msp430-ultra-
low-power-mcus Week 2: Addressing Modes 9
Requirements
(Please Buy from Local Stores)
• MSP-BNDL-FR5969LCD (buy or get from us)
• A breadboard
• Various LEDs (2 green, 2 blue, 2 red)
• 1 x RGB LED
• Various buttons (at least 5)
• Male-male jumper cables (at least 20)
• 2 x LM34 (or compatible) temperature sensor
• 1 x LDR
• 10 x BC347 transistors (or compatible)
• 10 x 330 ohm resistors
MSP430 Machine Code
The commands (numbers) that the

CPU understands

Machine Code
A set of binary codes that are

recognized and executed directly
by a particular CPU

Machine Language
• Microprocessors understand a set of numbers called
machine instructions.
• Each machine language instruction consists of an
operation code (opcode) and zero or more operands.
• Each machine instruction can be at least two bytes long.
• Operands are the data or the location of the data to be
used in performing the specified operation.
• Often some operands are implicit in the opcode.
• Each instruction occupies some number of consecutive
bytes of memory and the machine program consists of a
sequence of instructions stored consecutively in
memory.
Class Experiment
• Experiment 1 (1 1 2 1 3 1)
– 1: clap your hands
– 2: raise your right hand
– 3: raise your left hand
• Experiment 2
– 1 + [no of claps]: two number instruction
• Experiment 3
– 1 + [desk number is odd: 1 times, desk number is even: 2 times]: two
number instruction

Machine Language
• A special register called the program counter
(PC, i.e. R0) in the control unit of the CPU
contains the address of the next byte of
instruction code to be fetched.
• Unless the program directs otherwise,
instructions are executed in the sequence they
are stored in memory.
• Each instruction can access a Byte (8-bits) or a
Word (16-bit) in memory
– MOV.B R8,R7  lower 8 bits are transferred
– MOV.W R8,R7  16 bits are transferred
Assembly Language
• Machine codes (i.e. numbers) are very difficult
to understand for humans.
• Assembly language is a way of coding the
numbers in human readable symbolic form.
• Instead of using numbers to program a
microcomputer system, we write the code in
assembly language.
• Then convert the assembly program into
numbers using a program called assembler.
• Each microprocessor has a different assembly
language.
Assembler
Assembly language ..
program 0x40
0x36 MOV #0x300,R6
MOV.W #0x300,R6 0x03
0x00
MOV.W @R6+,R7 Assembler 0x46
MOV @R6+,R7
0x37
ADD.W @R6+,R7 0x56
0x37
ADD @R6+,R7
MOV.W R7,0(R6) 0x47
0x16 MOV.W R7,0(R6)
0x00
0x00

Machine Instructions
• An individual machine code is called a
Machine Instruction
– e.g. the machine instruction to move R5 register
value to R6 register value is 0x4506
• The set of all codes recognized by a
particular CPU is known as its Instruction
Set

Machine Instructions
• A typical machine instruction consists of an
operation code (op-code), which specifies
what operation the CPU is to do, plus a
number of arguments, which specify what
data the CPU is to operate on
– e.g. the machine instruction to move 0x0004
to the value in register R6 is 01000000
00110110 00000000 00000100

What Do/Can Machine Instructions Do?
• We can group the instructions according to

function. The groups given here are
generally applicable to most instruction sets
(i.e. they apply to the machine code for
most types of processor)

Instructions: Data Transfer
• From where, to where?
• load (e.g. from memory to a register)
• store (e.g. from a register to memory)
• move (e.g. from register to register)
• …

Instructions: Computations
• The arithmetic and logical operations,
normally carried out by the ALU
(Arithmetic Logic Unit)
• What might this include?
– add
– subtract
– increment
– invert bits
– … and more

Instructions: Flow Control
• A computer program is not a lot of use
without loops, functions, jumps, etc.
• We need to have machine codes to control
the flow of execution through a machine
code program
• Branching, jumping to subroutines,
returning from subroutines

Instructions: Others
• You’ll come across other types of
instructions as the course proceeds
• The bulk, however, fall into the three
categories already mentioned:
– Data transfer
– Computations
– Flow control

MSP430
• The MSP430 CPU is the one we’ll be looking at in
this course
• The codes that follow apply to the whole MSP430
family of microcontrollers
• The CPU has the following characteristics:
– an 16-bit word length
– a 16-bit address space
– memory-mapped I/O

MSP430 Register Set
• Every CPU contains a set of registers which
are available to the machine-code programmer
• You’ve seen one of these already:
– the Program Counter (PC)
– Registers
• You need to know about other registers before
you can start writing machine-code programs

The Programmer’s Model
• This is the way a programmer needs to view
the CPU
• As a programmer, you don’t necessarily
need to know about the hardware details of
the CPU. You need to know what’s
sometimes referred to as Programmer’s
Model of the CPU

MSP430 Architecture: Programmers Model
0 GPR R15 (General Purpose Register)
.
15 . .
. . .
. . . .
. . .
. . .
. . . .
0 GPR 15 R4 (General Purpose Register)

0 Constant Generator 15 R3 (Constant Generator)
0 Stack Pointer 15 R1 (Stack Pointer)
0 Program Counter 15 R0 (IR-Instruction Register - PC)
R2, SR or CG1 (Status Register)

Carry
Zero
Negative
GIE
CPU OFF
OSC OFF
CSG1
CSG2
Overflow

MSP430 Registers
• The MSP430 CPU has 16 registers
– Large 16-bit register file eliminates limited accumulator(i.e.
Register) bottleneck
– High-bandwidth 16-bit data and address bus
• R0 (PC) – Program Counter
– This register always points to the next instruction to be
fetched
– Each instruction occupies an even number of bytes. Therefore,
the least significant bit (LSB) of the PC register is always
zero.
• After fetch of an instruction, the PC register is
incremented by 2, 4, or 6 to point to the next
instruction.
MSP430 Registers
• R1 (SP) – Stack Pointer
– The MSP430 CPU stores the return address of
routines or interrupts on the stack
– User programs store local data on the stack
– The SP can be incremented or decremented
automatically with each stack access
– The stack “grows down” thru RAM and thus SP
must be initialized with a valid RAM address
– SP always points to an even address, so its LSB is
always zero
MSP430 Registers
• R2 (SR/CG1) – Status Register
– The status of the MSP430 CPU is defined by a set
of bits contained in register R2
– This register can only be accessed through register
addressing mode - all other addressing modes are
reserved to support the constants generator
– The status register is used for clock selection,
interrupt enable/disable, and instruction result status

R2 (SR) – Status Register
• R2 (SR/CG1), R3 (CG2) – Constant Generators
– Six different constants commonly used in
programming can be generated using the registers
R2 and R3, without adding a 16-bit extension word
of code to the instruction

MSP430 Registers
• R4 …. R15 – General Purpose registers
– The general purpose registers R4 to R15 can be
used as data registers, data pointers and indices.
– They can be accessed either as a byte or as a word
– Instruction formats support byte or word accesses
– The status bits of the CPU in the SR are updated
after the execution of a register instruction.

MSP430 Memory
– Unified 64KB
0x0000
continuous memory
map Peripheral/FRAM
– Same instructions for 0x1A00
data and peripherals

– Program and data in 0x1C00
Flash or RAM with no RAM (2KB)

restrictions 0x23FF
– Designed for modern
programming
0x4400
FRAM (17408
techniques such as 0xFFFF bytes)
pointers and fast look-
up tables
Instruction Format
.w for word (i.e. 16 bits) operations
.b for byte (i.e. 8 bits) operations
mov.w src,dest
Source operand Destination operand

dest  src
Copy or load source to destination

Addressing Modes
• The MSP430 supports seven addressing modes
for the source operand and four addressing
modes for the destination operand
Source Destination
Mode Description
Operand Operand
Register X X Single cycle
Indexed X X Table processing
Symbolic X X Easy to read code, PC relative
Absolute X X Directly Access any memory
Indirect Register X Access memory with pointers
Indirect autoincrement X Table processing
Immediate mode X Unrestricted constant values

Register Mode: mov R8,R6
• Content of the register R8 is copied to R6
• Current R6 value is overwritten after the
operation
• R8 value does not change
• Operation is performed within the
microprocessor. No address bus, data bus
and control bus is involved.

MOV register to register
mnemonic: MOV R8, R6
op-code: 0x4846 (hex)
operation: Move register 8 (src) content
to register 6 (dest)
addresses
increasing
48
op code for MOV
46

Indirect Register: mov @R8,R6
• Content of the memory pointed by register
R8 is copied to R6
• Current R6 value is overwritten after the
operation
• R8 value does not change
• Address, data and control buses are used to
get the data pointed by R8.

MOV indirect register to register
mnemonic: MOV @R8, R6
op-code: 0x4866 (hex)
operation: Move the content of memory
address pointer by register 8
(src) content to register 6 (dest)
addresses
increasing
48
op code for MOV
66

Why two instructions with the
same mnemonic?
MOV R8, R6
MOV @R8, R6
• They perform the same operation, but the source is different

• We say they use different addressing modes
• Customarily, the same mnemonic is used for all operations
that perform essentially the same operation, and differ only
in their addressing modes
• It’s the syntax (in assembly code) which differentiates them

Example MSP430 Instructions
Assembly RTN Comment

mov src,dest dest  src Copy or load source to destination
add src,dest dest  dest + src Add source to destination
sub src,dest dest  dest – src Subtract source from destination
and src,dest dest  dest .AND. src Bitwise AND source to destination
xor src,dest dest  dest .XOR. src Bitwise XOR source to destination
cmp src,dest dest - src Compare does not affect dest. Only flags

Addressing Modes
• Addressing modes are the methods how a
microprocessor architecture specifies the
address of an object (i.e. bytes in memory,
register, etc) they want to access.
• There are 7 addressing modes in MSP430
architecture.
• All seven addressing modes for the source
operand and all four addressing modes for the
destination operand can address the complete
address space.
Addressing Modes Example
MOV register mode to move R8 value to R6 can be
written as :
MOV R8,R6 0x4846
operands
MOV indirect register mode to move the content of
memory location pointed by R8 value to R6 can be
written as :
MOV @R8, R6 0x4866
operands
The @ sign distinguishes between them
Are Instruction Codes random?
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Op-Code S-reg Ad b/w As D-reg
MOV.W R8, R6
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 1 0 0 0 0 1 0 0 0 1 1 0
.W
MOV (4) R8 R6
Register Addr. mode
MOV.W @R8, R6
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 1 0 0 0 0 1 1 0 0 1 1 0
.W
MOV (4) R8 Indirect R6
Register Mode
Register Mode
45
The Instruction Execution Cycle
MSP430 Example
MOVE: copy an 16 bit constant value 0x300 (hexadecimal) into
the register R6 in CPU
MOV.W #0x300,R6
MOVE: copy the content of a memory location pointed by R6
to the register R7 and R6 is incremented by one.
MOV.B @R6+,R7
ADD: add the content of the memory location pointed by R6 to

the register R7 then increment R6 by one.
ADD.B @R6+,R7
STORE: copy the content of R7 the memory location pointed by
the address R6+2.
MOV.B R7,2(R6)
Assembly  Machine Code
Assembly language facilitates to write programs for humans.
Assembler program converts assembly programs to machine
code. Machine code equivalent
starting at some memory location
Assembly language ..
program 0x40
0x36 MOV #0x300,R6
MOV.W #0x300,R6 0x03
0x00
MOV.W @R6+,R7 Assembler 0x46
MOV @R6+,R7
0x37
ADD.W @R6+,R7 0x56
0x37
ADD @R6+,R7
MOV.W R7,0(R6) 0x47
0x16 MOV.W R7,2(R6)
0x00
0x02
Assembler
Source files
Object
*.asm, headers, Assembler
etc Files
Libraries
Linker
Object File
Linker uploads data and
Execute file in memory
At addresses specified by Loadable and
Map files, etc
Assembler using specifiers. Executable File

Endian-ness
• When we write a 16 bits to memory, how is it
stored?
Address ..... .....
1000 0x11 0x22
1001 0x22 0x11
mov.w #1000,R6
mov.w #0x2211,0(R6) 1002 0x00 OR 0x00
1003 0x32 0x32
1004 0x44 0x44
0x2211 1004 0x75 0x75
….. …..
High Byte Low Byte
Endian-ness
• MSP430 is a little endian microprocessor.
• Little Endian  Small end in First
– When we write a 16 bit number in a memory location, the
first byte of memory (i.e. lower memory) contains the lower
portion of the 16 bit number.
• Low byte  Low memory
• Big Endian  Big End in First
• Intel processors are the examples of Little Endian
machines.

Machine Language Execution
How Machine Language Programs

Are Executed on the CPU?

MOV.W #0x300,R6
• Step 1: Assume R0=0x0200. 0x0200 is
placed on A-bus and READ issued. (R0 is the
PC)
• Step 2: 16-bit content at location 0x200 (16
bits) is returned on data bus and placed in the
Instruction Decode Register (IDR) in the
control unit.
– PC is incremented by 2 to become 0x202
– The machine instruction loaded into IDR will be
analyzed to understand what to do next in the
control unit.
MOV #0x300,R6
..
Step 1: A-bus (0x0200-READ) 0x40 [0x0200]
0x36 [0x0201]
0x03 [0x0202]
0x00 [0x0203]
0x46 [0x0204]
0x37 [0x0205]
CPU 0x56 [0x0206]
0x37 [0x0207]
IDR
IDR 0x46 [0x0208]
..
D-bus 0x01 [0x0300]
0x00 [0x0301]
Step 2: 0x4036 is returned 0x01 [0x0302]
on D-bus. 0x02 [0x0303]
R0 (PC)  0x0202
MOV #0x300,R6
(0x40 0x36 0x03 0x00)
• Step 3: Control unit (decoder) recognizes LOAD
(MOV) instruction. This instruction needs 2-byte
value for operand address.
– Issues a 16 bit READ cycles
• address bus-READ-0x0202 data bus returns 0x0300
– Copies 0x0300 to MDR (Memory Data register)
– At the end PC becomes 0x0204
• Step 4: Execution of the instruction requires the
microprocessor copy 0x0300 in MDR to register
R6. It executes the command.

MOV #0x300,R6
Step 3: A-bus (0x0202 – 16 bits) ..
0x40 [0x0200]
0x36 [0x0201]
0x03 [0x0202]
0x00 [0x0203]
0x46 [0x0204]
0x37 [0x0205]
CPU 0x56 [0x0206]
0x37 [0x0207]
IDR MDR 0x46 [0x0208]
..
0x0300 0x01 [0x0300]
0x00 [0x0301]
0x0300 is returned on D-bus 0x01 [0x0302]
and put into Memory Data 0x02 [0x0303]
Register (MDR)
MOV #0x300,R6
Step 4: Execution within the micropressor
İs finished by copying MDR to R6
..
0xB6 [0xC000]
0xD0 [0xC001]
0x00 [0xC002]
0xBB [0xC003]
0xD0 [0xC004]
CPU 0x01 [0xC005]
0xB7 [0xC006]
IDR
0xD0 [0xC007]
MDR R6 0x00 [0xC008]
..
0x19 [0xD000]
0x37 [0xD001]
..

Addressing Modes
One instruction, multiple meanings

Addressing Modes
• “Addressing Modes” is the technical term for
the various different ways that arguments for
machine instructions can be specified
• It is common practice for CPUs to provide
several machine codes for each basic
operation: one code for each addressing mode
that makes sense with this operation.

Anatomy of an Instruction
• Opcode
– What the instruction does – verb
– May or may not require operands – objects
• Source Operand
– 1st data object manipulated by the instruction
• Destination Operand
– 2nd data object manipulated by the instruction
– Also where results of operation are stored.
• Addressing Modes
– source and destination
• Operates on byte or word?
Opcodes

Instruction Format
• There are three formats used to encode instructions for
processing by the CPU core
– Double operand
– Single operand
– Jumps
• The instructions for double and single operands,
depend on the suffix used, (.W) word or (.B) byte
• These suffixes allow word or byte data access
• If the suffix is ignored, the instruction processes word
data by default

Instruction Format Fields
• The source and destination of the data operated by an
instruction are defined by the following fields:
– src: source operand address, as defined in As and S-reg
– dst: destination operand address, as defined in Ad and D-reg
– As: addressing bits used to define the addressing mode used
by the source operand
– S-reg: register used by the source operand
– Ad: Addressing bits used to define the addressing mode
used by the destination operand
– D-reg: register used by the destination operand
– b/w: word or byte access definition bit.

MSP430 Instruction Formats
• Format I: Instructions with two operands
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
• Format II: Instruction with one operand

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Op-code bw Ad D/S-reg
• Format III: Jump instructions

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Op-code Condition 10 bit, 2’s complement PC offset

Source Addressing Modes
• The MSP430 has four basic modes for the source
address:
– Rs - Register
– x(Rs) - Indexed Register
– @Rs - Register Indirect
– @Rs+ - Indirect Autoincrement
• In combination with registers R0-R3, three additional
source addressing modes are available:
– label - PC Relative, x(PC)
– &label – Absolute, x(SR)
– #n – Immediate, @PC+

Destination Addressing Modes
• There are two basic modes for the destination
address:
– Rd - Register
– x(Rd) - Indexed Register
• In combination with registers R0/R2, two
additional destination addressing modes are
available:
– label - PC Relative, x(PC)
– &label – Absolute, x(SR)

Register Mode (Rn)
• It is most straightforward addressing mode and is available for
both source and destination
mov.w r5,r6 ; move word from r5 to r6
• The registers are specified in the instruction; no further data is

required.
• Also the fastest mode and does not require an additional cycle
– Byte instructions use only the lower byte, but clear the upper byte when
writing
0 1 0 0 0 1 0 1 0 0 0 0 0 1 1 0

Indexed Mode x(Rn)
• The address is formed by adding a constant (index) to the
contents of a CPU register
– Example:
mov.b 3(r5),r6 ; move byte from
; M(310+r5) to r6
• Indexed addressing can be used for source and/or destination,
value in r5 is unchanged.
• The index is located in the memory word following the
instruction and requires an additional memory cycle
• There is no restriction on the address for a byte, but words must
lie on even addresses
0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0

Symbolic Mode (PC Relative)
• The address is formed by adding a constant (index) to the program
counter (PC)
– Example: (Actual instruction: mov.w x(PC), r6 where x=Cnt-PC)
mov.w Cnt,r6 ; move word
; M(Cnt+PC) to r6
• The PC relative index is calculated by the assembler
• Produces position-independent code, but rarely used in the MSP430
because absolute addressing can reach all memory addresses
• Note: this is NOT an appropriate mode of addressing when
referencing fixed locations in memory such as the special function
registers (SFR’s)
0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0

Absolute Mode (&label)
• The address is formed directly from a constant (index) and specified by
preceding a label with an ampersand (&)
– The actual instruction is mov.w x(SR), r6 where 0 is used for SR)

mov.w &Cnt,r6 ; move word
; M(Cnt) to r6
• Same as indexed mode with the base register value of 0 (by using the status
register SR as the base register)
• The absolute address is stored in the memory word following the instruction
and requires an additional cycle
• Note: this is the preferred mode of addressing when referencing fixed
locations in memory such as the special function registers (SFR’s)
0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0

Indirect Register Mode (@Rn)
• The address of the operand is formed from the contents of the
specified register
– Example:
mov.w @r5,r6 ; move word
; Content of memory
; location pointed
; by r5 to r6
• Only available for source operands
• Same as indexed mode with index equal to 0, but does not
require an additional instruction word
• The value of the indirect register is unchanged
0 1 0 0 0 1 0 1 0 0 1 0 0 1 1 0

Indirect Autoincrement Mode (@Rn+)
• The address of the operand is formed from the contents of the specified
register and afterwards, the register is automatically increment by 1 if a byte is
fetched or by 2 if a word is fetched
• Example:
mov.w @r5+,r6 ; move word
; M(r5) to r6
; increment r5 by 2
• Only available for source operands.
• Usually called post-increment addressing.
• Note: All operations on the first address are fully completed before the second
address is evaluated
0 1 0 0 0 1 0 1 0 0 1 1 0 1 1 0

Immediate Mode
• The operand is an immediate value
mov.w @PC+,r6
– Example:
mov.w #100,r6
• The immediate value is located in the memory word following the
instruction
• Only available for source operands
• The immediate addressing mode is a special case of autoincrement
addressing that uses the program counter (PC) as the source
register.
• The PC is automatically incremented after the instruction is
fetched; hence points to the following word
0 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0
Week 2: Addressing Modes

72
Addressing Modes
As/Ad Addr. Mode. Syntax Description
00/0 Register mode Rn Register contents are operand
(Rn+X) points to the operand. X is stored şn

01/1 Indexed mode X(Rn)
the next word
(PC+X) points to the operand. X is stored in
01/1 Symbolic mode ADDR
the next word. Indexed mode X(PC) is used
The word following the instruction contains
01/1 Absolute mode &ADDR the absolute address. X is stored in the next
word. Indexed mode X(SR) is used.
10/- Indirect Register @Rn Rn is used as a pointer to the operand.
Rn is used as a pointer to the operand. Rn is

11/- Indirect Autoincrement @Rn+ incremented by 1 for .B instructions and by 2
for .W instructions.
The word following the instruction contains
11/- Immediate mode #N the immediate constant N. Indirect
autoincrement mode @PC+ is used.

Addressing Mode Summary
Addr. Mode Src Dst Syntax Example
Register X X MOV Rs,Rd MOV R10,R11
Indexed X X MOV X(Rs),Y(Rm) MOV 2(R5),6(R6)
Symbolic (PC
X X MOV SRC, DEST
relative)
Absolute X X MOV &MEM,&TCDAT
Indirect X - MOV @Rn,Y(Rm) MOV @R10,90(R6)
Indirect
X - MOV @Rn+, Rm MOV @R10+,R11
Autoincrement
Immediate X - MOV #X,DEST MOV #45, R6

Examples – Source
Registers Values Memory Values
R5 0010 0x9000 000f
R6 0020 0x9002 0010
R7 9000 0x9004 0011
R8 9004 0x9006 0012
R9 9006 0x9008 0013
mov.w R5,R6 move the content of R5 (0010) to R6

mov.w @R7,R8 use the content of R7 (9000) as the address to move data to R8
mov.w &var1,R6 go to absolute address to move data (0011) to R6
mov.w 1(R7),R9 use the content of R7 as the base adress and offset it by 2 (9002)
to move data (0010) to R9
mov.w @R7+,R6 use the content of R7 (9000) to move data (000F) to R6 and
then increment R7 by 2 (one word is 2 bytes)
mov.w #0x9000,R7 move the immediate value (9000) to R7
mov.w label,R7 move the data (0012) in the memory space represented by
«label» to R7
Examples – Destination
Registers Values Memory Values
R5 0010 0x9000 000f
R6 0020 0x9002 0010
R7 9000 0x9004 0011
R8 9004 0x9006 0012
R9 9006 0x9008 0013
mov.w R5,R6 move the content of R5 (0010) to R6

mov.w R5,4(R7) use the content of R7 (9000) as the base address and offset it
by 4 16 bits(9008) and move the content of R5 (0010) to the
effective address (9008)
mov.w R6,label move the content of R6 (0012 moved from R5) to the memory space
represented by “label”
mov.w &0x9004,&0x9008 go to the absolute address (9004) to move data (0011)
to the memory location of the absolute address (9008)
mov.w R6, label move the content of R6 (0012 moved from R5) to the memory
space represented by the absolute address «label»
Constant Generator Registers
• Depending of the source-register addressing
modes (As), six constants can be generated
without code word or code memory access
to retrieve.
mov.w 1200(R2),r6
Accesses memory address 1200
mov.w &1200,r6
HOW TO WRITE, ASSEMBLE
AND UPLOAD TO
LAUNCHPAD
Software for MSP430FR5969
• In order to use the launchpad you are provided, you
need to access the following web address
http://software-dl.ti.com/ccs/esd/documents/ccs_downloads.html
• You are supposed to install the following software
– CCS: Code Compose Studio. An Integrated Debugger
Environment (IDE) for programming the MSP430FR5969
launchpad
– MSP430 Flasher to install programs into flash of MSP430
microprocessors
Downloading Software
Code Composer Studio
• Code Composer Studio is an integrated development
environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio.
• Code Composer Studio comprises a suite of tools used to
develop and debug embedded applications. It includes an
optimizing C/C++ compiler, source code editor, project build
environment, debugger, profiler, and many other features.
• The IDE provides a single user interface taking you through
each step of the application development flow.
• Code Composer Studio combines the advantages of the Eclipse
software framework with advanced embedded debug
capabilities for embedded developers.

Creating an Assembler Project
• On CCS, click «New» and then «CCS Project»

Creating an Assembly CCS Project
• On the window, as
«Target» choose
MSP430FR5969
• Write a project name
such as «trial1»
• On the «project
templates and
examples», choose
«Empty Assembly-
only Project»
• Press «Identify» to
check whether the
card needs a firmware
update or not
• Then click «Finish»
main.asm
Do NOT change!!!!
Add your variables
Do NOT change!!!!
Write your code here
Do NOT change!!!!

Adding two 16 bit values
;-------------------------------------------------------------------------------
; MSP430 Assembler Code Template for use with TI Code Composer Studio
;-------------------------------------------------------------------------------
.cdecls C,LIST,"msp430.h" ; Include device header file
.def RESET
.text ; Assemble into program memory.
.retain
.retainrefs
.global add16
add1 .word 0x5463
add2 .word 0x1234
;-------------------------------------------------------------------------------
RESET mov.w #__STACK_END,SP ; Initialize stackpointer
StopWDT mov.w #WDTPW|WDTHOLD,&WDTCTL ; Stop watchdog timer
; Main loop here
mov.w add1,r15 ; content of add1 is copied to r15
mov.w add2,r14 ; content of add2 is copied to r14
add.w r14, r15 ; r15 = r14 + r15
jmp $ ; stuck here
nop ; required no operation
; Stack Pointer definition
.global __STACK_END
.sect .stack
; Interrupt Vectors
.sect ".reset" ; MSP430 RESET Vector
.short RESET
Debug the Code
• Click on «debug» button to assemble and
upload to the board
Click to start debugging

Debug the Code
• The program is assembled and uploaded to
the board and «CCS Debug» is activated.
For running the whole For stopping the debug

Code at once Operation. Get back to Edit mode
• In the «CCS Debug», you are allowed to
run the code one line by one line.
Running the code
• The highlighted line identifies where we are,
i.e. where the R0 or PC points to.

Debugging the Code
• You can use these two buttons to run a single
line or getting into functions.
Assembly step into Assembly step over

(get into the function) (execute the line)

Seeing Registers
• You can see the registers in the Register Tab

Seeing Registers
• If you click on «Assembly step into», you
execute a line and any changed registers will
be shown on the register tab in yellow.

Seeing SR Flags
• Click on the SR on register tab to see each flag

What are breakpoints?
• A breakpoint is a signal that enforces the
debugger to temporarily suspend the
execution at a certain point.
• You just place a breakpoint on the line
where you want to stop. When you execute
the code, the debugger stops at the
breakpoint.
• Right click on the code line to leave a
breakpoint
Breakpoints

Breakpoints
• On the left side of the line where you leave
a breakpoint, the line is identified by a
symbol. Click on to run and stop there.
breakpoint

Breakpoints
• Breakpoints are useful in order to examine
certain parts of the code.
• If there is a suspected problem, you can start
debugging the program from that point on.
• You can check registers, variables, etc.
• You can search the program areas that don’t
work as they are supposed to.

EEM336 Week02 Addr Modes

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Week 2

Week 2: Addressing Modes 2

• Go to Code composer Studio section on TI’s

• Download the latest version and install for

The commands (numbers) that the

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A set of binary codes that are

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• We can group the instructions according to

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0 GPR 15 R4 (General Purpose Register)

R2, SR or CG1 (Status Register)

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data and peripherals

Flash or RAM with no RAM (2KB)

Source operand Destination operand

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• They perform the same operation, but the source is different

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Assembly RTN Comment

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ADD: add the content of the memory location pointed by R6 to

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How Machine Language Programs

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One instruction, multiple meanings

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• Format II: Instruction with one operand

• Format III: Jump instructions

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mov.w r5,r6 ; move word from r5 to r6

• The registers are specified in the instruction; no further data is

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