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DOI 10.1007/s11265-011-0640-8
Received: 30 September 2011 / Revised: 28 October 2011 / Accepted: 7 November 2011 / Published online: 30 November 2011
# Springer Science+Business Media, LLC 2011
SPI
Control
A compact three-staged hardware stack was developed Linux OS
MAC
FSM
Config Regs.
Serial,
according to the photo in Fig. 2 and the corresponding
LP
Monitor
16 bit DAC
I/O Expansion (Spartan 3)
Application Software
PCIe Interf.
block diagram in Fig. 3. It is used in exactly the same
Dual
Ethernet
Driver
Frontend Board
PCIe
PCIe Interf.
configuration for the UGV, the UAV and the GCS. It DDR
LP
TX
combines a nanoETXexpress-SP Board from Kontron with USB
I/Q
Processing
Baseband
a 1.6 GHz Intel Atom Processor Z530 [15], a Xilinx Virtex
Packet Buffers
ADC
14 bit
LP
5 FPGA, coming as Express Card version from Pico
Waveform
Control
Ethernet DDR
Computing [16] to be inserted in a PCIe-based slot of the RX
ADC
14 bit
GUI
LP
Kontron board and a self-designed interface board. As I/Q
3.1 The Interface Board In order to achieve high signal processing performance, all
the OFDM baseband processing is done within the Xilinx
The hardware platform is combinable with any propri- Virtex 5 FPGA. Beside baseband processing, another major
etary or commercial-off-the-shelf (COTS) RF transceiv- function block of the FPGA is the TDMA MAC control,
er hardware. For this reason, a front-end interface board realized as a finite state machine (FSM).
was designed to offer analog baseband I/Q signal ports. Multiple first-in-first-out (FIFO) buffers are imple-
The board comprises a dual 16 bit 500 MSPS DAC for mented for temporary IP packet storage in order to
the transmitter path (currently 14 of 16 available bits in decouple the data stream, as it passes from the GPP-
use) and two 14 bit 125 MSPS ADCs for the receiver based application layer to the FPGA-based MAC layer.
path. As already mentioned, this interface is realized with
A downside of the Virtex 5 FPGA Express Card is PCIe, and it serves not only for exchanging payload
its limited number of free I/O ports. This number would data, but also for configuring the waveform: All flexible
be too small for the exchange of full 14 bit I and Q waveform parameters are set on runtime according
signals. The workaround to this problem is I/O port PCIe-fed signals, which are stored in a configuration
expansion with a second FPGA, a low-cost Xilinx RAM register in the FPGA. Polling this configuration
Spartan 3. Therefore, data is exchanged between the register for every new data frame allows frame-wise
Virtex 5 and the interface board on both edges of the parameter updates.
clock signal. More precisely, I data is exchanged on Beside payload data and parameter control, the third
rising edges and Q data on falling edges. This double signal type which is transmitted via PCIe contains
data rate transfer (DDR) is then resolved to single data information about relevant internal FPGA signals. This
rate transfer using the Spartan 3. information is required to evaluate the suitability of the
Low pass filters are included at the frontend I/O ports current waveform parameter set. Details of these monitor-
against aliasing effects. ing signals are given in Section 7.
For the Ethernet interface, an adequate driver was Fortunately, there was no claim for complying with any
implemented also in C language. It offers a standard Linux common OFDM wireless standard like DVB, IEEE 802.11a
network interface for the IP payload data, with the or WiMAX, so there was any freedom to pick up common
opportunity to set priorities for the different ports, namely ideas and disregard others. Just to name one example for an
the video port and the control port. As a consequence, the adoption from IEEE 802.11a, the synchronization algorithm
complete data link is fully transparent to the application and the Automatic Gain Control (AGC) setting was imple-
software. It does not even notice that a wireless link instead mented according Fort’s and Eberle’s proposal [20, 21].
of a cable underlies. The broad parameter flexibility must not only apply to
Since the GPP runs under Linux OS, any standard the waveform in general but for each logical link (video
application software is easily applicable to the SDR link, control link) independently of the other. So the idea is
platform. For this project, applications as the camera driver to have two sets of parameter settings, one referring to a
or video compression software are running on the Intel robust channel with low throughput for control data and
Atom. However, since this is no primary focus of this another one providing high throughput at the expense of
article, we will not go into details here. reliability for video data. Since subsets of subcarriers are
freely assigned to the individual links (video/control), they
can be transmitted simultaneously. This technique is
4 Baseband Processing commonly known as OFDMA (orthogonal frequency
multiple access).
Coming with the benefits of great spectral efficiency and Figure 5 gives a simplified overview of the whole
robustness in multipath environments, OFDM is the commu- functionality of the central part of the waveform, which is
nication scheme of choice when UAV systems require high the FPGA part. Control signals are illustrated with thin
data rates in heterogeneous outdoor scenarios [17, 18]. arrows and data signals with thick arrows. All function
Further advantages of OFDM are its efficiency in imple- blocks are self-designed, except for the IFFT/FFT, the En-
mentation based on FFT/IFFT processing and its efficiency and Decoder and the PCIe Interface, which are standard
in channel equalization within the frequency domain [19]. Xilinx IP cores.
J Sign Process Syst (2012) 69:11–21 15
PCIe Domain
PCIe Domain Baseband Domain
Baseband Domain
Frontend Config
(65.2 MHz Clock)
(65.2 MHz Clock) (100 MHz (100 MHz Clock)
Clock or 48 MHz Clock)
Interface
Config Reg. Frontend Config
Frontend Config Interface State Machine
(e.g. SPI)
DMA/Sys Config MAC State Machine
BERT
TX System Generator Model
Video
TXTX
Control
Control
State
State
Machine
Machine
BERT
TX
Control
TX Buf Video
MUX
HDLC Scramble Convol. Interleave QAM I
FIFO Scrambler Interleaver
Sync Symbol
Conditioning
Pilot Symbol
Serializer
Cyclic Prefix
I/Q Samples
Serializer r Encoder r Mapper Q
Windowing
I/Q Sample
Insertion +
Insertion
Insertion
Scaling
I I I I
TX
TX Buf Control IFFT
Config Q Q Q Q
HDLC
MUX
Calcul
ation
RSSI
RXRX
Control
Control
State
State
Machine
Machine
Detectio
RX Buf Video
Detect
Sync
Sync
Config
Correl
Auto-
ation
FIFO
HDLC
De- De- De- QAM
Offs. Correction
RX Buf Control Serializer Scramble Interleave De-
Conditioning
Carrier Freq.
FIR Filtering
I/Q Samples
Control Scrambler Decoder Interleaver Q
I/Q Sample
Assembler
Assembler
Config r r Mapper
Scaling
I II I I I
Channel
Channel
RX
FIFO FFT
DMA HDLC Equalization
Equalization
Q QQ Q Q Q
Read De- De- De- QAM
De- Viterbi De- I
Serializer Scramble Interleave De-
Scrambler Decoder Interleaver Q
r r Mapper
BERT
RX
BER Video I/Q signal I/Q signal
monitor BERT monitor monitor
RX
Control
As depicted at the top of Fig. 5, the entire frontend Since there is no need to change the frontend on runtime,
configuration, namely the AGC and transceiver setting, is there is also no runtime-configurable baseband clock
realized with simple FSMs. At the lower left part of required. Instead, the clock is defined before synthesizing
Fig. 5, the PCIe interface is shown, which serves for the design. With the 100 MHz oscillator, which drives the
video and control data exchange via IP frames on FPGA, a 100 MHz baseband domain and a 48 MHz were
network layer. These IP frames will be serialized to already realized and tested.
bitstreams within the High-Level Data Link Control
(HDLC) blocks on the transmitter side (TX). On the
receiver side (RX), similar HDLC blocks de-serialize the 5 Runtime Flexible TDMA
bitstreams again.
A similar structure of what is shown from those The channel access of the different users (UGV, UAV and
HDLC blocks on to the right-hand edge of Fig. 5 can GCS) is organized with TDMA. As depicted in Fig. 6, the
be found as standard OFDM baseband processing chain in top layer of the time schedule is made up of a periodically
every OFDM book (disregarding the OFDMA aspect) repeated TDMA superframe. This superframe is then sub-
[22]. Within this processing chain, the bitstream is divided into 64 TDMA slots or less, all of the same length.
mapped to I/Q constellation points (frequency domain) Within each TDMA time slot, only one user is transmitting
and finally transformed to I/Q time domain signals using while the rest is listening. This means, a half-duplex
an IFFT. communication system is provided.
Although the PCIe interface runs natively with Once the traffic demand of the different users is
65.2 MHz, the ideal clock for the baseband domain identified, the slots can be portioned accordingly: The
could differ from that for an optimal match with a more traffic a user requires, the more slots are reserved for
specific frontend. For this reason, two internal clock him to transmit.
domains are realized with the aid of a digital clock The users are not equal. One master node must be
manager and buffers, one for PCIe and one for the chosen to set the timing of the superframe by inserting a
baseband domain. superframe start indicator in the first slot of the schedule.
16 J Sign Process Syst (2012) 69:11–21
Superframe
Fr up A
S DM
am e r
Start Indicator one in the superframe schedule2 and a Pilot Symbol for
channel and fine frequency offset estimation [23, 24].
T
1 2 3 4 5 6
waveform offers a variety of configuration options for the
Sl M
(max. 64)
s
TD
SF Sync
AGC
Data
am M
Data
Data
...
Fr FD
e
O
Control Data
Windowing/2
Cyclic Prefix
Cyclic Prefix
Stream
Windowing
Windowing
Windowing
Windowing
Windowing
the OFDM frame should be generally chosen as long as
m DM
ls
Pilot
bo
Video Data
Sy OF
An essential challenge of the presented scenario is the high In the previous section, three options for subcarrier
speed the UAV is able to reach. The top speed depends on allocation were presented. In order to account for the
several aspects and can reach up to 120 km/h. With the scenario-specific problem of fast changing channels, yet
UGV moving in the opposite direction, the relative velocity another option is provided, which is the use of subcarriers
would be even higher. Specifically, in OFDM communica- as scattered pilots.
tion, high speed leads to much shorter coherence time and As already mentioned, the first OFDM symbol of each
larger Doppler frequency spread, especially for the case that OFDM frame is filled with pilots, which are known data to
a high RF carrier frequency is used. As a direct result, the identify the transfer function of the system. The correction
orthogonality among subcarriers gets lost and ICI degrades values calculated with these pilots for each subcarrier are
the performance [26]. The solution to this problem is to
broaden the frequency spacing between the subcarriers for
increased tolerance against orthogonality loss. This can be
achieved by decreasing the FFT length, because this
parameter is indirect proportional related to the frequency
spacing. So in order to strengthen against Doppler shift, an
adequate FFT length out of the following can be chosen: 8,
16, 32, 64, 128, 265, 512 or 1,024.
sion errors with the aid of a Viterbi decoder, completely The developed GUI not only visualizes the I/Q constella-
without further inquiry [33]. tion, but also provides with the error vector magnitude (EVM)
For the presented waveform, a Viterbi decoder IP core a corresponding performance metric. The EVM describes the
from Xilinx was applied [34]. Its code rate, meaning the deviation of the measured transmitted signal against a perfect,
ratio of payload to redundancy, is flexible from 1/2 to 1/7. theoretical signal [37]. The GUI supports plotting the EVM
With puncturing, the code rate can be increased up to 3/4 or versus subcarrier or versus symbol. This can be crucial in
7/8 [35]. allowing the operator to quickly locate the source of errors,
such as strong faded frequencies (EVM versus subcarrier) or
fast changing channels (EVM versus symbol).
7 System Performance Monitor
In the previous section, all run-time flexible OFDM param- 8 Designing and Testing the Waveform
eters of the waveform were introduced. The question remains
how to choose them in an adequate way for optimal The process of developing the waveform can be divided
performance in terms of the current nonideal channel into three major steps.
characteristics. For evaluating the temporary system perfor- At first, the software/hardware design: The PCIe and
mance, two general monitoring tools are provided: A bit error Ethernet drivers, as well as the waveform control were
rate tester (BERT) and different options to analyze the I versus implemented in C language. The FPGA design was done with
Q constellation diagram. a hybrid approach of pure VHDL and a model driven design
environment based on MathWorks Matlab/Simulink including
7.1 Bit Error Rate Monitor the System Generator for DSP from Xilinx. This approach
allows at a very early stage elaborated simulations, e.g. with the
During normal operation, the control and video data is Simulink multipath Rayleigh or Rician fading channel models.
exchanged via PCIe as described in Section 4. However, Second, testing on the SDR hardware was performed
when the BERT is applied, the system is alternatively fed within a predefined environment. More precisely, the fading
from a source for pseudo random bit sequences (PRBS). At channel simulator R&S AMU200A was deployed to stress
the receiver part, a second PRBS generator is synchronized the waveform with a set of specific static and dynamic
with the incoming data stream in order to evaluate the bit fading scenarios, as well as Doppler and AWGN noise real-
error rate. Since this number is directly transmitted to the time simulations.
GPP and indicated with the QT-based GUI, real-time The final step for the waveform to pass is the test with the
measurements are available. UGV, the UAV and a GCS in the open field. There are two
Of course, error rate testing is also possible with IP types of UAVs in use. On the one hand this is the self-designed
pinging, but this would only provide information about the UAV in Fig. 1 with the maximum speed of 70 km/h and on
IP packet loss rate and not about the bit error rate. The the other hand this is a Swiss UAV, NEO S-300 series, which
packet loss rate is less significant, because a packet will be flies with up to 120 km/h [38]. The applied UGV is the rover
discarded, no matter if there was only one false bit in the MERLIN, which was designed for robust operations in harsh
packet or multiple ones. outdoor environments. Its maximum speed is 12 km/h [39].
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