Cadence Design Systems, Inc.

RAPID ADOPTION KIT

Interface Logic Model (ILM)

Using Innovus

Note: Testcase database, Scripts and references can be found at

‘Attachments’ and ‘Related Solutions’ sections below the PDF on
https://support.cadence.com. This pdf can also be searched with the document
'Title' on Cadence Support Portal

Version: Innovus 17.1

August 2017

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 Table of Contents
Lab 1-1 Floorplan and Generate Partition Block-level Design ..................................................... 1
Objective: To generate timing budgets for partitions for standalone implementation.............. 1

Lab 1-2 Create ILM Model .......................................................................................................... 4

Objective: Create ILM model for all blocks ............................................................................. 4

Lab 1-3 Specify ILM Model ........................................................................................................ 6

Objective: Specify ILM data directory for the specified block ................................................. 6

Lab 1-4 Update SDC Constraints ................................................................................................. 7

Objective: Do final earlyGlobalRoute using partition pins and final timing check .................. 7

Lab 1-5 Optimize design .............................................................................................................. 8

Objective: Optimize timing for the design with ILM involved ................................................. 8

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Lab 1-1 Floorplan and Generate Partition Block-level Design

Objective: To generate timing budgets for partitions for standalone implementation

In this lab, you will generate timing budgets for each partition that will be used for block
implementation. Also convert the specified partition fences to partition blocks, and save the partition
information to the current directory or a specified directory.

Design Information

The design contains 2887 instances, 71 I/O pins and 5 macros. The design is hierarchical with top
module as dtmf_recvr_core . The design uses process technology with 9 metal layers, 7 of which are
used for signal routing.

RAK Database

Testcase database, Scripts and references can be found at ‘Attachments’ and ‘Related Solutions’
sections below the PDF.
This pdf can be searched with the document 'Title' on https://support.cadence.com

Starting the Software

Start Innovus by entering following. This lab had been prepared by using Innovus
version 17.10-p006
cd 17.10_ILM_RAK
Innovus

This lab assumes that the partitions and partition pins are already defined. This part of the
lab will not work without partition definition.

Source ./script/create_ptn_ilm.tcl will finish Lab 1-1 to Lab 1-2. The script invokes
timing budget, partition, create ILM model.

source ./script/create_ptn_ilm.tcl

Source ./script/opt_ilm.tcl will finish Lab 1-3 to Lab 1-5. The script invokes specify ILM
model, update SDC constraints, optimize design.

source ./script/opt_ilm.tcl

Source ./script/run.tcl will finish Lab 1-1 to Lab 1-5, which will run the complete flow with
source create_ptn_ilm.tcl and opt_ilm.tcl

source ./script/run.tcl
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1. Load design with good partition definition
set dataDir [pwd]/design
set libDir [pwd]/libs
source design/dtmf_recvr_core.enc

2. Run createActiveLogicView to trim the timing graph to ignore logic inside the first level
registers in partitions. If you do not specify -type flatTop, timing-related commands must
operate on the entire flat netlist rather than on the virtual partition version.
createActiveLogicView -type flatTop

3. Run deriveTimingBudget to budget timing based on partition result. For MMMC mode,
budgeting files are generated per view and per partition.

deriveTimingBudget

4. Run clearActiveLogicView to reset the reduced timing graph created by

createActiveLogicView back to the original timing graph.

clearActiveLogicView

5. Run partition to convert the specified module fences to be partitions, push down the
physical cells or power routing information to the partition level design, and duplicates
strips in the partition that overlap with the partition boundary at their original widths.
2
 partition

6. Run savePartition to generate needed data for top-level and block-level implementation.
-def is needed to write out DEF format files for the design.
savePartition -lib -dir PTN -pt –def

After savePartition, there will be 4 directories are generated under PTN.

dtmf_recvr_core is for top-level and tdsp_core, ram_128x16_test, ram_256x16_test are
for block-level.

3
Lab 1-2 Create ILM Model

Objective: Create ILM model for all blocks

In this lab, you will create a reduced set of instances representing only the interface paths, that is,
paths from the I/O ports of the design to the first level of sequential instances for all the blocks.

1. For each block, block level implementation should be finished first.

set ptnNameList {tdsp_core ram_128x16_test ram_256x16_test}

foreach ptnName $ptnNameList {
cd PTN/${ptnName}
restoreDesign . ${ptnName}
placeDesign
routeDesign
setAnalysisMode -analysisType onChipVariation
optDesign –postRoute
saveDesign ${ptnName}_data.enc

2. Run createInterfaceLogic to generate ILM data.

createInterfaceLogic -dir ilm
cd ../..
}

• The following is a sample summary report generated at the end of the

createInterfaceLogic command for tdsp_core.

In this report, the reduction ratio in the ilm_data model is 80 percent which means that
1834 out the total 2291 instances for this block have been eliminated. Only 457
instances are written to the Verilog netlist for the ilm_data model out of which 101
instances are registers.

When createInterfaceLogic is called, all views are generated for

multi-corner, multi-mode (MMMC) analysis.

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• Two types of ILM data

 ilm_data

The timing and CTS models have been merged in to ilm_data to reduce the
disk usage of an ILM model. The CTS data is limited to the worst clock
sinks and instances/nets leading to those sinks.

 si_data

The model includes all of the above, plus aggressor drivers or nets which
affect I/O paths. SIAware optimization must be done in blocks to generate
this model. In the example of tdsp_core above, only placeDesign is done in
block level implementation, so there is no ILM data related to SI.

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Lab 1-3 Specify ILM Model

Objective: Specify ILM data directory for the specified block

In this lab, you will use the ILM data for a block at the top level.

1. restoreDesign for top level.

set dataDir [pwd]/design
cd PTN/dtmf_recvr_core
restoreDesign . dtmf_recvr_core

2. Set –keepFlatten option of setIlmMode to true and flatten the design to reduce number of
flattenIlm and/or unflattenIlm calls during timing closure flow.

setIlmMode –keepFlatten true

3. Use the ILM data for all the blocks.

set ilmNameList {tdsp_core ram_128x16_test ram_256x16_test}
foreach ilmName $ilmNameList {
specifyIlm -cell ${i lmName} -dir ../../PTN/${ilmName}/ilm
}
NOTE: you can unspecify a previously specified ILM using the following command
unspecifyIlm –cell cellName

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Lab 1-4 Update SDC Constraints

Objective: Do final earlyGlobalRoute using partition pins and final timing check

In this lab, you will change the SDC constraint file information for the specified existing constraint
mode object.

1. Run update_constraint_mode to reset all interactive constraints for all the views.

update_constraint_mode -name setup_func \

-ilm_sdc_files $dataDir/mmmc/dtmf_recvr_core_func.sdc
update_constraint_mode -name setup_test \
-ilm_sdc_files $dataDir/mmmc/dtmf_chip_testmode.sdc

* Specified ILM SDC file should be the full chip SDC

* ILM SDC files will be used in the flattened view. Timing result will not be
available if ILM SDC file is not defined
* Top-level SDC will used when ILMs are un-specified

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Lab 1-5 Optimize design

Objective: Optimize timing for the design with ILM involved

In this lab, you will run placeDesign, earlyGlobalRoute and optDesign to optimize timing.

1. Starting from this point the design will be in flattening view UNTIL you explicitly run
unflattenIlm.
flattenIlm

2. Place the design and checks FIXED and PLACED cells for violations, adds violation
markers to the design display area, and generates a violation report.
placeDesign

3. Run checkFPlan to check floorplan and placement of the design before proceeding to next
step in the flow. In V17.1, for a command that cannot handle flattened ILM view,
Innovus can automatically flatten the design, check floorplan, unflatten the design back,
and issue a warning message to inform user what it did. To improve run time, you can
explicitly run unflattenIlm, execute a group of non-timing related commands, and run
unflattenIlm.
checkFPlan –place

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4. Check timing after placement and save the design
earlyGlobalRoute
timeDesign -preCTS
saveDesign DBS/place_route.enc

5. Optimize design, check timing after optimization and save the design

optDesign –preCTS
timeDesign –preCTS
saveDesign DBS/optDesign.enc

6. Report the ILM status in the design,

reportIlmStatus

===============================================================
========
Current design: dtmf_recvr_core
Current view is ILM (after flattenIlm)
Current ILM data is for timing mode.
===============================================================
========

Cell Type Stage Instance Name

---------------------------------------------------------------
--------
ram_128x16_test ILM - RAM_128x16_TEST_INST
ram_256x16_test ILM - RAM_256x16_TEST_INST
tdsp_core ILM - TDSP_CORE_INST

ILM/flexILM Data Location :

---------------------------------------------------------------
--------
tdsp_core : ../../PTN/tdsp_core/ilm
ram_128x16_test : ../../PTN/ram_128x16_test/ilm
ram_256x16_test : ../../PTN/ram_256x16_test/ilm