ELEC 335

Digital Logic Design

by

Dr. Mohammad Shakeel Laghari

Course Coordinator

ELEC 335, Digital Logic Design, UAE University

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 Chapter 7
3 question on the final

Analysis of Sequential Systems

ELEC 335, Digital Logic Design, UAE University

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 Outline
• Flip Flop Characteristics Table
• Input Equations
• State Table
• State Diagram
• Moore Model Circuit
• Mealy Model Circuit
• Sequential Circuit Design
• Sequence Detector
• Design with D and JK Flip Flop
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 Flip Flops Characteristic Table
Inputs Outputs Inputs Outputs
S R Q(t+1) J K Q(t+1)
0 0 Q(t) time 0 0 Q(t) no change

0 1 0 0 1 0
1 0 1 1 0 1
1 1 Not allowed 1 1 Q’(t) invert of that

Input Output Input Output

D Q(t+1) T Q(t+1)
0 0 0 Q(t)
1 1 1 Q’(t)

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 Input Equations
we called combinational for :- combination + Flip Flop
OR - AND - INVERTER - NAND gates = Sequentional Circuit

X JA Q A
Y
CLK

Z K Q A

Clock

JA = X + Y

KA = Y + Z

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 Input Equations

A
D Q A DA = A X
X X A
CLK DB = A’ B
Q A’
Y = B + X’
A’
D Q B
B B
CLK
Q B’
Clock
B
Y
X’
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 Definitions

State table: shows for each input combination

and each state, what the output is and what the
next state is, that is, what is to be stored in
memory after the next clock.
State diagram (or state graph): a graphical
representation of the state table.

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 State Table

• The functional relationship between the inputs,

outputs, and flip-flop states of a sequential circuit
is usually enumerated in a state table
• The state table consists of four columns:
– Present state
– Input
– Next state
– output

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 State Table

Present state Inputs Next state Output

A B X A B Y
0 0 0 0 0 1
0 0 1 0 0 0
0 1 0 0 1 1
0 1 1 0 1 1
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 1

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 1 0 1
0X D Q Z
1Y 1 A
clock CLK
Q

Present state Inputs Next state Output

A XY
0 00
0 01
State Table & 0 10
0 11
Logic Circuit 1 00
1 01
1 10
1 11
A Z
0 0
1 0
1 0
0 0
1 1
0 1
0 1
1 1

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 A State Table & Logic Circuit

Present state Inputs Next state Output

A B X A B Y
0 0 0 0 0 1
0 0 1 0 0 0
0 1 0 0 1 1
0 1 1 0 1 1
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 1
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 State Diagram for two models

• It is a graphical representation of a state table

• Each state is represented by a circle
• Transitions between states are indicated by directed lines
(arrows) connecting the circles
• For Moore model:
– circle includes state information and output information
– Arrows include input information
• For Mealy model:
– Arrows include input and output information
– Circle includes state information

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 A State Table & State Diagram for Moore Model

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 A State Diagram for Mealy Model

1/0

1/0
00 01
0/0
1/1 0/0
0/0
1/0
11 10

0/0

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 Moore Model Circuit

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 ELEC 335, Digital Logic Design, UAE University
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 Moore Model Circuit

ELEC 335, Digital Logic Design, UAE University

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 Mealy Model Circuit

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 Mealy
Model
Circuit

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 Mealy Model Circuit

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 J 1 = q2 x q1 q2 x q1 q2 z J1 K1
0 0 0 0 0 0 0 1
K 1 = x’
0 0 1 0 1 0 0 0
D 2 = x (q1 + q2’)
0 1 0 0 0 0 0 1
0 1 1 1 0 0 1 0
1 0 0 0 0 0 0 1
1 0 1 1 1 0 0 0
1 1 0 0 0 1 0 1
1 1 1 1 1 1 1 0

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 Sequential Circuit Analysis
A
D Q Z

C RQ

D
B
Q

C RQ

D Q
C

Clock CR Q
Reset

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 Flip Flop Input Equations

• Variables
– Inputs: None
– Outputs: Z
– State Variables: A, B, C
• Initialization: Reset to (0,0,0)
• Equations
– A(t+1) = Z=
– B(t+1) =
– C(t+1) =

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 State Table

X’ = X(t+1) ABC A’B’C’ Z

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

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 State Diagram

ABC
Reset 000

111 100 001

011 010 101

110

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 Sequential Circuit Design

1. Obtain either state diagram or the state table from the statement
of the problem
2. If only a state diagram is available from step 1, then obtain the
state table
3. Assign binary codes to the states
4. Derive the flip flop input equations from the next state entries
in the encoded state table
5. Derive output equations from the output entries in the state
table
6. Simplify the flip flop input equations and output equations
7. Draw the logic diagram with D flip flops and combinational
gates, as specified by the flip flop input equations and output
equations

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 Definitions for a Sequence Detector
A system with one input x and one output z such that z = 1 at a clock time
if x is currently 1 and was also 1 at the previous two clock times.
State: what is stored in memory. It is stored in binary devices, but the
information to be stored is not always naturally binary.
Timing trace: a set of values for the input and output (and sometimes
the state or other variables of the system, as well) at consecutive clock
times.

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 State Diagram for a Sequence Detector

• Let’s draw the state diagram for a circuit that recognizes

the occurrence of the sequence of bits 1101 on input X.
• The circuit recognizes the sequence 1101 on X by making
Z equal to 1 when the previous three inputs to the circuit
were 110 and current input is a 1, otherwise, Z is equal to 0
• Keep in mind that each state should remember the history
of previous inputs
• In this case, the circuit must remember that the previous 3
inputs were 110

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 1101 Detection
Sequence Sequence
1st 3rd occurred occurred
clock clock
edge edge
…
X 1 0 0 1 1 0 0 1 1 0 1 1 1 1 0 1 1 0 1
…
2nd 4th
clock clock
Sequence
edge edge
occurred

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 State Diagram (1101 detector)
This state remembers 1 on X
that a single 1 has appeared (sequence
detected)
0 on 1 appeared 1 1 1/1 Output
X on X
0/0 on X on X must
1/0 become 1
1/0 1/0
A B C D
0/0
0/0
0/0
Initial state
(remembers This state
0
nothing) remembers 0 on X X is 0
on we have
that the last 2
X to go back
Inputs were 1’s
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ELEC 335, Digital Logic Design, UAE University to initial state
 Sequential circuit design

• In sequential circuit design, we turn some

description into a working circuit
– We first make a state table or diagram to express the
computation
– Then we can turn that table or diagram into a
sequential circuit

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 Sequential circuit design procedure
Step 1:
Make a state table based on the problem statement. The table should
show the present states, inputs, next states and outputs. (It may be
easier to find a state diagram first, and then convert that to a table)
Step 2:
Assign binary codes to the states in the state table, if you haven’t already. If
you have n states, your binary codes will have at least
élog2 nù digits, and your circuit will have at least élog2 nù flip-flops
Step 3:
For each flip-flop and each row of your state table, find the flip-flop input
values that are needed to generate the next state from the present state. You
can use flip-flop excitation tables here.
Step 4:
Find simplified equations for the flip-flop inputs and the outputs.
Step 5:
Build the circuit!
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 Sequence recognizer (Mealy)
• A sequence recognizer is a special kind of sequential circuit that looks
for a special bit pattern in some input

• The recognizer circuit has only one input, X

– One bit of input is supplied on every clock cycle

– This is an easy way to permit arbitrarily long input sequences

• There is one output, Z, which is 1 when the desired pattern is found

• Our example will detect the bit pattern “1001”:

Inputs: 11100110100100110…
Outputs: 00000100000100100…

• A sequential circuit is required because the circuit has to “remember”

the inputs from previous clock cycles, in order to determine whether
or not a match was found

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 Step 1: Making a state table

• The first thing you have to figure out is precisely how the use of
state
will help you solve the given problem

– Make a state table based on the problem statement. The table

should show the present states, inputs, next states and outputs
– Sometimes it is easier to first find a state diagram and then
convert that to a table

• This is usually the most difficult step. Once you have the state
table,
the rest of the design procedure is the same for all sequential
circuits
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 A basic Mealy state diagram
• What state do we need for the sequence recognizer?
– We have to “remember” inputs from previous clock cycles
– For example, if the previous three inputs were 100 and the current input is
1, then the output should be 1
– In general, we will have to remember occurrences of parts of the desired
pattern—in this case, 1, 10, and 100
• We’ll start with a basic state diagram:

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 Overlapping occurrences of the pattern
• What happens if we’re in state D (the last three inputs were 100), and
the current input is 1?

– The output should be a 1, because we’ve found the desired pattern

– But this last 1 could also be the start of another occurrence of the pattern!
For example, 1001001 contains two occurrences of 1001
– To detect overlapping occurrences of the pattern, the next state
should be B.

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 Filling in the other arrows
• Two outgoing arrows for each node, to account for the possibilities of
X=0 and X=1

• The remaining arrows we need are shown in blue. They also allow for
the correct detection of overlapping occurrences of 1001.

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 Mealy state diagram & table

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 Step 2: Assigning binary codes to states
• We have four states ABCD, so we need at least two flip-flops Q1Q0

• The easiest thing to do is represent state A with Q1Q0 = 00, B with 01, C
with 10, and D with 11

• The state assignment can have a big impact on circuit complexity, but we
won’t worry about that too much in this class

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 Step 3: Finding flip-flop input values
• Next we have to figure out how to actually make the flip-flops change
from their present state into the desired next state
• This depends on what kind of flip-flops you use!
• We’ll use two JKs. For each flip-flip Qi, look at its present and next
states, and determine what the inputs Ji and Ki should be in order to
make that state change.

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 Finding JK flip-flop input values
• For JK flip-flops, this is a little tricky. Recall the characteristic table:

• If the present state of a JK flip-flop is 0 and we want the next state to be 1,

then we have two choices for the JK inputs:
– We can use JK= 10, to explicitly set the flip-flop’s next state to 1
– We can also use JK=11, to complement the current state 0

• So to change from 0 to 1, we must set J=1, but K could be either 0 or 1

• Similarly, the other possible state transitions can all be done in two
different ways as well
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 JK excitation table
• An excitation table shows what flip-flop inputs are required in order to
make a desired state change

• This is the same information that’s given in the characteristic table, but
presented “backwards”

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 Back to the example
• Use the JK excitation table on the right to
find the correct values for each flip-flop’s
inputs, based on its present and next states

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 Step 4: Find equations for the FF inputs and output

• Now you can make K-maps and find equations for each of the four flip-flop
inputs, as well as for the output Z

• These equations are in terms of the present state and the inputs

• The advantage of using JK flip-flops is that there are many don’t care
conditions, which can result in simpler MSP equations

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 FF input equations

J1 = X’ Q0 K1 = X + Q0
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 FF input equations

J0 Q1 Q0 K0 Q1 Q0
00 01 11 10 00 01 11 10
0 0 x x 1 0 x 1 1 x
X X
1 1 x x 1 1 x 0 0 x

J0 = X + Q1 K0 = X’

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 Output equation

Z = X Q1 Q0

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 Step 5: Build the circuit
• Lastly, we use these simplified equations to build the completed circuit

J1 = X’ Q0
K1 = X + Q0

J0 = X + Q1
K0 = X’

Z = Q1 Q0 X

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 Timing diagram
• Here is one example timing diagram for our sequence detector

– The flip-flops Q1Q0 start in the initial state, 00

– On the first three positive clock edges, X is 1, 0, and 0. These inputs cause
Q1Q0 to change, so after the third edge Q1Q0 = 11
– Then when X=1, Z becomes 1 also, meaning that 1001 was found

• The output Z does not have to change at positive clock edges. Instead, it may
change whenever X changes, since Z = Q1Q0X

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 Designing with D and JK Flip Flops

• Keep in mind that we are going to design clocked

sequential circuit (synchronous)
• We will use Mealy model for our designs
However, the method can be used for Moore
model as well
• We can use either D or JK flip flops for the states

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 Design example using D FFs
0/0
Present Input Next Output 1/0 00 1/0
State X State Z 1/1
A B A B 01 1/1 11
0 0 0 0 0 0
0/0 10 0/0
0 0 1 0 1 1
0 1 0 1 0 0 0/0
0 1 1 0 1 0
1 0 0 1 0 0
1 0 1 1 1 1
1 1 0 1 1 0
1 1 1 0 0 0
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 Design Example using D Flip Flops
AB
00 01 11 10
X
Present Input Next Output 1 1 1
0
State State
A B X A B Z 1 1
0 0 0 0 0 0
A=BX+AB
0 0 1 0 1 1
AB
0 1 0 1 0 0 00 01 11 10
X
0 1 1 0 1 0 1
0
1 0 0 1 0 0
1 0 1 1 1 1 1 1 1 1
1 1 0 1 1 0
B=AX+BX+ABX
1 1 1 0 0 0
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 Design Example using D Flip Flops

AB
00 01 11 10
X
0

1 1 1

Z=BX

Now, you can draw the final circuit with clock, set and reset
inputs

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 Designing with JK Flip Flops

• The design of a sequential circuit with flip flops other

than D type is complicated because the flip flop input
equations for the circuit must be derived indirectly from
the state table

• When D type FF’s are employed, the input equations are

obtained directly from the next state. This is not the case
for JK flip flops and other types of flip flops

• In order to determine the input equations for these FF’s, it

is necessary to derive a functional relationship between
the state table and input equations (Excitation table)

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 Excitation Tables
JK Flip Flop SR Flip Flop
Q(t) Q(t+1) J K Q(t) Q(t+1) S R
0 0 0 X 0 0 0 X
0 1 1 X 0 1 1 0
1 0 X 1 1 0 0 1
1 1 X 0 1 1 X 0
D Flip Flop T Flip Flop
Q(t) Q(t+1) D Q(t) Q(t+1) T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0
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 Design Example using JK Flip Flops
Present Input Next Flip Flop Q(t) Q(t+1) J K
state X state inputs
0 0 0 X
A B A B JA KA JB KB
0 1 1 X
0 0 0 0 0 0 X 0 X
1 0 X 1
0 0 1 0 1 0 X 1 X
1 1 X 0
0 1 0 1 0 1 X X 1
0 1 1 0 1 0 X X 0
The output equation is
1 0 0 1 0 X 0 0 X
the same as before
1 0 1 1 1 X 0 1 X
Now you can draw the
1 1 0 1 1 X 0 X 0 final circuit
1 1 1 0 0 X 1 X 1

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 Design Example using JK Flip Flops
AB AB
00 01 11 10 00 01 11 10
X X
0 1 X X 0 X X

1 X X 1 X X 1

JA = BX’ KA = BX

AB AB
00 01 11 10 00 01 11 10
X X
0 X X 0 X 1 X

1 1 X X 1 1 X 1 X

JB = X KB = A’X’ + AX

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 Design Example using JK Flip Flops

X Clock

JA A JB B
> JKFF > JKFF

KA A’ KB B’

JA = BX’ JB = X
KA = BX KB = A’X’ + AX

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