2010 IEEE/ASME International Conference on

Advanced Intelligent Mechatronics

Montréal, Canada, July 6-9, 2010

Using Linear Programming Models for Minimizing

Harmonics Values in Cascaded Multilevel Inverters

M. El-Bakry
Electronics Research Institute, Egypt
E-mail: mahmdali42@yahoo.com

Abstract- Linear programming models are formulated and solved

to determine the switching angles that optimally minimize the
values of the undesired harmonics in cascaded multilevel inverters Vdc
with staircase output voltage waveform. Three cases are discussed.
V1
Case 1 assumes fixed equal values of the input dc voltages. A
mixed integer linear programming (MILP) model is applied. In
case 2 this model is modified to be applied for controllable equal
values of the input dc voltages. In case 3 controllable different
values of the input dc voltages are assumed. In this case a linear Vdc V2 VAB
programming model is formulated, that further minimize the values
of the undesired harmonics. The proposed models for these cases
are solved to minimize the values of the non-tripled odd harmonics
from the 5th till the 31st for 5-level and 7-level cascaded multilevel
inverters and the obtained percentage values of these harmonics Vdc V3
relative to the main harmonic are less than 4.8% and 1.7%
respectively in case 2, and less than 4.8% and 1% respectively in
case 3. 0ther inverter levels are also investigated in cases 2 and 3.
Index Terms- cascaded multilevel inverters, controlling dc
voltages for multilevel inverters, harmonic minimization, linear
programming, MILP, total harmonic distortion. Fig.1 single phase cascaded four-level inverter

I. INTRODUCTION

In recent years multilevel inverters have received more

and more attention because of their capability of high
voltage operation, high efficiency and low electromagnetic
interference, [1]. The desired output of a multilevel inverter
is synthesized by several sources of dc voltages, thus a
nearly sinusoidal output voltage could be obtained. This has
opened a wide variety of applications of multilevel inverters,
in addition to the well known power and industrial
applications [2]-[3], such as for photovoltaic systems [4], for
hybrid electric vehicles [5], for MEMS micro motors [6] and
even for high frequency applications [7].
Cascaded multilevel inverter is one of the most important
topology in the family of multilevel inverters. It can be
supplied from dc sources of different nature and requires
least number of components compared with diode clamped
and flying capacitor type multilevel inverters and no
specially designed output transformer is needed as
compared to multiple pulse inverters [8]. Figure 1 shows, for
example, a single phase cascaded four-level inverter. It
consists of several simple H-bridge inverters fed from
separate dc voltage sources that could be independently
controlled. In addition a staircase output voltage waveform
is preferred, like that shown in Fig.2. It could be produced
by a single on and off switching of each H-inverter per half
cycle of the main harmonic.
Fig.2 A staircase output voltage of a four-level inverter
Since reduction of harmonics is an essential consideration
for multilevel inverters, selective harmonic elimination
methods have been proposed by many references, e.g.[1]-
[9]-[10], in which the zero equations of the undesired
harmonics as function of the switching angles are solved
with the equation of the required value of the main
harmonic to obtain the switching angles. Some references
consider in addition controlling the values of the input dc
voltages, e.g. [11]-[12] However these methods are
more suitable for eliminating small number of harmonics
without regarding the values of the other harmonics.
On the other hand the selective harmonic minimization
method introduced by the author in [13] can minimize the
values of large number of undesired harmonics with

978-1-4244-8030-2/10/$26.00 ©2010 IEEE 696

any desired relative weightings to very low values, that
depend on the level of the inverter. This method is based on
a mixed integer linear programming (MILP) model, which is X2
formulated to obtain the switching angles that minimize the X1 XI XN
values of the undesired harmonics for any desired allowable XN-1
value of the output main harmonic. In this paper this basic
MILP model is first introduced with an added constraint to
satisfy the required staircase output voltage waveform. Three wt
cases are next discussed. Case 1 assumes fixed equal values
of the dc voltage sources, and the model is solved for 5-level 0  2 3 I N
and 7-level inverters. In case 2 the model is modified to
Fig.3. Representation of F(wt) by XI, I= 1, 2, … ,N
consider controllable equal values of the dc voltage sources.
over the interval 0 wt /2
In case 3 different values of the dc voltage sources are
assumed and another linear programming model is
To obtain the values of XI, I=1, 2,. . , N that minimize
formulated to further minimize the undesired harmonics.
some undesired harmonics, a MILP problem is formulated as
Cases 2 and 3 are first investigated for multilevel inverters of
follows, [13]:
different levels, then the results of applying these cases to 5-
level and 7-level cascaded multilevel inverters are given.
Minimize
, subject to the constraints:
1- V'1-  V1  V'1+,
II.THE BASIC MILP MODEL 2- -
m  V2m+1 
m , for each undesired harmonic,
3- XI  L , for I= 1, 2, . . , N,
4- XI 0, and integer, for I=1, 2, . . , N.
The input dc voltages of the multilevel inverter are
assumed to be equal (=Vdc) and fixed. It is assumed,
In addition, the following constraint is added to assure the
without loss of generality, that the multilevel inverter
staircase shape of the output voltage waveform:
generates different voltage levels equally spaced by 1 volt,
5- XI+1 XI for I= 1,2, . . , N-1,
i.e. normalized with respect to Vdc.. It is assumed also that
the inverter output voltage waveform F(wt) is an odd-sines
where :
periodic function, as that shown in Fig. 2. The pattern of this
- V'1 is the required amplitude of the output main harmonic,
function is generated by on and off switching of the inverter
-  is a small incremental value, with  << V'1 , arbitrary
power switches, and is completely determined by defining
chosen and added to the main harmonic constraint to ensure
the switching pattern over the interval 0wt /2. The basic
obtaining an optimum solution, since an equality constrain
approach depends on dividing this interval into N equal
may give a high value of
or even an unfeasible solution,
small subintervals, starting at the angles 0, , 2, . . , (I-1)  ,
- V2m+1 is given by equation (1), for V1 and the undesired
. . and (N-1) ., where  = /2N, Fig.3. We define the
harmonics.
positive integer values XI, I=1, 2, . . , N over each
subinterval, to represent the required instantaneous output - m is a weighting factor for the undesired harmonics, to be
voltage level value F(wt) of the inverter, so that F(wt) is given as desired, to enable reduction of harmonics with
defined over the interval 0wt/2 by: different upper bounds according to their order, and
- L is the number of positive voltage levels of the multilevel
F(wt) = XI for (I-1)   wt  I  and I=1, 2, .., N inverter.
Once all the parameters of this MILP problem are given,
The odd-sines Fourier series expansion of F(wt) is given an optimum solution could be obtained, that will give the
by: values of XI and
, using any of the available operations
m= research software packages, e.g. "LINGO" software [14].
F(wt) = m=0 V2m+1 sin(2m+1)wt , where
In the following this model is applied to cascaded
/2 multilevel inverters of different levels, considering three
V2m+1 = (4/) 0 F(wt) sin(2m+1)wt dwt cases of the input dc voltage sources, equal and fixed, equal
and controllable, and unequal and controllable. In all these
I=N cases the following assumptions are taken:
=(8/(2m+1)) XI sin(2m+1)/2 sin(2m+1)(I+/2) (1) - It is required to minimize equally the non-tripled odd
I=1 harmonics of order 2m+1 = 5, 7, 11, 13,. ., till 31 , i.e. the
where: (2m+1) is the order of the harmonic, harmonics of order 6r ± 1 for r = 1, 2, 3, 4 and 5. We take
m= 0, 1, 2, . . ,, = /2N, and I= (I-1) . m =1 for all these harmonics. The tripled odd harmonics
( 2m+1 = 3, 9, 15, 21, 27) are self cancelled in the output
The value of the amplitude of the main harmonic line voltage assuming a star connected three phase inverter.
corresponds to V1 , i.e. by substituting m=0 in equation (1). The non-tripled odd harmonics are calculated till the 61st
Equation (1) shows that V2m+1, for any value of m, is a harmonic to cover a wide frequency spectrum.
linear function of the integer values XI , I=1, 2, . . , N.
697
- We take the number of subintervals N =180 within the
interval of /2, to assure a suitable accuracy in the obtained
(a)
values of the switching angles, i.e. each subinterval will take
an interval 90˚/180˚ =0.5˚.
6

Value of X(I)
4
III. CASE 1: THE DC VOLTAGE SOURCES ARE OF
EQUAL AND FIXED VALUES 2

0
This case applies directly the MILP formulation given 1 17 33 49 65 81 97 113 129 145 161 177
above. It will be applied next to 5-level and 7-level inverters.
Subinterval (I)
The model is solved for 5-level inverter, i.e. L=4, and for
required output voltage (main harmonic) amplitudes of V'1=
(b)
5, 4, 3 and 2, and  is taken equal 0.1. From the solution
results, the following quantities are recorded in table I :

% Harmonic value
- The amplitude of the output voltage V1. 25
- The value of
. 20
- The maximum percentage amplitude of the undesired 15
harmonics relative to the main harmonic ( %Vh1 ), i.e. from 10
the 5th till the 31st harmonic. 5
- The total harmonic distortion (%THD1) produced by the 0
undesired harmonics, from the 5th till the 31st, defined by : 0 9 18 27 36 45 54 63
m=15 2 0.5 Harmonic order
%THD1 = (  (V2m+1 / V1 ) ) x 100
m=2
Fig. 4 Case 1: 5-level inverter, V1=4.90 a) values of XI
- The maximum percentage amplitude of harmonics
b) % values of harmonics
relative to the main harmonic ( %Vh2 ) from the 5th till the
61st harmonic.
- The total harmonic distortion (%THD2) calculated from
the 5th till the 61st harmonic.
(noting that only the non-tripled odd harmonics are (a)
considered )
4
Value of X(I)

TABLE I 3
SAMPLES OF SOLUTIONS FOR DIFFERENT VOLTAGES
2
(F0R 5-LEVEL INVERTER)
1
V1 4.90 4.10 3.03 1.97 0

0.32 0.23 0.25 0.32 1 17 33 49 65 81 97 113 129 145 161 177
%Vh1 6.54 5.52 8.35 9.50
%THD1 10.80 9.83 14.75 27.17 Subinterval (I)
%Vh2 6.54 5.52 8.35 9.50
%THD2 10.88 10.82 15.53 27.36
(b)
Fig. 4 shows for V1 = 4.90 the obtained values of XI ,
which represent the switching pattern over a quarter cycle of 25
% Harmonic value

the main harmonic (the switching angles are 1=0.5˚, 20

2=2.5˚, 3=20.5˚ and 4=24˚) and the percentage values of 15
the harmonics (V2m+1 *100/V1) till the 61st harmonic 10
relative to 20% of the amplitude of the main harmonic V1. 5
Fig. 5 shows the same for V1 = 3.03 (the switching angles 0
are 1=0.5˚, 2=30˚, 3=58˚ and the fourth level is not -5 0 9 18 27 36 45 54 63
needed). The percentage values of the undesired harmonics
Harmonic order
relative to the main harmonic (%Vh1) are less than 6.6% for
V1 = 4.90 and less than 8.4% for V1 = 3.03.
Table II shows the results obtained when applying the Fig. 5 Case 1: 5-level inverter, V1=3.03 a) values of XI
MILP formulation to a 7-level inverter for the values V'1 = b) % values of harmonics
7.5, 6, 5 and 4 with =0.1.

698
 TABLE II
SAMPLES OF SOLUTIONS FOR DIFFERENT VOLTAGES (a)
(F0R 7-LEVEL INVERTER)

8
V1 7.40 5.94 4.90 4.10

Value of X(I)

0.61 0.14 0.26 0.23 6
%Vh1 8.20 2.40 5.31 5.52 4
%THD1 11.99 3.71 10.03 9.83
%Vh2 8.20 2.40 5.31 5.52
2
%THD2 12.52 4.88 10.43 10.82 0
1 17 33 49 65 81 97 113 129 145 161 177
Fig. 6 shows for V1 = 7.40 the values of XI (the switching Subinterval (I)
angles are 1=0.0˚, 2=1˚, 3=1.5˚, 4=19˚, 5=20.5˚, and
6=21.5˚), and the percentage values of the harmonics (V2m+1
*100/V1) till the 61st harmonic relative to 20% of the (b)
amplitude of the main harmonic V1. Fig. 7 shows the same
for V1 = 4.90 (the switching angles are 1=1˚, 2=2.5˚,

% Harmonic value
25
3=28.5˚, 4=38.5˚, 5=79˚ and the sixth level is not needed).
20
The percentage values of the undesired harmonics relative to
15
the main harmonic (%Vh1) are less than 8.3% for V1 = 7.4
10
and less than 5.4% for V1 = 4.90.
5
Under the above assumptions of the MILP model, the
0
values of the undesired harmonics are equally optimally
0 9 18 27 36 45 54 63
minimized. It is noticed that the percentage value of some
undesired harmonics of low order relative to the main Harmonic order
harmonic exceeds 5%.

It should be noted that the values of V1 in tables I and II Fig. 6 Case 1: 7-level inverter, V1=7.40 a) values of XI
are relative to a unity value of the input Vdc. For any other b) % values of harmonics
value of Vdc , the value of V1 has to calculated
proportionally.

IV. CASE 2: THE DC VOLTAGE SOURCES ARE OF (a)

EQUAL AND CONTROLLABLE VALUES
6
In this case the values of the dc voltage sources are equal
Value of X(I)

and are controlled to give any required value of V'1 while 4

keeping the minimum relative values of the undesired
2
harmonics obtained over the whole possible output voltage
values. 0
The MILP given in section II is modified, to give 1 17 33 49 65 81 97 113 129 145 161 177
minimum
over all possible values of V1 that require
Subinterval (I)
utilizing all the dc voltage levels by replacing the first
constraint on V1 by the constraint :
V1 L
(b)
Table III gives the solutions obtained for multilevel
inverters of 5, 6, 7, 8 and 9 levels, i.e. taking L= 3, 4,. , 8.
For each level the values of V1 ,
, %Vh1 , %THD1, %Vh2 , 25
% Harmonic value

and %THD2 as defined before, in section III, are recorded: 20

15
TABLE III 10
SAMPLES OF SOLUTIONS FOR DIFFERENT LEVELS 5
0
Level 5 6 7 8 9 -5 0 9 18 27 36 45 54 63
V1 4.28 5.94 6.96 8.12 9.32

0.20 0.14 0.11 0.08 0.07 Harmonic order
%Vh1 4.75 2.40 1.60 0.96 0.71
%THD1 7.08 3.71 2.77 2.23 1.70
%Vh2 4.75 2.40 1.60 1.08 1.15 Fig. 7 Case 1: 7-level inverter, V1= 4.90 a) values of XI
%THD2 7.78 4.88 3.54 3.12 2.48 b) % values of harmonics

699
 (a) (a)

5 8

Value of X(I)
Value of X(I)

4 6
3
4
2
2
1
0 0
1 17 33 49 65 81 97 113 129 145 161 177 1 17 33 49 65 81 97 113 129 145 161 177

Subinterval (I) Subinterval (I)

(b) (b)

25 25

% Harmonic value
% Harmonic value

20 20
15 15
10 10
5 5
0 0
-5 0 -5 0 9 18 27 36 45 54 63
9 18 27 36 45 54 63
Harmonic order Harmonic order

Fig. 8 Case 2: 5-level inverter a) values of XI Fig. 9 Case 2: 7-level inverter a) values of XI
b) % values of harmonics b) % values of harmonics

Minimize
, subject to the constraints:
Fig. 8 shows for level 5 the values of XI (the switching 1- V1 = VL
angles are 1=0.0, 2=17.5˚, 3=35.5˚, 4=53.5˚) and the 2- -
m  V2m+1 
m , for each undesired harmonic,
percentage values of the harmonics (V2m+1*100/V1) till the 3- YI  L , for I= 1,2, . . , N
61st harmonic relative to 20% of the amplitude of the main 4- YI+1 YI for I= 1,2, . . , N-1
harmonic V1 . 5- YI 0, for I=1,2, . . ,N
Fig. 9 shows the same for level 7 (the switching angles are where:
1=0.0˚, 2=6˚, 3=13.5˚, 4=23˚, 5=33˚, and 6=42.5˚). - VL is the value of the main harmonic voltage of the level
The percentage values of the undesired harmonics relative to under consideration, as calculated in the previous section
the main harmonic (%Vh1) are less than 4.8% for level 5 and and given in tables III.
less than 1.7% for level 7. - V2m+1 is calculated from equation (1) by substituting YI
It should be noted that the value of V1 in table III is relative instead of XI , and
to a unity value of the input Vdc. For any required value of - the other constraints are similar to the previous MILP
V1 the value of Vdc has to be calculated proportionally . formulation given in section II, except that YI may not take
Since Vdc in this case is controllable, it could be changed to integer values.
the calculated value. For these new values the percentage The solution of this LP will give the values of YI and
.
values of harmonics given in table III remain the same.
Table IV gives the solution results for the levels 5, 6, 7, 8,
V. CASE 3: THE DC VOLTAGE SOURCES ARE OF 9 and for the values calculated as in table III.
DIFFERENT AND CONTROLLABLE VALUES
TABLE IV
To further minimize the harmonics produced by applying SAMPLES OF SOLUTIONS FOR DIFFERENT LEVELS
the MILP formulation given in section II and modified in
Level 5 6 7 8 9
section IV, the solution values of XI obtained from the V1 4.28 5.94 6.96 8.12 9.32
MILP are used to define another set of values YI such that :
0.20 0.11 0.07 0.04 0.05
YI = EXI , where I= 1,. . , N and E0 = 0. %Vh1 4.74 1.91 0.95 0.54 0.50
Since XI take the values 0. 1, 2, . ., L the values of E1, %THD1 6.94 4.15 1.74 1.24 1.23
E2, . . , EL represent the voltage levels. These are the %Vh2 4.74 1.91 1.50 1.07 1.18
%THD2 7.65 5.20 2.87 2.63 2.24
variables that will be obtained by solving the following
linear programming (LP) problem:

700
 Fig. 10 shows for level 5 the obtained values of YI (the
(a)
switching angles are the same as that of Fig. 4 and the dc
voltage levels are: E1 = 0.96, E2 = 2.01, E3 = 2.98 and E4
=4.01, i.e. the values of the dc voltage sources are :0.96, 8

Value of Y(I)
1.05, 0.97 and 1.03) and the percentage values of the 6
harmonics (V2m+1 *100/V1) till the 61st harmonic relative to 4
20% of the amplitude of the main harmonic V1. All the
2
percentage values of the undesired harmonics are less than
4.8%. 0
Fig. 11 shows the same for level 7 (the switching angles are 1 17 33 49 65 81 97 113 129 145 161 177
the same as of Fig. 5 and the dc voltage levels are: E1 = 0.73, Subinterval (I)
E2 = 1.88, E3 =3.17, E4 = 4.31, E5 = 5.30 and E6 = 5.92, i.e.
the value of the dc voltage sources are: 0.73, 1.15, 1.29,
1.14, 1.19 and 0.62). All the percentage values of the (b)
undesired harmonics are less than 1%.
25

% Harmonic value
It should be noted that the values of the dc voltage sources 20
are relative to the value of V1 as given in table IV. For any 15
required value of V1 the values of the dc voltage sources 10
have to be calculated proportionally. For these new values 5
the percentage values of harmonics given in table IV remain 0
the same. -5 0 9 18 27 36 45 54 63
Harmonic order
We notice that as the level of the inverter increases the
deviations of the dc voltage levels from their previous Fig. 11 Case 3: 7-level inverter a) values of YI
integer values increase and this algorithm becomes more b) % values of harmonics
effective for further reduction of the values of the undesired
harmonics.

VI. CONCLUSIONS
(a)

Using linear programming models for cascaded multilevel

5 inverters with staircase output voltage waveform to
Value of Y(I)

4 determine the switching angles that optimally minimize the

3 values of the undesired harmonics has shown the following
2 advantages over the harmonic elimination methods
1 discussed in the literature:
0 1- Very low relative values of a large number of undesired
1 17 33 49 65 81 97 113 129 145 161 177 harmonics, relative to the fundamental voltage, could be
Subinterval (I) obtained, independent of the number of switching angles per
quarter cycle of the output waveform.
2- An exact solution could be almost obtained for any
(b) possible value of the fundamental voltage, since the main
model does not contain any restrict equality constraints.
25 3- It is possible to minimize any number of undesired
% Harmonic value

20 harmonics, with the same upper bound or with any desired

15 relative weightings.
10 4- It is possible to include any additional requirements or
5 constraints on the amplitudes of the fundamental and
0 undesired harmonics.
-5 0 9 18 27 36 45 54 63 5- These models may help in selecting the level of the
Harmonic order required multilevel inverter for any specific application,
since an overview of the optimum harmonic spectrum under
any required conditions could be obtained.
Fig. 10 Case 3: 5-level inverter a) values of YI
b) % values of harmonics

701
 In addition the execution time on a personal computer does
not exceed few seconds for all the cases discussed, which
make the use of these models very practical.
In this paper three cases are considered:
Case 1: assumes that the dc voltage sources are of equal
and fixed values.
Case 2: assumes that the dc voltages sources are of
equal values but their value is controllable.
These cases could be also applied for other types of
multilevel inverters that have a single dc source, such as
diode clamped and flying capacitors multilevel inverters,
and with a staircase output voltage waveform. For other
output voltage waveforms, the same procedure could be
applied after excluding the staircase waveform constraint
(which is given by XI+1
XI for I= 1, 2. . ., N-1). "DC-AC cascaded H-bridge multilevel boast inverter with
Case 3: assumes that the dc voltage sources could have
unequal and controllable values. In this case another linear
programming problem is solved to further minimize the
values of the undesired harmonics. However this case is
more effective for inverters of levels higher than four.
These cases have been explained by examples of 5-level
and 7-level inverters. In these examples the following
assumptions are taken:
- The harmonics to be minimized are the non-tripled odd
harmonics of order 6r ± 1 for r = 1, 2, 3, 4 and 5, and the
harmonics till r = 10 are also calculated.
- The undesired harmonics are required to be equally
minimized by the same amount.
- The number of subintervals considered in the
linear programming formulation is taken N = 180. This
given a precision of 0.5˚in calculating the switching angles.
The obtained maximum percentage amplitudes of the
undesired harmonics relative to the main harmonic differs
greatly from output voltage value to another in case 1,
while it is recorded in table II for case 2 and in table III for
case 3 for inverters of different levels, and drop below 1%
in case III for inverters of 7 levels and higher levels.
The models deduced in this paper could be applied to
optimally minimize the values of any number of harmonics
of any order and with any desired relative weighting of
minimization. When applying them with higher number of
subintervals, i.e. with N > 180, more precision in calculating
the switching angles is achieved and may produce further
reduction in the values of the undesired harmonics, but the
execution time will be expected to increase.
VII. REFERENCES
[1] K. El-Naggar and T. Abdelhamid, "Selective harmonic
elimination of new family of multilevel inverters using
genetic algorithms", Energy Conversion and Management,
Elsevier Ltd., 49, Jan 2008, pp. 89-95.
702
[2] S. Khomfoy, L. M. Tolbert and B. Ozpineci, "Cascaded
H-bridge multilevel inverter drives operating under faulty
conditions with AI-based fault diagnosis and
reconfiguration", IEEE/ASME Advanced Intelligent
Mechatronics Conf., June 2006, pp. 3121-3127.
[3] J. Rodrigues, S. Bernet, J. O. Pontt and S. Kouro,
"Multilevel voltage sources converter topology for
industrial medium voltage drives", IEEE Trans. Industrial
Electronics, Vol.54, No. 6,Dec. 2007, pp. 2930-2945.
[4] E. Ozdemir, S. Ozdemir and L. M. Tolbert,
"Fundamental frequency modulated six-level diode-clamped
multilevel inverter for three-phase stand-alone photovoltaic
system" IEEE Trans. Industrial Electronics, Vol. 56, No. 11,
Nov. 2009, pp. 4409-4415.
[5] Z. Du, B. Ozpineci, L. M. Tolbert and J. N. Chiasson,
no inductors for electric/hybrid vechicle applications", IEEE
Trans. Industry Applications, Vol. 45. Issue 3, May-June
2009, pp. 963-970.
[6] T. C. Neugebauen, D. J. Perreault, J. H. Long and C.
Livermore, "A six-phase multilevel inverter for MEMS
electrostatic induction micrometers", IEEE Trans. Circuits
and Systems- Express briefs, Vol.51, No. 2, Feb. 2004, pp.
49-56.
[7] H. Soltani, J. Adabia and F. Zare, " Effects of switching
time on output voltages of a multilevel inverter used in
high frequency applications´, Australian Journal of Electrical
& Electronic Engineering, Vol. 5, No. 2, 2008, pp. 149-160.
[8] J. Kumar, B. Das and P. Agarwal, "Selective harmonic
elimination technique for a multilevel inverter", ", Proc.
15th National Power Systems Conf., India, Dec. 2008,
pp.608-613.
[9] J. Chiasson, L. Tolbert, K. McKenzie and Z. Du,
"Harmonic elimination in multilevel converters", Proc.
IASTED Power and Energy Systems Conf, 2003, pp. 1-6.
[10] S. Barakati, L. Baghli, E. Berkouk and M. Boucherit,
"Harmonic elimination in diode clamped multilevel inverters
using evolutionary algorithms", Electrical Power Systems
Research, Elsevier Ltd., 78, Oct. 2008, pp. 1736-1746.
[11] S. Krishna, "Harmonic elimination by selection of
switching angles and dc voltages in cascaded multilevel
inverters", Proc. 15th National Power Systems Conf.,
India, Dec. 2008, pp. 119-124.
[12] Y. Lui, H. Hong, and A. Q. Huang, "Real-time
algorithm for minimizing THD in multilevel inverters with
unequal varying voltage steps under staircase modulation",
IEEE Trans. Industrial Electronics, 56(6), 2009, pp. 2249-
2258.
[13] M. El-Bakry, "Selective harmonic minimization for
multilevel inverters", Proc. 2nd Int. Conf. Computer and
Electrical Engineering (ICCEE 2009) , Dubai , UAE, Vol. 2,
Dec. 2009, pp.341-346.
[14] Lindo Systems Inc., "Optimization modeling with
LINGO",2004,www.lindo.co