EE539: Analog Integrated Circuit Design

Opamp-summary

Nagendra Krishnapura

Department of Electrical Engineering

Indian Institute of Technology, Madras
Chennai, 600036, India

26 March 2008

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Differential pair opamp
Vdd
M3 M4
Iref out

inp M1 M2
inn

I0
M0

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Differential pair opamp

Gm gm1
Gout gds1 + gds3
Ao gm1 /(gds1 + gds3 )
Acm gds0 /gm3
Ci Cgs1 /2
ωu gm1 /CL
pk , zk p2 = −gm3 /(Cdb1 + Cdb3 + 2Cgs3 ); z1 = 2p2
Svi 16kT /3gm1 (1 + gm3 /gm1 )
2
σVos 2
σVT 2 2
1 + (gm3 /gm1 ) σVT 3
Vcm ≥ VT 1 + VDSAT 1 + VDSAT 0
≤ Vdd − VDSAT 3 − VT 3 + VT 1
Vout ≥ Vcm − VT 1
≤ Vdd − VDSAT 3
SR ±I0 /CL
Isupply I0 + Iref

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Cascode output resistance

Rout = gmc/gdscgm1 + 1/gdsc + 1/gm1

(negligible)
Rout = 1/gdsc(1+gmc/gm1)
Rout = gmc/gdscGs + 1/Gs + 1/gdsc Rout = gmc/gdscgds1 + 1/gdsc + 1/gds1
Vdd
(negligible)
Vbiasc Vbiasc Vbiasc Vbias1
Mc Mc Mc M1

Gs Vbias1 Gs=gds1 Gs=gm1

M1
differential pair: Mc degenerated
by M1’s source impedance (gm1)

Output resistance looking into one side of the differential

pair is 2/gds1 (gm 1 = gm c in the figure)

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Opamp: dc small signal analysis

Bias values in black

Incremental values in red
Impedances in blue
Total quantity = Bias + increment

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Differential pair: Quiescent condition

M3 M4
Vdd Vdd
M3 M4
Vdd-VGS3 (by symmetry)

I0/2
zero current

I0/2 I0/2 I0/2 I0/2 +

−
Vcm Vcm Vcm Vcm
M1 M2 M1 M2 Vdd-VGS3

Vbias0 Vbias0

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Differential pair: Transconductance

M3 M4
Vdd

gmvd/2
I0/2 gmvd
gmvd/2
gmvd/2
I0/2 I0/2 +
−
Vcm Vcm
M1 M2 Vdd-VGS3
+vd/2 -vd/2

vx ~ 0

Vbias0

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Differential pair: Output conductance

M3 M4
Vdd

vTgds1/2 + vTgds3
I0/2
vTgds1/2
vT(gds1 + gds3)
I0/2 I0/2 vTgds1/2 +
−
Vcm Vcm
M1 M2 Vdd-VGS3
+vT
vTgds1/2

Vbias0

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Telescopic cascode: Quiescent condition
M3 M4
Vdd

I0/2

Vbiasp2
M7 M8

zero current

+
−
M5 M6
Vdd-VGS3
Vbiasn2

I0/2 I0/2

Vcm Vcm
M1 M2

Vbias0

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Telescopic cascode: Transconductance
M3 M4
Vdd

gmvd/2

Vbiasp2
M7 M8 gmvd/2
I0/2
gmvd

gmvd/2 +
gmvd/2 −
M5 M6
Vdd-VGS3
Vbiasn2
gmvd/2
I0/2 I0/2

Vcm Vcm
M1 M2
+vd/2 -vd/2

vx ~ 0

Vbias0

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Telescopic cascode: Output conductance
M3 M4
Vdd

vTgds5gds1/2gm5
I0/2

Vbiasp2
vTgds5gds1/2gm5 + vTgds7gds3/gm7
M7 M8

vTgds5gds1/2gm5+ vT(gds5gds1/gm5 + gds7gds3/gm7)

−
M5 M6 gds5gds1/2gm5
Vdd-VGS3
Vbiasn2 +vT
vTgds5gds1/2gm5 gds1/2
I0/2 I0/2

Vcm Vcm
M1 M2

vTgds5gds1/2gm5

Vbias0

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Folded cascode: Quiescent condition

M9 M10
Vdd
I0/2+I1 I0/2+I1
Vbiasp1

M5 M6
Vbiasp2
I1 I1

zero current
I0/2 I0/2
+
Vcm
M1 M2
Vcm M7 M8 −
Vbiasn2 VGS3

Vbias0 I1 I1

M3 M4

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Folded cascode: Transconductance

M9 M10
Vdd
I0/2+I1 I0/2+I1
Vbiasp1

M5 M6
gmvd/2
gmvd/2
Vbiasp2
I1 I1
gmvd/2 gmvd/2
gmvd
I0/2 I0/2
gmvd/2 +
Vcm
M1 M2
Vcm M7 M8 −
+vd/2 -vd/2 Vbiasn2 VGS3

vx ~ 0

gmvd/2 gmvd/2
Vbias0 I1 I1

M3 M4

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Folded cascode: Output conductance

M9 M10
Vdd
I0/2+I1 I0/2+I1
Vbiasp1
vTgds5gds1/2gm5

vTgds5gds1/2gm5

M5 M6
Vbiasp2
I1 I1 vTgds5(gds1/2+gds9)/gm5

gds1/2 zero current

I0/2 I0/2
+ vT(gds5(gds1+gds9)/gm5 + gds7gds3/gm7)
Vcm
M1 M2
Vcm M7 M8 −
Vbiasn2 VGS3
+vT

vTgds5gds1/2gm5
Vbias0 I1 I1 vTgds5gds1/2gm5 + vTgds7gds3/gm7

M3 M4

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Differential pair: Noise
in0/2+in1/2-in2/2+in3 in0/2+in1/2-in2/2+in3

in3
in4
in1-in2+in3-in4

in0/2+in1/2-in2/2
in1 in2 in0/2-in1/2+in2/2 +
− Vdd-VGS3

Vcm Vcm

in0/2+in1/2-in2/2 in0/2-in1/2+in2/2
in0
in0

Carry out small signal linear analysis with one noise

source at a time
Add up the results at the output (current in this case)
Add up corresponding spectral densities
Divide by gain squared to get input referred noise
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Telescopic cascode opamp
M3 M4
Vdd

Vbiasp2
M7 M8

out

M5 M6
Vbiasn2

inp inn
M1 M2

Vbias0

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Telescopic cascode opamp
Gm gm1
Gout gds1 gds5 /gm5 + gds3 gds7 /gm7
Ao gm1 /(gds1 gds5 /gm5 + gds3 gds7 /gm7 )
Acm gds0 /gm3
Ci Cgs1 /2
ωu gm1 /CL
pk , zk p2 = −gm3 /(Cdb1 + Cdb3 + 2Cgs3 )
p3 = −gm5 /Cp5
p4 = −gm7 /Cp7
p2,4 appear for one half and cause mirrror zeros
Svi 16kT /3gm1 (1 + gm3 /gm1 )
2
σVos 2
σVT 2 2
1 + (gm3 /gm1 ) σVT 3
Vout ≥ Vbiasn1 − VT 5
≤ Vbiasp1 + VT 7
SR ±I0 /CL
Isupply I0 + Iref

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Folded cascode opamp
M9 M10
Vdd

Vbiasp1

M5 M6
Vbiasp2

out
inp inn M7 M8
M1 M2
Vbiasn2

Vbias0

M3 M4

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Folded cascode opamp
Gm gm1
Gout (gds1 + gds9 )gds5 /gm5 + gds3 gds7 /gm7
Ao gm1 /((gds1 + gds9 )gds5 /gm5 + gds3 gds7 /gm7 )
Acm gds0 /gm3
Ci Cgs1 /2
ωu gm1 /CL
pk , zk p2 = −gm3 /(Cdb1 + Cdb3 + 2Cgs3 )
p3 = −gm5 /Cp5
p4 = −gm7 /Cp7
p2,4 appear for one half and cause mirrror zeros
Svi 16kT /3gm1 (1 + gm3 /gm1 + gm9 /gm1 )
2
σVos 2
σVT 2 2 2 2
1 + (gm3 /gm1 ) σVT 3 + (gm9 /gm1 ) σVT 9
Vout ≥ Vbiasn1 − VT 5
≤ Vbiasp1 + VT 7
SR ± min{I0 , I1 }/CL
Isupply I0 + I1 + Iref

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Body effect

All nMOS bulk terminals to ground

All pMOS bulk terminals to Vdd
Acm has an additional factor gm1 /(gm1 + gmb1 )
gm5 + gmb5 instead of gm5 in cascode opamp results
gm7 + gmb7 instead of gm7 in cascode opamp results

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Two stage opamp

bias stage 1 stage 2

Vdd
M3 M4
Iref
M11

RL
Rc
Voutbias
inn M1 M2
inp
Cc
CL
I0
M0 M12

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Two stage opamp
gm1 Vdd
inp −
inn M11
+
single stage
opamp
out

Rc Cc

I1

First stage can be Differential pair, Telescopic cascode, or

Folded cascode; Ideal gm1 assumed in the analysis
Second stage: Common source amplifier
Frequency response is the product of frequency responses
of the first stage gm and a common source amplifier driven
from a current source
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Common source amplifier: Frequency response

 
Vo (s) gm 1 gm 11 sCc (Rc − 1/gm 11 ) + 1
=
Vd (s) G1 GL a3 s 3 + a 2 s 2 + a 1 s + 1
Rc C1 CL Cc
a3 =
G1 GL
C1 Cc + Cc CL + CL C1 + Rc Cc (G1 CL + C1 GL )
a2 =
G1 GL
Cc (gm 11 + G1 + GL + G1 GL Rc ) + C1 GL + G1 CL
a1 =
G1 GL

G1 : Total conductive load at the input

GL : Total conductive load at the output
C1 : Total capacitive load at the input
CL : Total capacitive load at the output
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Common source amplifier: Poles and zeros

G1
p1 ≈ − gm 11 G1
Cc (GL + 1 + + G1 Rc ) + C1 (1 + G
GL GL )
1

+CL
gm 11 C1C+C
c
c
+ GL + G1 CC1c+C C
+ G1GL Rc C1C+C c
c
p2 ≈ − C1 Cc Rc Cc (G1 CL +GL C1 )
C1 +Cc + CL + Cc +CL
   
11 1 1 G1 GL
p3 ≈ − + + + +
Rc
CL Cc C1 C1 CL
1
z1 =
(1/gm 11 − Rc )Cc

Unity gain frequency

gm 1
ωu ≈    
GL G1 G1 GL Rc
Cc 1 + gm 11 + gm 11 + gm 11 + C1 gGmL + gGm1
11 11

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Common source amplifier: Frequency response

Pole splitting using compensation capacitor Cc

p1 moves to a lower frequency
p2 moves to a higher frequency (For large Cc ,
p2 = gm 11 /CL )
Zero cancelling resistor Rc moves z1 towards the left half s
plane and results in a third pole p3
z1 can be moved to ∞ with Rc = 1/gm 11
z1 can be moved to cancel p2 with Rc > 1/gm 11 (needs to
be verified against process variations)
Third pole p3 at a high frequency
Poles and zeros from the first stage will appear in the
frequency response—Ym1 (s) instead of gm 1 in Vo /Vi
above
Mirror pole and zero
Poles due to cascode amplifiers

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Two stage opamp

Ao gm1 gm11 /(gds1 + gds3 )(gds11 + gds12 )

Acm gds0 gm11 /gm3 (gds11 + gds12 )
Ci Cgs1 /2
ωu gm1 /Cc
pk , zk See previous pages
Svi ≈ 16kT /3gm1 (1 + gm3 /gm1 )
2
σVos ≈ σVT2 2 2
1 + (gm3 /gm1 ) σVT 3
Vcm ≥ VT 1 + VDSAT 1 + VDSAT 0
≤ Vdd − VDSAT 3 − VT 3 + VT 1
Vout ≥ VDSAT 12
≤ Vdd − VDSAT 11
SR+ I0 /Cc
SR- min{I0 /Cc , I1 /(CL + Cc )}
Isupply I0 + I1 + Iref

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Fully differential circuits: Noise

M3 M4 M3
in3 in4 in3
CMFB
vn,half
- +
vn,full

Vcm Vcm
M1 M2 M1
in1 in2 in1

half circuit(small signal)

M0
Sn,full = 2Sn,half

Calculate noise spectral density of the half circuit

Multiply by 2×

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Fully differential circuits: Offset

Vdd

M3 M4 M3

−
+
+

+
−

−
∆VT3 ∆VT4 ∆VT3
voff,half
voff,full
- +
∆VT1 ∆VT2 ∆VT1
Vcm Vcm

−
+
+

+
−

−
M1 M2 M1

half circuit(small signal)

M0

v2off,full = 2v2off,half

Calculate mean squared offset of the half circuit

Multiply by 2× if mismatch (e.g. ∆VT ) wrt ideal device is
used

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Fully differential circuits: Offset

Vdd

M3 M4 M3

+
−

−
∆VT34 ∆VT34
voff,half
voff,full
- +
∆VT12 ∆VT12
Vcm Vcm
+

+
−

−
M1 M2 M1

half circuit(small signal)

M0

v2off,full = v2off,half

Calculate mean squared offset of the half circuit

Multiply by 1× if mismatch between two real devices is
used

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Opamp comparison

Differential Telescopic Folded Two

pair cascode cascode stage
Gain − ++ + ++
Noise = = high =
Offset = = high =
Swing − − + ++
Speed ++ + − +

Nagendra Krishnapura EE539: Analog Integrated Circuit Design

Differential pair
Vdd
M3 M4
Iref out

inp M1 M2
inn

I0
M0

Low accuracy (low gain) applications

Voltage follower (capacitive load)
Voltage follower with source follower (resistive load)
In bias stabilization loops (effectively two stages in
feedback)
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Telescopic cascode
M3 M4
Vdd

Vbiasp2
M7 M8

out

M5 M6
Vbiasn2

inp inn
M1 M2

Vbias0

Low swing circuits

Switched capacitor circuits
Capacitive load
Different input and output common mode voltages
First stage of a two stage opamp
Only way to get high gain in fine line processes
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Folded cascode
M9 M10
Vdd

Vbiasp1

M5 M6
Vbiasp2

out

inp inn M7 M8
M1 M2
Vbiasn2

Vbias0

M3 M4

Higher swing circuits

Higher noise and offset
Lower speed than telescopic cascode
Low frequency pole at the drain of the input pair
Switched capacitor circuits (Capacitive load)
First stage of a two stage class AB opamp
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Two stage opamp
bias stage 1 stage 2
Vdd
M3 M4
Iref
M11

RL
Rc
Voutbias
inn M1 M2
inp
Cc
CL
I0
M0 M12

Highest possible swing

Resistive loads
Capacitive loads at high speed
“Standard” opamp: Miller compensated two stage opamp
Class AB opamp: Always two (or more) stages
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Opamps: pMOS versus nMOS input stage

nMOS input stage

Higher gm for the same current
Suitable for large bandwidths
Higher flicker noise (usually)
pMOS input stage
Lower gm for the same current
Lower flicker noise (usually)
Suitable for low noise low frequency applications

Nagendra Krishnapura EE539: Analog Integrated Circuit Design