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Chapter 9 1 ComputerBasics Datapath
Chapter 9 1 ComputerBasics Datapath
Chapter 9 – Computer
Design Basics
Part 1 – Datapaths
Chapter 9 Part 1 2
Introduction
Computer Specification
• Instruction Set Architecture (ISA) - the
specification of a computer's appearance to a
programmer at its lowest level
• Computer Architecture - a high-level
description of the hardware implementing
the computer derived from the ISA
• The architecture usually includes additional
specifications such as speed, cost, and
reliability.
Chapter 9 Part 1 3
Introduction (continued)
registers L oad
R0 2 2
Two mux-based n n
L oad
register selectors R1
0
n 1
Register destination n
0
2
3
M UX
decoder L oad
R2
1
2
M UX
3
Mux B for external n n
constant input 0 1 2 3
L oad R3
n n
n
Register file
Buses A and B with external D ecoder
2
D address
n
A data
n
B data
Constant in
address and data outputs Destination select
M B select
n 1 0
MU X B A ddress
ALU and Shifter with BusA n
n out
Bus B
Data
A B n out
Mux F for output select G select
4 A B
H select
2
S
B
S2:0 || Cin
M D select 0 1
MU X D
n Bus D
Chapter 9 Part 1 6
Datapath Example: Performing a
Microoperation
L oad enable A select B select
Microoperation: R0 ← R1 + R2 Write
D data n
A address B address
A B
B
H select
n
B
out
4 2
Apply 1 to Load Enable to force the V
S2:0 || Cin
A rithmetic/logic 0
S
IR Shifter IL 0
unit (A L U )
Load input to R0 to 1 so that R0 is C
N
G
n
H
n
loaded on the clock pulse (not shown) Z Z ero D etect
M F select
0 1
Function unit
MUX F
The overall microoperation requires F
n n D ata in
to MB select n 1
2
M UX
n
0 3
Provide an address and data for a L oad
R2
1
2
MUX
n
n
1 0
data for a memory or output read M B select
BusA
M UX B
n A ddress
out
microoperation – apply 1 to MD Bus B n
Data
A B n out
G select H select
select V
4 A
S2:0 || Cin
A rithmetic/logic
B
0
2
S
IR
B
Shifter IL 0
cares F
n n D ata in
MD select 0 1
MUX D
Bus D
n
Chapter 9 Part 1 8
Arithmetic Logic Unit (ALU)
Chapter 9 Part 1 9
Arithmetic Circuit Design (continued)
There are only four functions of B to select as Y in G = A + Y:
Cin = 0 Cin = 1
• 0 G=A G=A+ 1
• B G=A+ B G=A+ B + 1
• B G=A+ B G=A+ B + 1
• 1 G=A– 1 G=A
What functions are implemented with carry-in to the adder = 0?
C
=1? in
n
A X
n n-bit n
B parallel G X Y Cin
adder
B input n
Y
S0 logic
S1
Cout
Chapter 9 Part 1 10
Arithmetic Circuit Design (continued)
S1 S0 Y Cin =0 Cin =1
Chapter 9 Part 1 11
Logic Circuit
Chapter 9 Part 1 13
Arithmetic Logic Unit (ALU) (continued)
C0 5 Cin
Ci Ci Ci 1 1
Ai Ai
One stage of
Bi Bi arithmetic
circuit 2-to-1
S0 S0
0 M UX
S1 S1
Gi
1
Ai S
B i One stage of
Cin S logic circuit
0
S1
S2
The next most significant select signals, S0 for the arithmetic circuit and
S1 for the logic circuit, are wired together, completing the two select
signals for the logic circuit.
The remaining S1 completes the three select signals for the arithmetic
circuit.
Chapter 9 Part 1 14
Combinational Shifter Parameters
Direction: Left, Right
Number of positions with examples:
• Single bit:
1 position
0 and 1 positions
• Multiple bit:
1 to n – 1 positions
0 to n – 1 positions
Filling of vacant positions
• Many options depending on instruction set
• Here, will provide input lines or zero fill
Chapter 9 Part 1 15
4-Bit Basic Left/Right Shifter
B3 B2 B1 B0
Serial
output L
Serial
output R
IR IL
0 1 2 M 0 1 2 M 0 1 2M 0 1 2M
S U S U S U S U
X X X X
2
S
H3 H2 H1 H0
Serial Inputs: Shift Functions:
• IR for right shift (S1, S0) = 00 Pass B unchanged
• IL for left shift 01 Right shift
Serial Outputs 10 Left shift
• R for right shift (Same as MSB input) 11 Unused
• L for left shift (Same as LSB input)
Chapter 9 Part 1 16
Barrel Shifter
D3 D2 D1 D0
S0
S1
3 2 1 0 S1 S0 3 2 1 0 S1 S0 3 2 1 0 S1 S0 3 2 1 0 S1 S0
M M M M
U U U U
X X X X
Y3 Y2 Y1 Y0
A rotate is a shift in which the bits shifted out are inserted into the
positions vacated
The circuit rotates its contents left from 0 to 3 positions depending on S:
S = 00 position unchanged S = 10 rotate left by 2 positions
S = 01 rotate left by 1 positions S = 11 rotate left by 3 positions
See Table 10-3 in text for details
Chapter 9 Part 1 17
Barrel Shifter (continued)
Chapter 9 Part 1 18
Datapath Representation
Have looked at detailed design of n
function unit V
C Function
The remaining muxes and buses N
unit
MD select 0 1
MUX D
Chapter 9 Part 1 19
Datapath Representation (continued)
In the register file: n
MD select 0 1
MUX D
Chapter 9 Part 1 20
Definition of Function
G Select, H Select, and MF Unit Select (FS) Codes
in T of FS Codes
MF G H
FS(3:0) Select Select(3:0) Select(3:0) Microoperation
Chapter 9 Part 1 21
The Control Word
Chapter 9 Part 1 22
The Control Word Fields
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DA AA BA M FS MR
B D W
Control word
Fields
• DA – D Address
• AA – A Address
• BA – B Address
• MB – Mux B
• FS – Function Select
• MD – Mux D
• RW – Register Write
The connections to datapath are shown in the next slide
Chapter 9 Part 1 23
Control Word Block Diagram
n
RW 0 Write D data
15
DA 14 D address
13 8x n
Register file
12 9
AA 11 A address B address 8 BA
10 7
A data B data
n n
n
Constant in
1 0
MB 6 MUX B
Bus A n
Address out
Bus B n
Data out
A B
V 5
C Function 4 FS
N unit 3
Z 2
n
n Data in
0 1
MD 1 MUX D
Bus D
Chapter 9 Part 1 24
Control Word Encoding
Encoding of ControlW
DA, AA, BA MB FS MD RW
Function Code Function Code Function Code Function Code Function Code
Chapter 9 Part 1 25
Microoperations for the Datapath -
Symbolic Representation
Micro-
operation DA AA BA MB FS MD RW
Chapter 9 Part 1 26
Microoperations for the Datapath -
Binary
m Representation
Microoperations from T
a Binary Co o
Micro-
operation DA AA BA MB FS MD RW
Chapter 9 Part 1 27
Datapath Simulation
Clock 1 2 3 4 5 6 7 8
DA 1 4 7 1 0 4 5
AA 2 0 7 0
BA 3 6 0 3 0
FS 5 14 1 2 0 10
Constant_in X 2 X
MB
A ddress_out 2 0 7 0
D ata_out 3 6 0 2 3 0
D ata_in 18 18
MD
RW
reg0 0
reg1 1 255 2
reg2 2
reg3 3
reg4 4 12 18
reg5 5 0
reg6 6
reg7 7 8
Status_bits 2 0 0 1 X
Chapter 9 Part 1 28