SC2332B Device Specification - V1.2

w
r
Fo
l
ia
d
nt
rl
e
o
id
rw
f
te
on
wa
r
Fo
al
SC2332B Device Specification
ti
en
id
nf
Co
ld
or
oc
rw
is
te
Un
wa
r
Fo
l
t ia
en
www.unisoc.com
id
nf
Co
t
c
wa
o
is
UNISOC TECHNOLOGIES INC., Confidential and Proprietary

r
Un
Fo
l
ia
nt
de
fi
on
w
r
Fo
l
ia
d
Disclaimer
nt
rl
e
o
id
rw
All data and information contained in or disclosed by this document is confidential and
f
te
on
proprietary information of UNISOC and all rights therein are expressly reserved. This document is
wa
provided for reference purpose, no license (express or implied, by estoppel or otherwise) to any
intellectual property rights is granted by this document, and no express and implied warranties,
r
including but without limitation, the implied warranties of fitness for any particular purpose, and
Fo
non-infringement, as well as any performance. By accepting this material, the recipient agrees that
the material and the information contained therein is to be held in confidence and in trust and will
al
not be used, copied, reproduced in whole or in part, nor its contents revealed in any manner to
ti
others without the express written permission of UNISOC. UNISOC may make any changes at any
time without prior notice. Although every reasonable effort is made to present current and accurate
en
information, UNISOC makes no guarantees of any kind with respect to the matters addressed in this
id
document. In no event shall UNISOC be responsible or liable, directly or indirectly, for any damage or
nf
loss caused or alleged to be caused by or in connection with the use of or reliance on any such
Co
content.
ld
Please refer to the UNISOC Documents in the UNISOC Deliverables for the use of the
or
oc
Deliverables. Any loss caused by the modification, customization or use of the UNISOC Deliverables
rw
is
in violation of the instructions in the UNISOC Documents shall be undertaken by those who conduct
te
Un
so. The performance indicators, test results and parameters in the UNISOC Deliverables are all
obtained in the internal development and test system of UNISOC and are only for the reference.
wa
Before using UNISOC Deliverables commercially or conducting mass production of the Deliverables,
comprehensive testing and debugging in combination with its own software and hardware test
r
Fo
environment are pre-requisite.

l
t ia
en
id
nf
Co
t
c
wa
o
is
r
Un
Fo
l
ia
nt
de
fi
UNISOC TECHNOLOGIES INC., Confidential and Proprietary 2 of 43

on
w
r
Fo
l
Revision History
ia
d
Version Date Note
nt
rl
e
1.0 2019/09/09 First release
o
id
rw
1.1 2019/10/16 Update the Disclaimer and logo
f
te
on
1.2 2019/10/23 Delete invalid information
wa
r
Fo
al
ti
en
id
nf
Co
ld
or
oc
rw
is
te
Un
wa
r
Fo
l
t ia
en
id
nf
Co
t
c
wa
o
is
r
Un
Fo
l
ia
nt
de
fi

on
w
r
Fo
l
Contents
ia
d
1 SYSTEM OVERVIEW ................................................................................................................... 7
nt
rl
1.1 Overview ............................................................................................................................ 7
e
o
1.2 Features ............................................................................................................................. 7
id
rw
1.2.1 General Features .......................................................................................... 7
f
te
1.2.2 WiFi Features ................................................................................................ 7
on
1.2.3 Bluetooth Features ........................................................................................ 7
wa
1.2.4 FM Features .................................................................................................. 8
1.2.5 Power management ...................................................................................... 8
r
Fo
2 PACKAGE INFORMATION ......................................................................................................... 9
2.1 Device Pinout ..................................................................................................................... 9
2.2 Package Outline ............................................................................................................... 10
3 al
PIN INFORMATION ................................................................................................................... 13
ti
3.1 Pin symbol descriptions.................................................................................................... 13
en
3.2 Pin List .............................................................................................................................. 13

3.3 Pin Multiplexed Function List ........................................................................................... 21
id
3.4 Control Registers for BT/WiFi/FM .................................................................................... 23

nf
3.4.1 Pin_reg Memory map .................................................................................. 23

Co
3.4.2 Register Description .................................................................................... 24
ld
4 ELECTRICAL SPECIFICATION ................................................................................................ 26
or
oc
4.1 Absolute Maximum Ratings ............................................................................................. 26

4.2 rw
Recommended Operating Range .................................................................................... 26
is
4.3 Power On Sequence ........................................................................................................ 27

te
Un
4.4 Leakage Current ............................................................................................................... 27

wa
5 RF SUBSYSTEM ........................................................................................................................ 28
5.1 System overview .............................................................................................................. 28
r
5.1.1 Functional block diagram ............................................................................ 28

Fo
5.2 Features ........................................................................................................................... 30

5.2.1 WiFi/BT ........................................................................................................ 30
l
5.2.2 FM ............................................................................................................... 30
ia
5.3 RF Specification ............................................................................................................... 30

t
5.3.1 WiFi / BT Specification ................................................................................ 30

en
5.3.2 FM Receiver Specification ........................................................................... 37

id
6 IO INTERFACE TIMING SPECIFICATION ................................................................................ 39

nf
6.1 SDIO Interface Timing ...................................................................................................... 39

6.1.1 SDIO Bus Timing ......................................................................................... 39
Co
6.2 IIS/PCM Interface Timing ................................................................................................. 41

6.2.1 IIS/PCM Interface Timing ............................................................................ 41
t
c
6.2.2 Setup time and hold time ............................................................................. 42

wa
o
is
6.3 UART Interface Timing ..................................................................................................... 42

r
Un
Fo
l
ia
nt
de
fi

on
w
r
Fo
l
List of Figures
ia
d
Figure 2-1 Device Pinout ................................................................................................................... 9
nt
rl
Figure 2-2 Package Outline (Top view) ........................................................................................... 10
e
Figure 2-3 Package Outline （Detail:“A”） ................................................................................... 10
o
id
rw
Figure 2-4 Package Outline (Bottom view) ...................................................................................... 11
f
Figure 2-5 Package Outline (Dimension) ........................................................................................ 12
te
on
Figure 4-1 Power-on sequence ....................................................................................................... 27
wa
Figure 5-1 SC2332B RF block diagram ........................................................................................... 28
Figure 6-1 SDIO Bus Timing (Default) ............................................................................................. 39
r
Figure 6-2 SDIO Bus Timing (High Speed) ..................................................................................... 40
Fo
Figure 6-3 Sampling data at falling edge of IISCLK ........................................................................ 41
Figure 6-4 Sampling data at rising edge of IISCLK ......................................................................... 41
Figure 6-5 al
Implementation of sampling data at falling edge of IISCLK ........................................... 42
ti
Figure 6-6 Implementation of sampling data at rising edge of IISCLK ............................................ 42
Figure 6-7 Implementation of sampling data at falling edge of IISCLK ........................................... 42
en
Figure 6-8 UART Interface Timing (Default) .................................................................................... 43

id
nf
Co
ld
or
oc
rw
is
te
Un
wa
r
Fo
l
t ia
en
id
nf
Co
t
c
wa
o
is
r
Un
Fo
l
ia
nt
de
fi

on
w
r
Fo
l
List of Tables
ia
d
Table 3-1 Definition of pin symbols ................................................................................................ 13
nt
rl
Table 3-2 Pin List description ......................................................................................................... 13
e
Table 3-3 Pin Multiplexed Function list ........................................................................................... 21
o
id
rw
Table 3-5 Pin_reg Memory map ..................................................................................................... 23
f
Table 3-6 Pin control register0 ....................................................................................................... 24
te
on
Table 3-7 SD interface pin control register ..................................................................................... 24
wa
Table 3-8 Other pin bit control ........................................................................................................ 24
Table 4-1 Absolute maximum ratings ............................................................................................. 26
r
Table 4-2 Recommended operating range ..................................................................................... 26
Fo
Table 4-3 Deep sleep leakage current summary ........................................................................... 27
Table 5-1 WiFi Receiver Specification............................................................................................ 31
Table 5-2 al
WiFi Transmitter Specification ....................................................................................... 32
ti
Table 5-3 Bluetooth BDR receiver performance ............................................................................ 33
Table 5-4 Bluetooth BDR transmitter performance ........................................................................ 34
en
Table 5-5 Bluetooth EDR Receiver Specification ........................................................................... 34

id
Table 5-6 Bluetooth EDR Transmitter Specification ....................................................................... 35

Table 5-7 Bluetooth LE Receiver Specification .............................................................................. 36
nf
Table 5-8 Bluetooth LE Transmitter Specification .......................................................................... 37

Co
Table 5-9 FM Receiver Specification.............................................................................................. 37
ld
Table 6-1 Bus Timing – Parameter Values (Default) ...................................................................... 39
or
oc
Table 6-2 Bus Timing – Parameter Values (High Speed) .............................................................. 40

Table 6-3
rw
Bus Timing – Parameter Values (Default) ...................................................................... 43
is
te
Un
wa
r
Fo
l
t ia
en
id
nf
Co
t
c
wa
o
is
r
Un
Fo
l
ia
nt
de
fi

on
w
r
Fo
l
ia
1 System Overview
d
nt
rl
e
1.1 Overview
o
id
rw
f
SC2332B is a chip that includes the WiFi/BT/FM baseband core and their RF. It’s the highest level of
te
on
integration for a mobile system with integrated 802.11 b/g and single stream 802.11n, Bluetooth4.2,
Smart ready mode and an FM radio receiver. It also includes on-chip 2.4GHz CMOS power amplifiers,
wa
LNA and RF TR switch.
SC2332B supports SDIO 2.0 for both WIFI and Bluetooth/FM host interface.
r
SC2332B implements SPRD Gen2 WIFI/BT/LTE Coexistence algorithms for smooth user experience.
Fo
SC2332B adopts the most advanced LP 40nm process to reduce active and idle power, and it can
satisfy the mobile devices which require minimal power consumption and compact PCB size.
al
ti
1.2 Features
en
1.2.1 General Features

id
 175Ball BGA package (7.5mm x 5.3mm, 0.4mm pitch)

nf
 Share 26M clock with SPRD chipset

Co
ld
1.2.2 WiFi Features
or

oc
Single-band 2.4 GHz single stream IEEE 802.11b/g/n


rw
is
Support WIFI and Bluetooth TDD operation and single-antenna topology with integrated
te
TR-switch.
Un
 Integrated DPD technology to reduce power consumption.

wa
 Integrated power detector to support TX power control

r
 Build-in calibration for PVT variation

Fo
 Security:
o WEP,WPA-TKIP, AES, WPA2, WAPI
l
ia
o WPS2.0, EAP-sim, Hotspot2.0

t
o Support 802.11w - Secure Management Frames

en
 Support 802.11k - Resource Management

id
 Support WIFI P2P mode

nf
 Support STA&P2P concurrency in same channel

Co
 Low power mode

o ARP offload, auto response in sleep mode
t
c
o
wa
DTIM Lower power mode

o
is
 WIFI/BT/LTE co-existence
r
Un
Fo
1.2.3 Bluetooth Features

 Bluetooth specification v2.1 + EDR
l
 Bluetooth v4.2 Low Energy (LE)

ia
 Bluetooth v2.1 and BLE dual mode concurrent, Bluetooth Smart Ready compliant
nt
de
fi

on
w
r
Fo
l
ia  Integrated on-chip PA for TX, maximum power >10dBm (class 1)
 Supports extended synchronous connections (eSCO) for enhanced voice quality
d
nt
rl
1.2.4 FM Features
e
o
id
rw
Supporting frequency range of 65MHz ~ 108MHz

f
Support RDS/RBDS
te
on
 Digital stereo modulator/demodulator
wa
 Digital audio interface (I2S)

r
Stereo Mono blending and auto selectivity
Fo
1.2.5 Power management

al
The input voltage of 1.6V for RF & Analog internal LDOs
ti
 External 3.3V for the internal PA

en
External power supply 1.8V I/O

 Input voltage of 1.2~1.6V for internal digital core LDO
id
 WiFi power domain for power saving

nf
Co
ld
or
oc
rw
is
te
Un
wa
r
Fo
l
t ia
en
id
nf
Co
t
c
wa
o
is
r
Un
Fo
l
ia
nt
de
fi

on
w
r
Fo
l
ia
2 Package Information
d
nt
rl
e
o
2.1 Device Pinout
id
rw
f
te
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
on
CHIP_E SD_CM DVDD11

A NC NC NC NC XTLEN IISDO SD_CLK VDDIO SD_D0 NC A
N D _CORE
wa
OSC_26 DVDD12
B NC NC NC NC NC NC NC IISDI IISCLK VSS VSS SD_D1 SD_D2 SD_D3 B
M _CORE
r
C NC NC VSS NC NC NC NC VSS IISLRCK VSS VSS VSS VSS U0CTS C
Fo
AVDD13
D NC VSS VSS VSS NC NC VSS VSS VSS VSS VSS VSS U0RTS U1TXD D
_AFE
al
AVDD16
E NC NC VSS VSS VSS VSS NC VSS VSS VSS VSS VSS U0RXD U0TXD E
_AFE
WCI_2_
ti
F NC NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS MTCK F
RXD
AVDD16 WCI_2_
en
G NC NC VSS VSS NC _TRX_IS VSS VSS VSS VSS VSS VSS VSS G
TXD
M
RF_ISM
id
H NC VSS VSS VSS NC NC VSS VSS VSS VSS VSS VSS VSS GPIO0 MTMS H
_N
nf
J NC VSS NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS GPIO2 RST_N J
Co
K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS GPIO1 K
ld
AVDD33 FM_SAN CLK_32
L VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS INT L
_PA T K
or
oc
RF_ISM FM_LAN AVDD16

M NC VSS NC VSS NC VSS NC VSS VSS PTEST NC M
_P rw T _FM
is
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
te
Un
Analog
Power Digital CLK GND NC
and RF
wa
Figure 2-1 Device Pinout

r
Fo
l
t ia
en
id
nf
Co
t
c
wa
o
is
r
Un
Fo
l
ia
nt
de
fi

on
w
r
Fo
l
2.2
ia Package Outline
d
nt
rl
e
o
id
rw
f
te
on
wa
r
Fo
al
ti
en
id
nf
Co
ld
Figure 2-2 Package Outline (Top view)
or
oc
rw
is
te
Un
wa
r
Fo
l
t ia
en
id
nf
Co
t
c
wa
o
is
r
Un
Fo
Figure 2-3 Package Outline （Detail:“A”）

l
ia
nt
de
fi

on
w
r
Fo
l
ia
d
nt
rl
e
o
id
rw
f
te
on
wa
r
Fo
al
ti
en
id
nf
Co
ld
Figure 2-4 Package Outline (Bottom view)
or
oc
rw
is
te
Un
wa
r
Fo
l
t ia
en
id
nf
Co
t
c
wa
o
is
r
Un
Fo
l
ia
nt
de
fi

on
w
r
Fo
l
ia
d
nt
rl
e
o
id
rw
f
te
on
wa
r
Fo
al
ti
en
id
nf
Co
ld
or
oc
rw
is
te
Un
wa
r
Fo
l
Figure 2-5 Package Outline (Dimension)

t ia
en
id
nf
Co
t
c
wa
o
is
r
Un
Fo
l
ia
nt
de
fi

on
w
r
Fo
l
ia
3 Pin Information
d
nt
rl
e
o
3.1 Pin symbol descriptions
id
rw
f
te
The following table explains the symbols used in the pin lists.
on
wa
Table 3-1 Definition of pin symbols
Field Symbol Type Description
r
Fo
I Digital input
O Digital output
O/T
al
Digital output with tri-state option
ti
I/O Digital bi-directional pin
I/O/T Digital bi-directional pin with tri-state option
en
Pin PI Power pin, input from external power supply

id
Power pin, input from external or floating to use internal LDO power
PIO
nf
Type supply
PO Power pin, output for external devices
Co
ld
G Ground pin
or
oc
AI Analog input pin

AO Analog output pin
rw
is
AIO Analog bi-directional pin

te
Un
IPU Input with pull-up

wa
IPD Input with pull-down

Pin
OH Output “1”
r
Value
OL Output “0”
Fo
Z Tri-state
l
ia
3.2 Pin List

t
en
Table 3-2 Pin List description

Pin Pull up Pull Descriptio
id
Pow Drive At
No. Pin Name dow After Reset n
nf
er Strength Reset
n
Co
JTAG
H1 VDDI 1.8V,120K 120 ie=1, oe=0, ARM JTAG
MTMS
t
c
2/6/12/24 TMS
wa
8 O /9K K wpu
o
is
F1 VDDI 1.8V,120K 120 ie=1, oe=0, ARM JTAG

MTCK
r
Un
2/6/12/24 TCK
Fo
8 O /9K K wpdo
B2 NC
l
C2 NC
ia
A2 NC
nt
de
fi

on
w
r
Fo
l
B1 NC
ia
WCI-2
d
nt
rl
WCI-2
e
Coexisten
o
F1 VDDI 1.8V,120K 120 ie=1, oe=0,
id
rw
WCI_2_RXD 2/6/12/24 ce
7 O /9K K wpu
f
interface
te
on
RX
wa
WCI-2
Coexisten
r
G1 VDDI 1.8V,120K 120
WCI_2_TXD 2/6/12/24 ie=0, oe=1,1 ce
Fo
7 O /9K K
interface
TX
GPIO al
ti
H1 VDDI 1.8V,120K 120 2/6/12/24 ie=1, oe=0,
GPIO0 GPIO0
en
7 O /9K K wpu
id
K1 VDDI 1.8V,120K 120 2/6/12/24 ie=1, oe=0,

GPIO1 GPIO1
7 O /9K K wpu
nf
VDDI 1.8V,120K 120 2/6/12/24 ie=1, oe=0,

J17 GPIO2 GPIO2
Co
O /9K K wpu
ld
F1 NC
or
oc
C1 NC rw
is
Clock
te
32KHz
Un
VDDI 1.8V,120K 120 clock

L18 CLK_32K
wa
2/6/12/24 ie=1, oe=0

O /9K K input
r
D2 NC
Fo
26MHz
B9 OSC_26M clock
l
ia
input
D7 NC
t
en
System
id
2/6/12/24 External
VDDI 1.8V,120K 120 ie=1, oe=0, reset
nf
J18 RST_N
O /9K K wpu input,
Co
Active low
2/6/12/24 Crystal
t
VDDI 1.8V,120K 120

c
A9 XTLEN ie=0, oe=1, 0 enable

wa
o
O /9K K
is
control
E2 NC
r
Un
Fo
K1 NC
Productio
M1 VDDI 1.8V,120K 120 ie=1, oe=0,
l
PTEST 2/6/12/24 n test

ia
7 O /9K K wpdo
mode
nt
de
fi

on
w
r
Fo
l
E1
ia NC
H7 NC
d
nt
rl
VDDI 1.8V,120K 120 Chip
A3 CHIP_EN 2/6/12/24 ie=0,oe=0
e
O /9K K enable
o
id
rw
B5 NC
f
Interrupt
te
VDDI 1.8V,120K 120
on
L17 INT 2/6/12/24 ie=0, oe=1, 0 output to
wa
O /9K K
AP
IIS
r
VDDI 2/6/12/24 ie=0, oe=1, 0 IIS port
Fo
A1 1.8V,120K 120
IISDO O data
0 /9K K
output
VDDI al 2/6/12/24 ie=0, oe=1, 0
ti
B1 1.8V,120K 120 IIS port bit
IISCLK O
1 /9K K clock
en
VDDI 2/6/12/24 ie=0, oe=1, 1 IIS port

id
C1 1.8V,120K 120
IISLRCK O Left/Right
1 /9K K
nf
clock
Co
B1 VDDI 1.8V,120K 120 2/6/12/24 IIS port
ld
0 IISDI O ie=1, oe=0 data input
/9K K
or
oc
UART rw
is
E1 VDDI 1.8V,120K 120 2/6/12/24 UART

te
Un
U0TXD O
8 /9K K ie=0, oe=1, 1 port0 TX
wa
E1 VDDI 1.8V,120K 120 2/6/12/24 UART

U0RXD ie=1, oe=0,
O
r
7 /9K K wpu port0 RX

Fo
D1 VDDI 1.8V,120K 120 2/6/12/24 UART

U0RTS O
l
7 /9K K ie=0, oe=1, 1 port0 RTS

ia
C1 VDDI 1.8V,120K 120 2/6/12/24 UART

t
U0CTS ie=1, oe=0,

O
en
7 /9K K wpu port0 CTS

id
D1 VDDI 1.8V,120K 120 2/6/12/24 UART

U1TXD O ie=0, oe=1, 1
nf
8 /9K K port1 TX
Co
B3 NC
t
c
C4 NC
wa
o
is
SDIO
r
Un
B1 VDDI 2/6/12/24 ie=1, oe=0, SDIO port

Fo
SD_D3 O 1.8V,60K 60K

7 wpu data 3
l
B1 VDDI 2/6/12/24 ie=1, oe=0, SDIO port

ia
SD_D2 O 1.8V,60K 60K

6 wpu data 2
nt
de
fi

on
w
r
Fo
l
B1
ia VDDI 2/6/12/24 ie=1, oe=0, SDIO port
SD_D1 O 1.8V,60K 60K
d
5 wpu data 1
nt
rl
A1 VDDI 2/6/12/24 ie=1, oe=0, SDIO port
e
o
SD_D0 O 1.8V,60K 60K
id
rw
5 wpu data 0
f
te
A1 VDDI 2/6/12/24 ie=1, oe=0, SDIO port
on
SD_CMD O 1.8V,60K 60K
wa
3 wpu command
A1 VDDI 2/6/12/24 SDIO port
r
SD_CLK O 1.8V,60K 60K ie=1,oe=0
Fo
2 clock
SPI
G3 NC al
ti
J1 NC
en
id
F2 NC
nf
G2 NC
Co
ld
RF
FM short
or
oc
L14 FM_SANT
rw antenna
is
M1 FM long
FM_LANT
te
Un
4 antenna
wa
BT/WIFI
M1
RF_ISM_P RF input
0
r
positive
Fo
BT/WIFI
H9 RF_ISM_N RF input
l
negative
ia
J4 NC
t
M6 NC
en
M8 NC
id
M4 NC
nf
TSEN
Co
B7 NC
C7 NC
t
c
B6 NC
wa
o
Power
is
Power
r
Un
A1
Fo
VDDIO supply for

4
digital IO
l
B4 NC
ia
H1 NC
nt
B1 DVDD12_COR Power
de
fi

on
w
r
Fo
l
8
ia E supply
input for
d
nt
rl
internal
digital
e
o
id
rw
core LDO
A6 NC
f
te
on
Power
M1
wa
AVDD16_FM supply for
5
FM
r
Power
Fo
supply for
analog
E9 AVDD16_AFE al front
ti
end(ADC/
en
PLL)
E7 NC
id
Power
nf
AVDD16_TRX supply for

G8
Co
_ISM TRX and
ld
VCO
or
oc
H6 NC rw
is
Power
te
supply for
Un
L12 AVDD33_PA
BT/WIFI
wa
PA
Digital
r
Fo
A1 DVDD11_COR core cap

7 E LDO 1.1V
l
output
ia
A5 NC
t
ADC and
en
PLL cap
id
D9 AVDD13_AFE 1.3V cap

LDO
nf
output
Co
G7 NC
NC
t
c
wa
o
A1 NC NC
is
A1
NC NC
r
Un
8
Fo
C5 NC NC
D6 NC NC
l
ia
M1 NC NC
M1 NC NC
nt
de
fi

on
w
r
Fo
l
8
ia
Ground
d
nt
rl
GND for
C6 VSS_TSEN
e
TSEN
o
id
rw
B1
VSS GND
f
te
on
B1
wa
VSS GND
4
C3 VSS GND
r
C1
Fo
VSS GND
0
C1
2
VSS al GND
ti
C1
VSS GND
en
4
id
C1
VSS GND
5
nf
C1
Co
VSS GND
ld
6
D3 VSS GND
or
oc
D4 VSS rw GND
is
D5 VSS GND
te
Un
D1
VSS GND
0
wa
D1
VSS GND
1
r
Fo
D1
VSS GND
2
l
D1
ia
VSS GND
3
t
D1
en
VSS GND
4
id
D1
VSS GND
nf
6
E3 VSS GND
Co
E4 VSS GND
t
E5 VSS GND
c
wa
o
E6 VSS GND
is
E8 VSS GND
r
Un
E1
Fo
VSS GND
0
E1
l
VSS GND
ia
2
nt
E1 VSS GND
de
fi

on
w
r
Fo
l
4
ia
E1
d
VSS GND
nt
rl
6
e
F3 VSS GND
o
id
rw
F4 VSS GND
f
F5 VSS GND
te
on
F6 VSS GND
wa
F8 VSS GND
F9 VSS GND
r
Fo
F1
VSS GND
0
F1
1
VSS al GND
ti
F1
VSS GND
en
2
id
F1
VSS GND
3
nf
F1
Co
VSS GND
ld
5
G4 VSS GND
or
oc
G5 VSS rw GND
is
G9 VSS GND
te
Un
G1
VSS GND
0
wa
G1
VSS GND
r
1
Fo
G1
VSS GND
2
l
G1
ia
VSS GND
3
t
G1
en
VSS GND
4
id
G1
VSS GND
nf
6
H2 VSS GND
Co
H3 VSS GND
t
c
H5 VSS GND
wa
o
H1
is
VSS GND
0
r
Un
H1
Fo
VSS GND
1
H1
l
VSS GND
ia
2
nt
H1 VSS GND
de
fi

on
w
r
Fo
l
3
ia
H1
d
VSS GND
nt
rl
4
e
H1
o
VSS GND
id
rw
5
f
H1
te
VSS GND
on
wa
J3 VSS GND
J5 VSS GND
r
J7 VSS GND
Fo
J8 VSS GND
J9
J10
VSS
VSS
al GND
GND
ti
J11 VSS GND
en
J12 VSS GND

id
J13 VSS GND

J15 VSS GND
nf
J16 VSS GND

Co
ld
K5 VSS GND
K6 VSS GND
or
oc
K8 VSS rw GND
is
K1
VSS GND
te
Un
0
wa
K1
VSS GND
1
r
K1
VSS GND
Fo
2
K1
l
VSS GND
3
ia
K1
t
VSS GND
4
en
K1
id
VSS GND
6
nf
L1 VSS GND
Co
L2 VSS GND
L4 VSS GND
t
c
L5 VSS GND
wa
o
L6 VSS GND
is
L7 VSS GND
r
Un
Fo
L8 VSS GND
L9 VSS GND
l
L10 VSS GND

ia
L11 VSS GND

nt
L13 VSS GND

de
fi

on
w
r
Fo
l
L15
ia VSS GND
L16 VSS GND
d
nt
rl
M2 VSS GND
e
M5 VSS GND
o
id
rw
M7 VSS GND
f
M9 VSS GND
te
on
M1
wa
VSS GND
1
r
3.3 Pin Multiplexed Function List
Fo
SC2332B adopts programmable pin multiplexing to reduce pin number as well as providing enough
al
flexibility. Multiple signals are connected to a multiplexer that connects to the same I/O pin showed in
the following two tables.
ti
en
Table 3-3 Pin Multiplexed Function list

id
PIN Functio Ty Functi Ty Functi Ty Functi Ty Functi Ty Functi Ty

nf
Name n1 pe on2 pe on3 pe on4 pe on5 pe on6 pe

O GPIO1 I/O
Co
ld
XTLEN XTLEN 7 /T
or
O/ O/ I/O
oc
GPIO1 DB0(G
IISDO IISDO T T I/O /T rw O WB8 O
6 0)
is
IIS1DO COEX3
te
I/O I/O I/O

Un
GPIO1 DB1(G
IISCLK IISCLK /T IIS1CK /T I/O /T O WB9 O
wa
COEX4 5 0)
I/O I/O I/O
r
/T IIS1LR /T I/O GPIO1 /T DB2(G O WB5( O

Fo
IISLRCK IISLRCK CK COEX5 4 0) G1)

I/O
l
I I/O GPIO1 /T DB3(G O WB6( O

ia
IISDI IISDI COEX6 3 0) G1)

t
I
en
PTEST PTEST
I/O
id
DB4(G
/T I/O O WB0 O
0)
nf
GPIO0 GPIO0 COEX2

Co
I/O DB5(G
/T O WB1 O
GPIO1 GPIO1 0)
t
c
wa
o
I/O DB6(G
is
/T 0) O O
GPIO2 GPIO2 WB2
r
Un
Fo
I/O
CLK_32 CLK_32 GPIO1
I /T
K K 8
l
ia
RST_N RST_N I
nt
de
fi

on
w
r
Fo
l
ia I/O
WCI_2_ WCI_2_ I GPIO3 DB2(G
I/O /T O O
d
RXD RXD COEX0 1) WB3
nt
rl
WCI_2_ WCI_2_ I/O
e
o
U1RX GPIO4 DB7(G
I I/O /T O O
id
rw
TXD TXD D COEX1 0) WB4
f
te
I/O
on
O GPIO6
I/O /T
wa
INT INT COEX7
GPIO2 I/O
I/O
r
MTMS MTMS /T DB0(G O WB5( O
Fo
0 1) G0)
GPIO1 I/O
MTCK MTCK I
al 9 /T
DB1(G
1)
O
WB6(
G0)
O
ti
I/O
en
GPIO2
O /T
U0TXD U0TXD 5
id
I/O
nf
I GPIO2 /T
U0RXD U0RXD 4
Co
ld
I/O
GPIO2
or
O /T
oc
U0RTS U0RTS 3 rw
is
I/O
GPIO2
te
Un
I /T
U0CTS U0CTS 2
wa
I/O
GPIO2 WB7
O /T O
r
U1TXD U1TXD 1
Fo
I/O GPIO1 I/O

/T /T DB3(G O
2
l
SD_D3 SD_D3 1)
ia
I/O I/O
t
/T GPIO1 /T DB4(G O
en
SD_D2 SD_D2 1 1)
id
I/O I/O
/T GPIO1 /T DB5(G O
nf
SD_D1 SD_D1 0 1)
Co
I/O I/O
/T GPIO9 /T DB6(G O
SD_D0 SD_D0 1)
t
c
wa
o
I/O I/O
is
/T GPIO7 /T
SD_CLK SD_CLK
r
Un
Fo
I/O I/O
SD_CM SD_CM GPIO8 DB7(G
/T /T O
D D 1)
l
ia
CHIP_E CHIP_E I
nt
de
fi

on
w
r
Fo
l
N
ia N
d
nt
rl
3.4 Control Registers for BT/WiFi/FM
e
o
id
rw
3.4.1 Pin_reg Memory map
f
te
on
Base address: 0x4000_0000
wa
Table 3-4 Pin_reg Memory map
r
Fo
Offset Address Pin Name Default Value after Reset
0x00 PIN_CTRL_reg0 32'h0
0x04
0x08
al
PIN_CTRL_reg1
PIN_CTRL_reg2
32'h0
32'h0
ti
0x0C PIN_CTRL_reg3 32'h0
en
0x10 XTLEN 32’h4000

id
0x14 IISDO 32’h4000

nf
0x18 IISCLK 32’h4000

0x1C IISLRCK 32’h4000
Co
ld
0x20 IISDI 32’h4000
or
0x24 PTEST 32’h4000
oc
0x28 GPIO0 32’h4000

rw
is
0x2C GPIO1 32’h4000

te
Un
0x30 GPIO2 32’h4000

wa
0x34 CLK_32K 32’h4000

0x38 RST_N 32’h4100
r
0x3C WCI_2_RXD 32’h4100

Fo
0x40 WCI_2_TXD 32’h4000

0x44 INT 32’h4000
l
ia
0x48 MTMS 32’h410a

0x4C MTCK 32’h4006
t
en
0x50 U0TXD 32’h4000

0x54 U0RXD 32’h4100
id
0x58 U0RTS 32’h4000

nf
0x5C U0CTS 32’h4100

Co
0x60 U1TXD 32’h4000

0x64 SD_D3 32’hC10A
t
c
0x68 SD_D2 32’hC100

wa
o
is
0x6C SD_D1 32’hC100

0x70 SD_D0 32’hC100
r
Un
Fo
0x74 SD_CMD 32’hC100

0x78 SD_CLK 32’hC000
l
ia
nt
de
fi

on
w
r
Fo
l
3.4.2
ia Register Description
In the following tables, “PIN_NAME” represents each pin. Function 1, 2, 3, 4, 5, and 6 of each pin is
d
nt
rl
detailed in Table 3-3 Pin Multiplexed Function list.
e
o
3.4.2.1 PIN_CTRL_REG0～3
id
rw
Description：Pin control register0～3
f
te
on
Table 3-5 Pin control register0
wa
Field Name Bit Type Reset Value Description
r
Fo
NULL [31:0] R/W 32’h0 Wait to be used
3.4.2.2
al
SD interface pin control register
ti
SD_D0~SD_D3, SD_CMD, SD_CLK pin control.
en
Table 3-6 SD interface pin control register

id
Field Name Bit Type Reset Description

nf
Value
Co
ld
Reserved [31:16] RO 16’h0 Reserved
or
PIN_NAME_bsr_drv [15:14] R/W Driver Strength select
oc

rw
is
PIN_NAME_fun_wpu [8] R/W Weakly pull up for function mode

te
Un
PIN_NAME_fun_wpdo [7] R/W Weakly pull down for function

wa
mode
PIN_NAME_fun_sel [6:4] R/W Function select
r
PIN_NAME_slp_wpu [3] R/W Weak pull up for chip deep sleep

Fo
mode
PIN_NAME_slp_wpdo [2] R/W Weak pull down for chip deep
l
ia
sleep mode
PIN_NAME_slp_ie [1] R/W Input enable for chip deep sleep
t
en
mode
PIN_NAME_slp_oe [0] R/W Output enable for chip deep sleep
id
mode
nf
Co
3.4.2.3 Other Pin Control Register

t
c
Description：Other Pin control register share the same bit format shown as below.
wa
o
The default value of each control bit is detailed in Table 3-4 Pin_reg Memory map.
is
r
Un
Table 3-7 Other pin bit control

Fo
Field Name Bit Type Reset Description

Value
l
ia

PIN_NAME_bsr_drv [15:14] R/W Driver Strength select
nt
de
fi

on
w
r
Fo
l
Reserved
ia [13] RO 1’h0 Reserved
PIN_NAME_bsr_wpus [12] R/W
d
nt
rl
PIN_NAME_bsr_se [11] R/W
e
o
id
rw
PIN_NAME_fun_wpu [8] R/W Weakly pull up for function mode
f
PIN_NAME_fun_wpdo [7] R/W Weakly pull down for function
te
on
mode
wa
PIN_NAME_fun_sel [6:4] R/W Function select
PIN_NAME_slp_wpu [3] R/W Weak pull up for chip deep sleep
r
Fo
mode
PIN_NAME_slp_wpdo [2] R/W Weak pull down for chip deep
PIN_NAME_slp_ie [1]
al
R/W
sleep mode
Input enable for chip deep sleep
ti
mode
en
PIN_NAME_slp_oe [0] R/W Output enable for chip deep sleep

id
mode
nf
Co
ld
or
oc
rw
is
te
Un
wa
r
Fo
l
t ia
en
id
nf
Co
t
c
wa
o
is
r
Un
Fo
l
ia
nt
de
fi

on
w
r
Fo
l
ia
4 Electrical Specification
d
nt
rl
4.1 Absolute Maximum Ratings
e
o
id
rw
Table 4-1 Absolute maximum ratings
f
te
on
wa
Symbol Parameter Rating Unit
AVDD16_AFE 1.6V supply for analog front end -0.3 to 1.8 V
(ADC/DAC/PLL)
r
Fo
AVDD16_TRX_ISM 1.6V supply for WiFi/BT RF -0.3 to 1.8 V
AVDD16_FM 1.6V supply for FM RF -0.3 to 1.8 V
DVDD12_CORE 1.2V supply for WiFi/BT/FM digital core -0.3 to 1.8 V
VDDIO al
1.8V supply for IO -0.3 to 2.5 V
ti
AVDD33_PA WiFi/BT 3.3V supply for PA and Tx -0.3 to 3.6 V
modulator
en
ESD (HBM) Human body model 1500 V

id
ESD (CDM) Charged-device model 350 V

nf
ESD (MM) Machine model 100 V

Co
ld
or
oc
rw
is
4.2 Recommended Operating Range

te
Un
Table 4-2 Recommended operating range

wa
Symbol Parameter Min. Typ. Max. Unit

r
AVDD16_AFE 1.6V supply for analog front end V

Fo
1.45 1.6 1.65

(ADC/DAC/PLL)
AVDD16_TRX_ISM 1.6V supply for WiFi/BT RF 1.45 1.6 1.65 V
l
AVDD16_FM 1.6V supply for FM RF 1.45 1.6 1.65 V

ia
DVDD12_CORE 1.2V supply for WiFi/BT/FM digital core 1.2 1.6 1.65 V
t
VDDIO 1.8V supply for IO 1.7 1.8 1.9 V

en
AVDD33_PA WiFi/BT 3.3V supply for PA and Tx 3.2 3.3 3.4 V

modulator
id
Tj Junction temperature -10 +25 +115 °C

nf
TSTG Storage temperature -60 +25 +150 °C

TA Ambient operating temperature -40 +25 +85 °C
Co
Device operating temperature -30 +25 +85 °C

TC
t
c
-30 +25 +85 °C

wa
o
Fuse programming temperature

is
r
Un
Fo
l
ia
nt
de
fi

on
w
r
Fo
l
4.3
ia Power On Sequence
d
nt
rl
VDDIO
≥0uS
e
o
id
rw
DVDD12_CORE
f
te
≥0uS
on
wa
CHIP_EN
≤300uS
r
Fo
DVDD11_CORE
≥50uS
al
≥0uS
ti
RST_N
en
Figure 4-1 Power-on sequence

id
nf
4.4 Leakage Current

Co
ld
Table 4-3 Deep sleep leakage current summary
or
oc
rw
is
Symbol Parameter Min. Typ. Max. Unit

te
Un
AVDD16_AFE 1.6V supply for analog front end uA

0
(ADC/DAC/PLL)
wa
AVDD16_TRX_ISM 1.6V supply for WiFi/BT RF 0 uA

r
AVDD16_FM 1.6V supply for FM RF 0 uA

Fo
DVDD12_CORE 1.2V supply for WiFi/BT/FM digital core TBD uA

VDDIO 1.8V supply for IO TBD uA
l
AVDD33_PA WiFi/BT 3.3V supply for PA and Tx 0 uA

ia
modulator
t
en
id
nf
Co
t
c
wa
o
is
r
Un
Fo
l
ia
nt
de
fi

on
w
r
Fo
l
ia
d
5 RF Subsystem
nt
rl
e
o
id
5.1 System overview
rw
f
te
on
5.1.1 Functional block diagram
wa
The RF system block diagram is shown in Figure 5-1. SC2332B is a 3-in-1 wireless connectivity chip.
It includes a WiFi/Bluetooth/FM SOC. The SIP solution consists of a WiFi/Bluetooth (ISM-band)
r
transceiver, an FM receiver, local-oscillation (LO) generators, PLLs, and LDOs.
Fo
al
ti
en
id
nf
Co
ld
or
oc
rw
is
te
Un
wa
r
Fo
l
t ia
en
Figure 5-1 SC2332B RF block diagram

id
5.1.1.1 LDOs
nf
A low-power bandgap reference provides reference voltage and biasing currents for all the internal
Co
LDOs. An always-on LDO is responsible for providing an internal 1.1V voltage to digital circuits from
an external supply of 1.6V. In sleep mode, the BG and LDO consume only a small amount of
quiescent current in several tens of uA. There are several high-PSRR cap/cap-less LDOs on chip to
t
c
wa
provide internal supplies for RF and analog circuits.

o
is
5.1.1.2 Reference Clock and BBPLL

r
Un
Fo
The 26MHz clock is used for RF synthesizer and base-band PLL as reference, and it needs to satisfy
the following specifications
l
ia
 Frequency stability ±0.5ppm


nt
Output voltage >0.6 Vpp and <1.6Vpp

de
fi

on
w
r
Fo
l
ia  Phase noise: <-50dBc/Hz of @ 1-Hz offset, <-77dBc/Hz of @ 10-Hz offset, <-142dBc/Hz @
100-kHz offset.
d

nt
Short-term stability: <4ppb/s
rl
 Duty cycle: No requirement
e
o
id
rw
The base-band PLL provides low-jitter clocks for ADC/DAC and multiple reference clocks for digital
f
core of all radios and CPU.
te
on
32K clock is also adopted in this system for digital part, and it need to satisfy the following
wa
specifications:
r
Frequency stability: 20ppm @25degree
Fo
 Output voltage: PP Min: 0.4VDDIO, PP Typical: 0.7VDDIO, PP Max: VDDIO+0.5V.
 Rising/falling time: No requirement
 Jitter: <10000 ppm


al
Short-term stability: No requirement
ti
Duty cycle: 35%-65%
en
5.1.1.3 WiFi/Bluetooth transceiver

id
WiFi/Bluetooth transceiver supports ISM 2.4GHz-band operation and is a high performance and
highly-integrated RF transceiver which is fully compliant with IEEE 802.11 b/g/n and Bluetooth
nf
v2.1+EDR/ v4.2 LE standards. A unified RF front-end architecture embedding RF T/R switch is

implemented to achieve the maximum hardware usage between WiFi and Bluetooth while achieving
Co
ld
WiFi/Bluetooth concurrent operations. It also features self calibration scheme to compensate the
process and temperature variation to maintain high performance. Calibrations are performed
or
oc
automatically right after the system boot-up.

rw
is
5.1.1.3.1 WiFi / BT Tx
te
Un
The ISM-band transmitting path is designed under the concept of maximally sharing WiFi and
wa
Bluetooth circuitry to achieve minimum area while achieving high performance. Either WiFi or
Bluetooth data is digitally modulated in the baseband processor, and then up-converted to 2.4GHz RF
channels through single-path of DA converter, filter, and IQ up-converter. Due to distinct power
r
Fo
requirements, the only parts that cannot be shared in the transmitting path are WiFi power amplifier
(WPA) and Bluetooth PA (BTPA).
l
5.1.1.3.2 WiFi/BT Rx
t ia
The ISM-band receiving path is also designed in single path. For WiFi operation, the receiver is
en
configured into a direct down-conversion receiver with appropriate gain and bandwidth settings for
decent WiFi operation in terms of interference and blocking condition for sufficient demodulating
id
signal-to-noise ratio. The receiver consists of a gain-programmable LNA, quadrature passive mixer
and gain/bandwidth-programmable low-pass filter. For Bluetooth operation, it is then configured into
nf
low-IF mode with reduced bandwidth for power saving. Fast AGC scheme is used for overcoming
interference conditions within the dynamic range of the receiver ADC.
Co
5.1.1.3.3 WiFi/BT Sx
t
c
wa
o
A single fractional-N frequency synthesizer is implemented for supporting both WiFi and Bluetooth LO
is
signal. The reconfigurable synthesizer is designed to meet both WiFi and Bluetooth LO requirements
r
Un
by appropriate settings under various operations. In WiFi mode, the synthesizer is configured to meet
Fo
phase noise requirements and in Bluetooth mode, the synthesizer is configured to low-power
operation for BT requirements. Fast turn-around time is specially addressed in the design to ensure
smooth WiFi/Bluetooth switching for high throughput.
l
ia
nt
de
fi

on
w
r
Fo
l
5.1.1.4
ia FM receiver
FM radio subsystem integrates complete receiver supporting 65-108 MHz bands with configurable
d
nt
（50 KHz~200KHz）tuning step. The FM radio subsystem supports long antenna, which is usually in
rl
the earphone on the mobile device, and short antenna, which is usually a FPC short antenna or
e
o
shared antenna with GSM.
id
rw
5.1.1.5 Calibrations
f
te
on
The chip also features a full set of self-calibrating mechanisms to compensate the process and
wa
temperature variations and therefore maintains high operating performance. The calibrations include
DC calibration, R-C calibration, automatically-frequency calibration, DC-offset calibration, I/Q-
imbalance calibration, LO-leakage calibration, TX power calibration and digital pre-distortion.
r
Fo
5.2 Features
5.2.1 WiFi/BT al
ti
en
WLAN
id
 Single-band (2.4GHz) single stream 802.11 b/g/n MAC/BB/RF

nf
 Support WiFi and Bluetooth TDD operation and single-antenna topology with integrated TR-
switch
Co
 Integrated PA with max 21 dBm CCK output power
ld
 Typical RX sensitivity: -77.8dBm at 802.11g 54Mbps mode
or

oc
Integrated power detector to support real-time TX power calibration

 Built-in calibrations for PVT variation rw
is
 One fully integrated frequency synthesizer for both WiFi/BT supporting multiple crystal clock
frequencies
te
Un
wa
Bluetooth
r
 Bluetooth specification v2.1+EDR

Fo
 Bluetooth v4.2 Low Energy (LE)

 Integrated PA with 12dBm/10dBm (BDR/EDR) transmit power

l
Typical Rx sensitivity: GFSK -95dBm, DQPSK -94.5dBm, 8-DPSK -87.5dBm

ia
5.2.2 FM
t
en
 65-108MHz with configurable (50 KHz~200 KHz) step

id
 Supports RDS/RBDS(PI/PS/AF/ECC/RT/RTP/DI/PTY/PTYN,etc)
 Digital stereo modulator/demodulator
nf
 Digital audio interface (I2S)

 Audio sensitivity 2dBμVemf ((S+N)/N=26dB)
Co
 Audio S/N 60dB

 Anti-jamming
t
c
 Support short antenna

wa
o
is
5.3 RF Specification
r
Un
Fo
5.3.1 WiFi / BT Specification

l
The WLAN/BT radio characteristics are described in this section. Unless otherwise specified, all
ia
specifications are measured at the RF chip port.

nt
Note: The specification value is valid at room temperature (25 degree).

de
fi

on
w
r
Fo
l
5.3.1.1
ia WiFi Receiver Specification
d
Table 5-1 WiFi Receiver Specification
nt
rl
Parameter Description Min. Typ. Max. Unit
e
o
id
rw
Frequency range 2,412 - 2,484 MHz
f
te
1 Mbps DSSS -99.0 dBm
on
wa
RX sensitivity IEEE
802.11b
5.5 Mbps DSSS -94.0 dBm
r
Fo
6 Mbps OFDM -94.3 dBm

al
ti
en

id

RX Sensitivity IEEE
nf
802.11g
Co
ld
or
oc
rw
is

te
Un
MCS 0 -94.3 dBm

wa
MCS 1 -92.1 dBm
MCS 2 -89.6 dBm

r
Fo
RX sensitivity IEEE
MCS 3 -86.7 dBm
802.11n BW = 20MHz
Green field 800nS guard
l
MCS 4 -82.8 dBm

interval Non-STBC
ia
MCS 5 -78.6 dBm

t
en
MCS 6 -76.8 dBm

id
MCS 7 -75.6 dBm

nf
11 Mbps DSSS -10 dBm

Co
6 Mbps OFDM -20 dBm

t
c
Maximum receive level 54 Mbps OFDM -20 dBm

wa
o
is
MCS0 -20 dBm

r
Un
MCS7 -20 dBm

Fo
Adjacent channel
1 Mbps DSSS 35 dB
rejection (30MHz offset)
l
ia
Adjacent channel
11 Mbps DSSS 35 dB
nt

de
fi

on
w
r
Fo
l
6 Mbps OFDM 16 dB
ia
Adjacent channel
d
54 Mbps OFDM -1 dB
nt
rl
e
Adjacent channel MCS 0 16 dB
o
id
rejection (25MHz
rw
offset),BW = 20MHz MCS 7 -2 dB
f
te
on
776 ~ 794 MHz CDMA2000 TBD dBm
wa
824 ~ 849 MHz GSM TBD dBm
r
880 ~ 915 MHz GSM TBD dBm
Fo
Blocking level for 1dB
RX sensitivity 1,710 ~ 1,785 MHz GSM TBD dBm
degradation
al
1,850 ~ 1,910 MHz GSM TBD dBm
ti
1,850 ~ 1,910 MHz WCDMA TBD dBm
en
1,920 ~ 1,980 MHz WCDMA TBD dBm

id
nf
Co
ld
5.3.1.2 WiFi Transmitter Specification
or
oc
Table 5-2 WiFi Transmitter Specification

rw
is

te
Un

wa
802.11b, 1~11 Mbps DSSS 21 dBm

r
Output power VBAT =

802.11g, 6 ~54Mbps OFDM 19 dBm
Fo
3.6V
802.11n, HT20 MCS0~7 19 dBm
l
ia
802.11b, 1~11 Mbps DSSS

10 %
@Pout=17dBm
t
en
802.11g, 6 ~54Mbps OFDM

EVM -30 dB
@Pout=14dBm
id
802.11n, HT20 MCS0~7

nf
-30 dB
@Pout=14dBm
Co
TX power accuracy -40~85 oC, 2~18dBm ±1.5 dB

t
c
Output power variation ±1.5 dB

Loadpull variation at
wa
o
VSWR = 2:1
is
EVM degradation 4 dB
r
Un
76 ~ 108 MHz -148 dBm/Hz

Fo
Transmitted power (Data 776 ~ 794 MHz -145 dBm/Hz

rate = 1M, Pout
l
ia
=20dBm) 869 ~ 960 MHz -145 dBm/Hz

nt
925 ~ 960 MHz -145 dBm/Hz

de
fi

on
w
r
Fo
l
1,570 ~ 1,580 MHz -144 dBm/Hz
ia
d
1,805 ~ 1,880 MHz -144 dBm/Hz
nt
rl
e
1,930 ~ 1,990 MHz -143 dBm/Hz
o
id
rw
2,110 ~ 2,170MHz -135 dBm/Hz
f
te
on
Harmonic output power 2nd harmonic -12 dBm/MHz
wa
(Data rate = 1M, Pout
=20dBm) 3rd harmonic -23 dBm/MHz
r
Fo
5.3.1.3
al
Bluetooth BDR receiver performance
ti
Table 5-3 Bluetooth BDR receiver performance
en

id

nf
RX sensitivity BER < 0.1% - -95 - dBm

Co
ld
Max. usable signal BER < 0.1% -20 - - dBm
or
oc
Co-channel selectivity (BER< - -

C/I co-channel rw 11 dB
is
0.1%)
te
Un
Adjacent channel selectivity (BER - -

C/I 1MHz 0 dB
< 0.1%)
wa
2nd adjacent channel selectivity - -

C/I 2MHz -30 dB
(BER < 0.1%)
r
Fo
3rd adjacent channel selectivity - -

C/I ≧3MHz -40 dB
(BER < 0.1%)
l
ia
Image channel selectivity (BER < - -

C/I image channel -9 dB
0.1%)
t
en
1MHz adjacent to image channel - -

C/I image 1MHz -20 dB
selectivity (BER <0.1%)
id
30MHz to 2,000MHz -10 - - dBm

nf
-27 - -
Co
2,000MHz to 2,400MHz dBm

Out-of-band blocking
2,500MHz to 3,000MHz -27 - - dBm
t
c
wa
o
3,00MHz to 12.75GHz -10 - - dBm

is
Max. interference level to maintain

r
-39 -30 -
Un
Inter-modulation dBm
0.1% BER
Fo
l
ia
nt
de
fi

on
w
r
Fo
l
ia
d
Table 5-4 Bluetooth BDR transmitter performance
nt
rl
e
Parameter Description Min.
o
Typ. Max. Unit
id
rw
f
te
on
Output power At max power output level - 10 - dBm
wa
Power control step 2 4 8 dB
r
ICFT Initial carrier frequency drift -75 -15 75 kHz
Fo
One slot packet (DH1) - ±10 ±25 kHz
al
Three slot packet (DH3) - ±10 ±40 kHz
ti
Carrier frequency drift
Five slot packet (DH5) - ±10 ±40 kHz
en
Max. drift rate - 180 400 Hz/us

id
△f1avg 140 160 175 kHz

nf
△f2max (for at least 99% of all

Co
ld
Modulation characteristic 99.9 - - %
a
△f2max)
or
oc
△f2avg/△f1avg 0.8 rw0.9 - %

is
te
20-dB bandwidth - 920 1000 kHz
Un
wa
±2MHz offset - -45 -20 dBm

In-band spurious - -48 -40
±3MHz offset dBm
emission
r
Fo
>±3MHz offset - -50 -40 dBm
30MHz to 1GHz - - -39 dBm

l
ia
1GHz to 12.75GHz - - -33 dBm

Out-of-band spurious
t
emission - - -50
en
1.8GHz to 1.9GHz dBm
- - -50
id
5.15 to 5.3GHz dBm

nf
Co
At least 99.9% of all delta F2 max.frequency values recorded over 10 packets must be greater than
185 kHz.
t
c
wa
o
is
5.3.1.4 Bluetooth EDR Receiver Specification

r
Un
Fo
Table 5-5 Bluetooth EDR Receiver Specification

l
ia

nt
de
fi

on
w
r
Fo
l
ia π/4 DQPSK (BER < 0.01%) - -94.5 - dBm
Receiver sensitivity
d
8PSK (BER < 0.01%) - -87.5 - dBm
nt
rl
π/4 DQPSK (BER < 0.1%) -
e
-20 - dBm
o
id
Max. usable signal
rw
8PSK (BER < 0.1%) -20 - - dBm
f
te
on
π/4 DQPSK (BER < 0.1%) - - 13 dB
wa
C/I co-channel
8PSK (BER < 0.1%) - - 21 dB
r
π/4 DQPSK (BER < 0.1%) - - 0 dB
Fo
C/I 1MHz
8PSK (BER < 0.1%) - - 5 dB
C/I 2MHz
al
π/4 DQPSK (BER < 0.1%) - - -30 dB
ti
8PSK (BER < 0.1%) - - -25 dB
en
π/4 DQPSK (BER < 0.1%) - - -40 dB

C/I ≧3MHz
id
8PSK (BER < 0.1%) - - -33 dB

nf
π/4 DQPSK (BER < 0.1%) - - -7 dB

Co
C/I image channel
ld
8PSK (BER < 0.1%) - - 0 dB
or
oc
π/4 DQPSK (BER < 0.1%) - - -20 dB

C/I image 1MHz
rw
is
8PSK (BER < 0.1%) - - -13 dB

te
Un
wa
r
5.3.1.5 Bluetooth EDR Transmitter Specification

Fo
Table 5-6 Bluetooth EDR Transmitter Specification

l
ia

t

en
π/4 DQPSK - 9 - dBm

id
Output power
8PSK - 9 - dBm
nf
π/4 DQPSK 2 -1 8 dB
Co
Relative transmit power

8PSK 2 -1 8 dB
t
c
-10 10
wa
π/4 DQPSK (ω0)

o
6 kHz
is
8PSK(ω0) -10 6 10 kHz

r
Un
Fo
Frequency stability π/4 DQPSK(ωi) -75 8 75 kHz
8PSK(ωi) -75 8 75 kHz

l
ia
π/4 DQPSK|ω0+ωi| -75 8 75 kHz

nt
de
fi

on
w
r
Fo
l
8PSK|ω0+ωi| -75 8 75 kHz
ia
d
π/4 DQPSK(RMS DEVM) - 7 20 %
nt
rl
- 7 13
e
8PSK(RMS DEVM) %
o
id
rw
π/4 DQPSK(99% DEVM) - 8 30 %
f
te
Modulation accuracy
on
8PSK(99% DEVM) - 8 20 %
wa
π/4 DQPSK(Peak DEVM) - 15 35 %
r
8PSK(Peak DEVM) - 15 25 %
Fo
π/4 DQPSK(±1MHz offset) - -38 -26 dB
al
8PSK(±1MHz offset) - -38 -26 dB
ti
π/4 DQPSK(±2MHz offset) - -26 -20 dBm
In-band spurious
en
emission
8PSK(±2MHz offset) - -24 -20 dBm
id
π/4 DQPSK(±3MHz offset) - -42 -40 dBm

nf
8PSK(±3MHz offset) - -43 -40 dBm

Co
ld
or
oc
rw
is
5.3.1.6 Bluetooth LE Receiver Specification

te
Un
Table 5-7 Bluetooth LE Receiver Specification

wa

r

Fo
Receiver sensitivity (*) PER < 30.8% - -91 - dBm

l
ia
Co-channel selectivity (PER <

C/I co-channel - - 21 dB
30.8%)
t
en
Adjacent channel selectivity (PER

C/I 1MHz - - 15 dB
< 30.8%)
id
2nd adjacent channel selectivity

nf
C/I 2MHz - - -17 dB

(PER < 30.8%)
Co
C/I ≧3MHz 3rd adjacent channel selectivity

- - -27 dB
(PER < 30.8%)
t
c
wa
o
Image channel selectivity (PER <

C/I Image channel - - -9 dB
is
30.8%)
r
Un
1MHz adjacent to image channel

Fo
C/I Image 1MHz - - -15 dB

selectivity (PER <30.8%)
30MHz to 2,000MHz - - -27 dBm

l
ia
Out-of-band blocking
2,001MHz to 2,339MHz - - -32 dBm
nt
de
fi

on
w
r
Fo
l
ia 2,501MHz to 3,000MHz - - -32 dBm
d
3,001MHz to 12.75GHz - - -27 dBm
nt
rl
e
o
id
rw
f
te
5.3.1.7 Bluetooth LE Transmitter Specification
on
wa
Table 5-8 Bluetooth LE Transmitter Specification
r
Fo
Output power al
At max. power output level - 5 - dBm
ti
Frequency offset -150 2 150 kHz
en
Carrier frequency offset

Frequency drift -50 2 150 kHz
and drift
id
Max. drift rate -20 3 20 Hz/us

nf
△f1avg 225 251 275 kHz

Co
ld
△f2max (For at least 99% of all
Modulation characteristic 99.9 - - %
△f2max)a
or
oc
△f2avg/△f1avg 0.8 rw0.88 - %

is
te
±2M offset - - -23 dBm
Un
In-band spurious
emission
wa
>±3MHz offset - - -33 dBm

r
Fo
At least 99.9% of all delta F2 max.frequency values recorded over 10 packets must be greater than
l
185 kHz.
t ia
5.3.2 FM Receiver Specification

en
Typical specifications are for channel 98MHz, default register settings and under recommended
id
operating conditions. The min/max specifications are for extreme operating voltage and temperature
nf
conditions, unless otherwise stated.

Co
Table 5-9 FM Receiver Specification

t
c

wa
o
is
Input frequency range 65 108 MHz

r
Un
5 dBuVemf
Fo
(S+N)/N = 26dB, unmatched

Sensitivity1,3
(S+N)/N = 26dB, matched 3 dBuVemf
l
ia
Δf = 22.5 kHz, fmod = 1 kHz, 22 dBuVemf

RDS sensitivity
nt
Δf Pilot = 6.75 kHz,RDS deviation

de
fi

on
w
r
Fo
l
ia = 1.2 kHz.
95% of blocks decoded with no
d
nt
errors, over a sample of 3000
rl
blocks.
e
o
id
Δf = 22.5 kHz, fmod = 1 kHz,
rw
Δf Pilot = 6.75 kHz,
f
te
on
RDS deviation
wa
= 2 kHz. 18 dBuVemf
r
95% of blocks decoded with no
Fo
errors,over a sample of 3000
blocks.
LNA input resistance4 al
Long antenna port 2.4 Ohm
ti
LNA input capacitance4 Long antenna port 8 Pf
en
AM suppression1,4 m = 0.3 60 dB
id
nf
Adjacent channel 53 dB
±200kHz
selectivity1,4
Co
ld
Alternate channel 66 dB
±400kHz
selectivity1,4
or
oc
Spurious response rw
is
In-band 55 dB
rejection4
te
Un
Maximum input level 130 dBuVemf

wa
Audio mono 56 60 dB
(S+N)/N1,3,4
r
Fo
Audio stereo 54 58 dB
(S+N)/N2,3,4
l
ia
Audio stereo 40 dB
f = 75kHz
separation4
t
en
Audio output THD1,4 0.05 0.1 %

id
Audio output frequency 30 15k Hz

3dB corner frequency
range
nf
1 D△f = 22.5kHz, fm = 1kHz, 75 us de-emphasis, mono, L = R

Co
2 D△f = 22.5kHz, fm = 1kHz, 75 us de-emphasis, stereo

t
c
wa
o
3 A-weighting, BW = 300Hz to 15kHz

is
4 Vin = 60dBuVemf
r
Un
Fo
l
ia
nt
de
fi

on
w
r
Fo
l
ia
6 IO Interface Timing Specification
d
nt
rl
e
6.1 SDIO Interface Timing
o
id
rw
f
6.1.1 SDIO Bus Timing
te
on
SDIO Default Speed Timing
wa
r
Bus Timing (Default)
Fo
tWL tWH
al
ti
SD_CLK
en
tTHL tTLH
tISU tIH
id
nf
SD_D0/1/2/3
Co
ld
tODLY(max) tODLY(min)
or
oc
rw
is
SD_D0/1/2/3
te
Un
wa
Figure 6-1 SDIO Bus Timing (Default)

r
Fo
Table 6-1 Bus Timing – Parameter Values (Default)
Parameter Symbol M M Unit

l
i a
ia
n x
. .
t
en
Clock CLK(All values are referred to min(VIH) and max (VIL)

id
Clock frequency Data fPP 0 2 MHz

Transfer Mode 5
nf
Clock frequency Identification fOD 0 4 kHz

Co
Mode 0
0
t
c
Clock low time tWL 1 - ns

wa
o
0
is
Clock high time WH 1 - ns

r
Un
Fo
0
Clock rise time tTLH 1 ns
0
l
ia
Clock fall time tTHL 1 ns

0
nt
de
fi

on
w
r
Fo
l
Inputs CMD, DATA (referenced to CLK)
ia
d
Input set-up time tISU 5 - ns
nt
rl
Input hold time tIH 5 - ns
e
o
id
rw
Outputs CMD, DATA (referenced to CLK)
f
te
Output Delay time during tODLY 0 1 ns
on
Data 4
wa
Transfer Mode
Output Delay time during tODLY 0 5 ns
r
Data 0
Fo
Identification Mode
*Timing parameter is based on CL ≤ 40pF (1 card)
SDIO High Speed Mode Timing
al
ti
en
Bus Timing (High-Speed)

id
tWL tWH
nf
Co
ld
SD_CLK
or
oc
tTHL tTLH
tISU tIH
rw
is
te
Un
SD_D0/1/2/3
wa
r
tODLY(max) tOH(min)
Fo
SD_D0/1/2/3
l
t ia
Figure 6-2 SDIO Bus Timing (High Speed)

en
Table 6-2 Bus Timing – Parameter Values (High Speed)

id
Parameter Symbol Min. Max. Unit

nf
Clock CLK(All values are referred to min(VIH) and max (VIL)

Co
Clock frequency Data fPP 0 50 MHz

t
c
Transfer Mode
wa
o
Clock low time tWL 7 - ns

is
r
Un
Clock high time tWH 7 - ns

Fo
Clock rise time tTLH 3 ns

l
Clock fall time tTHL 3 ns

ia
Inputs CMD, DATA (referenced to CLK)

nt
de
fi

on
w
r
Fo
l
Input set-up time tISU 6 - ns
ia
d
Input hold time tIH 2 - ns
nt
rl
e
Outputs CMD, DATA (referenced to CLK)
o
id
rw
Output Delay time tODLY 0 14 ns
during Data
f
te
on
Transfer Mode
wa
Output Hold Time tOH 2.5 - ns
r
*Timing parameter is based on CL ≤ 40pF (1 card) for each line
Fo
6.2 IIS/PCM Interface Timing
6.2.1 IIS/PCM Interface Timing
al
ti
en
In default mode, IIS output signals, like IISDO, IISLRCK (for master) signal, are sent at the rising edge
of IISCLK. And input signals like IISDI, IISLRCK (for slave), are sampled at the falling edge of IISCLK.
id
nf
Sampling data at negedge of IISCLK

Co
ld
IISCLK
or
oc
IISDI rw
is
te
IISDO/IISLRCK
Un
wa
Figure 6-3 Sampling data at falling edge of IISCLK

r
Output signals can be set as sent edge at falling edge and sampling edge at rising edge, as shown in
Fo
Figure 6-4.
l
ia
Sampling data at posedge of IISCLK

t
IISCLK
en
id
IISDI
nf
IISDO/IISLRCK
Co
t
c
Figure 6-4 Sampling data at rising edge of IISCLK

wa
o
is
The implementation of sampling edge is as following.

r
Un
Fo
l
ia
nt
de
fi

on
w
r
Fo
l
ia
IISCLK
d
Posedge of
nt
rl
IISCLK
e
o
IISCLK
id
rw
f
IISDI
te
on
wa
IISDO/IISLRCK
r
Fo
Figure 6-5 Implementation of sampling data at falling edge of IISCLK
IISCLK
al
ti
Posedge of
IISCLK
en
IISCLK
id
IISDI
nf
IISDO/IISLRCK
Co
ld
or
oc
Figure 6-6 Implementation of sampling data at rising edge of IISCLK

rw
is
6.2.2 Setup time and hold time

te
Un
If we assume that max input delay is 10ns and min input delay is 0ns for IISDI to IISCLK, max output
wa
delay is 10ns and min output delay is 5ns for IISDO/IISLRCK to IISCLK. The clock period time is
50ns for IISCLK.
r
Fo
Sampling Edge
IISCLK period=50ns
l
IISCLK
ia
IISDI
Max_Input_Delay=12ns
t
Max_hold_time=37ns
en
Min_Setup_time=13ns
id
nf
Figure 6-7 Implementation of sampling data at falling edge of IISCLK

Co
Then for IISDI, the setup time range is 13ns<setup_time<25ns, and the hold time range is
25ns<hold_time<37ns. For IISDO/IISLRCK, the setup time range is 13ns<setup_time<25ns, and the
t
c
hold time range is 25ns<hold_time<37ns

wa
o
is
6.3 UART Interface Timing

r
Un
Fo
UART interface timing conforms to standard baud rate, taking UART0 as example in Figure 6-8.
l
ia
nt
de
fi

on
w
r
Fo
l
ia U0CTS
d
2
nt
rl
1
e
U0TXD
o
Midpoint of stop bit
id
rw
f
te
on
U0RXD Midpoint of STOP bit
wa
3
r
U0RTS
Fo
Figure 6-8 UART Interface Timing (Default)
al
ti
Table 6-3 Bus Timing – Parameter Values (Default)
en
RefNO. Characteristics Min. Typical Max. Unit

id
Delay time, U0CTS low to U0TXD

1 - - 1.5 Bit periods
nf
valid
Co
Setup time, U0CTS high before

2 - - - Bit periods
ld
midpoint of stop bit
or
oc
Delay time, midpoint of stop bit to

3 - - rw 0.5 Bit periods
U0RTS high
is
te
Un
For T2 timing, If T2 >= 0.5 bit time (U0CTS high active before the stop bit), next TX data will not send;
wa
else, the next TX data will send out, and the data after the next one will not send.
r
Fo
l
t ia
en
id
nf
Co
t
c
wa
o
is
r
Un
Fo
l
ia
nt
de
fi

on

SC2332B Device Specification - V1.2

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

SC2332B Device Specification - V1.2

Uploaded by

Copyright:

Available Formats

w

UNISOC TECHNOLOGIES INC., Confidential and Proprietary

environment are pre-requisite.

UNISOC TECHNOLOGIES INC., Confidential and Proprietary 2 of 43

1.0 2019/09/09 First release

1.2 2019/10/23 Delete invalid information

UNISOC TECHNOLOGIES INC., Confidential and Proprietary 3 of 43

1.2.3 Bluetooth Features ........................................................................................ 7

3.2 Pin List .............................................................................................................................. 13

3.4 Control Registers for BT/WiFi/FM .................................................................................... 23

3.4.1 Pin_reg Memory map .................................................................................. 23

3.4.2 Register Description .................................................................................... 24

4.1 Absolute Maximum Ratings ............................................................................................. 26

4.3 Power On Sequence ........................................................................................................ 27

4.4 Leakage Current ............................................................................................................... 27

5.1.1 Functional block diagram ............................................................................ 28

5.2 Features ........................................................................................................................... 30

5.3 RF Specification ............................................................................................................... 30

5.3.1 WiFi / BT Specification ................................................................................ 30

5.3.2 FM Receiver Specification ........................................................................... 37

6 IO INTERFACE TIMING SPECIFICATION ................................................................................ 39

6.1 SDIO Interface Timing ...................................................................................................... 39

6.2 IIS/PCM Interface Timing ................................................................................................. 41

6.2.2 Setup time and hold time ............................................................................. 42

6.3 UART Interface Timing ..................................................................................................... 42

UNISOC TECHNOLOGIES INC., Confidential and Proprietary 4 of 43

Figure 2-3 Package Outline （Detail:“A”） ................................................................................... 10

Figure 2-5 Package Outline (Dimension) ........................................................................................ 12

Figure 4-1 Power-on sequence ....................................................................................................... 27

Figure 6-8 UART Interface Timing (Default) .................................................................................... 43

UNISOC TECHNOLOGIES INC., Confidential and Proprietary 5 of 43

Table 3-3 Pin Multiplexed Function list ........................................................................................... 21

Table 3-6 Pin control register0 ....................................................................................................... 24

Table 3-7 SD interface pin control register ..................................................................................... 24

Table 5-5 Bluetooth EDR Receiver Specification ........................................................................... 34

Table 5-6 Bluetooth EDR Transmitter Specification ....................................................................... 35

Table 5-8 Bluetooth LE Transmitter Specification .......................................................................... 37

Table 5-9 FM Receiver Specification.............................................................................................. 37

Table 6-2 Bus Timing – Parameter Values (High Speed) .............................................................. 40

UNISOC TECHNOLOGIES INC., Confidential and Proprietary 6 of 43

1.2.1 General Features

 175Ball BGA package (7.5mm x 5.3mm, 0.4mm pitch)

 Share 26M clock with SPRD chipset

Single-band 2.4 GHz single stream IEEE 802.11b/g/n

 Integrated DPD technology to reduce power consumption.

 Integrated power detector to support TX power control

 Build-in calibration for PVT variation

o WPS2.0, EAP-sim, Hotspot2.0

o Support 802.11w - Secure Management Frames

 Support 802.11k - Resource Management

 Support WIFI P2P mode

 Support STA&P2P concurrency in same channel

 Low power mode

DTIM Lower power mode

1.2.3 Bluetooth Features

 Bluetooth v4.2 Low Energy (LE)

UNISOC TECHNOLOGIES INC., Confidential and Proprietary 7 of 43

 Digital stereo modulator/demodulator

External power supply 1.8V I/O

 WiFi power domain for power saving

UNISOC TECHNOLOGIES INC., Confidential and Proprietary 8 of 43

CHIP_E SD_CM DVDD11

RF_ISM FM_LAN AVDD16