Professional Documents
Culture Documents
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2019.10.24
SR3595D RF Design
Guide V1.1
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History
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Version Date Notes
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2018.05.01
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V1.0 First version
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1. Update UNISOC new temple
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V1.1 2. Add C2K baseband introduction
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2019.10.24
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Document Information
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Chip Platform OS Version Keyword
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SC9832E,SC9820E,SC9863A,UMS312,
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N/A RF Design Guide
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UMS512, UMS512T, T117
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Contents
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Ⅰ
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Typical Application
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Ⅱ
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Ⅲ RF Transceiver power domain
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Ⅴ
Ⅳ RF Design Notes
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Un
Ⅵ General Introduction
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General Introduction
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Modem Features
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TD-LTE/ LTE FDD Baseband
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Support 3GPP Release 12
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Support downlink Category 7, UL Cat13
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Support bands
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TD-LTE : Band34,Band38,Band 39, Band 40, Band 41
en
id
LTE-FDD : Band1, 2, 3, 4, 5, 6, 7, 8, 9,12, 13, 17, 18,19,20,25,26,28,29
nf
Co
ld
or
oc
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WCDMA/HSDPA/HSUPA Baseband
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Un
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Release 8 HSDPA, up to 42Mbps(Category 24)
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Fo
Release 8 HSUPA, up to 11Mbps(Category 7)
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Band support: Band1,Band2 ,Band3, Band4,Band5 ,Band6 ,band8,band9 and 10
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TD-SCDMA/HSDPA/HSUPA Baseband
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Compatible with TD-SCDMA (TDD LCR) standard in 3GPP Release 7
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Support BandF (1880~1920MHz) and BandA (2010~2025MHz)
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Support HSDPA 2.8Mbps (category 15)
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GSM/GPRS/EDGE Baseband
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Compatible with GSM/GPRS/EDGE Release 99, GSM850,GSM900, DCS1800, and PCS1900
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ld
recommendations
or
oc
GPRS and E-GPRS all classes up to and including class 12
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CDMA2000 Baseband
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CDMA2000 1xRTT Rel 0
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CDMA2000 1xEV-DO high speed package data Rel 0 and Rel A. ti
CDMA2000 1x: 153.6Kbps for both links
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ld
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or
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te
oc
Note:The above baseband information is the max capability of SR3595D. The baseband
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capability is also dependent on the BB chip. The accurate capability could be found in the
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chapter of Modem Features of BB Device Specification
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7
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Typical Application(Global use Phase 2.5)
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on rw or
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CONFIDENTIAL
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8
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Fo r
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Typical Application(Global use Phase 2.5)
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on rw or
fi or ld
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CONFIDENTIAL
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RF Transceiver design notes
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en
or
The SR3595D has 6 transmit ports, 12 primary RX ports and 11 diversity RX ports. These
id
rw
ports are single-ended.
nf
te
Co
wa
oc PRX
r
DRX
Fo
is
port
Un
port
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ti
en
id
nf
Co
ld
or
oc
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Un
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Fo
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en
ld
id
or
nf
TX
rw
Co
port
te
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Un
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den
fi
on
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ld
en
or
id
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nf
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Co
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Un
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TX
en
id
Port Frequency support
nf
Co
ld
TX_L1
or
LB:699~915MHz
oc
rw
TX_L2
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te
Un
wa
TX_H1
r
Fo
TX_H2
MHB:1710~2690MHz
TX_H3 al
ti
en
TX_H4
ld
id
or
nf
rw
Co
te
oc
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Un
Fo
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den
fi
on
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ld
en
or
id
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nf
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PRX Ports assign
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Primary RX
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Port Frequency support
is
Un
al
PRX_L1
ti
PRX_L2 LB:699~960MHz
en
id
PRX_L3 MB:1805~2200MHz
nf
PRX_L4
Co
ld
or
PRX_M1 oc
rw
LB:699~960MHz
is
PRX_M2
te
Un
MHB:1805~2700MHz
wa
PRX_M3
r
PRX_M4
Fo
PRX_H1
al
ti
PRX_H2 MHB:1805~2700MHz
en
ld
id
PRX_H3
or
nf
PRX_H4
rw
Co
te
oc
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r
Un
Fo
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den
fi
on
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ld
DRX Ports assign
en
or
id
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Diversity RX
nf
te
Co
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Port Frequency support
oc
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DRX_L1
Fo
is
Un
al
LB:699~960MHz
DRX_L2
ti
MB:1805~2200MHz
en
id
DRX_L3
nf
Co
DRX_M1
ld
or
DRX_M2 LB:699~960MHz oc
rw
is
DRX_M3 MHB:1805~2700MHz
te
Un
wa
DRX_M4
r
DRX_H1
Fo
DRX_H2
MHB:1805~2700MHz al
ti
DRX_H3
en
DRX_H4
ld
id
or
nf
rw
Co
te
oc
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Un
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den
fi
on
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ld
en
or
LVDS interface (Low-voltage Differential Signaling)
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nf
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Co
•The maximum bit rate is 1.04 Gbps.
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Fo
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•There are 2 group LVDS, each group contains two
Un
al
downlink ports and one uplink port.
ti
en
id
nf
Co
ld
or
oc
rw
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Un
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Fo
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en
ld
id
or
nf
rw
Co
te
oc
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Un
Fo
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den
fi
on
al
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ld
en
or
id
rw
nf
te
Co
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oc
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Un
al
ti
en
SPI(Serial Parallel Interface)
id
nf
2 group SPI are provided, each of them include
Co
ld
three ports of DATA, CLK, and LE
or
oc
rw
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Un
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en
ld
id
or
nf
rw
Co
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oc
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Un
Fo
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den
fi
on
al
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ld
en
or
id
rw
nf
te
Co
32KHz output
wa
oc
r
Fo
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Un
al
ti
en
id
nf
Co
ld
26MHz XO output (un-tuned)
or
oc
rw
is
te
Un
wa
r
Fo
al
ti (Unused)26MHz XO output (tuned)
en
ld
id
or
nf
rw
Co
te
26MHz input
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Un
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den
fi
on
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Un al
Un is Fo
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oc Co w
RF Transceiver design notes
Co nf
nf id
id en
en ti
ti al
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16
16
Fo
Fo r
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on rw or
fi or ld
d en
ld
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Fo
r
wa
te
rw
or
ld
CONFIDENTIAL
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RF Transceiver power domain
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ti
ld
en
or
Maximum current consumption @
id
rw
nf
te
each power domain
Co
wa
oc
r
10mA@~1.8V
Fo
is
Un
al
ti
en
32mA@~1.8V
id
nf
Co
ld
243mA@~1.8V
or
oc
rw
is
te
Un
wa
162mA@~1.8V
r
Fo
al
ti
287mA@~1.2V
en
ld
id
or
nf
rw
Co
te
47mA@~1.2V
oc
wa
is
r
Un
Fo
VDD1V1DIG can
81mA@~1.1V
al
use internal LDO ti
from VDD1V8IO
den
fi
on
al
ti
ld
en
or
id
rw
nf
Note:
te
Co
wa
oc
r
Fo
is
In order to reduce voltage drop, need
Un
al
use star topology chain on the
ti
VDDRF1V8 and the VDDRF1V25.
en
id
nf
Co
ld
or
oc
rw
is
te
Un
wa
transceiver side
r
Fo
al
ti
en
ld
id
or
nf
rw
Co
te
oc
wa
is
r
Un
Fo
al
ti
en
d
fi
on
nf id
id en
en ti
ti al
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19
19
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on rw or
fi or ld
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CONFIDENTIAL
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RF Design Notes
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ld
en
or
3G/4G TX Module
id
rw
nf
te
Co
The transceiver output/PA input matching network
wa
oc
r
Do not delete filter capacitors for
Fo
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ti
en
id
nf
Co
ld
or
oc
rw
is
te
Un
wa
r
Fo
al
ti
en
ld
id
or
nf
rw
Co
te
oc
wa
is
r
Un
Fo
al
The PA output matching close to PA
ti
den
fi
on
al
ti
ld
en
or
id
rw
nf
te
Co
wa
oc
r
Fo
is
Antenna port
Un
al
Transceiver port
ti
en
id
Matching
nf
Matching
Co
network
ld
network
or
oc
rw
is
te
Un
wa
r
Fo
al
ti
en
ld
id
or
nf
rw
Co
te
oc
wa
is
r
Un
Fo
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ti
den
fi
on
al
ti
ld
en
or
These components need to be as
id
rw
close to Duplexer when placement
nf
te
Co
wa
oc
r
Fo
is
Antenna port Transceiver port
Un
al
ti
en
id
nf
Matching
Co
ld
network Matching
or
oc
rw
is
network
te
Un
wa
r
Fo
al
ti
en
ld
id
or
nf
rw
Co
te
oc
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Un
Fo
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den
fi
on
al
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ld
en
GNSS and LTE B13 coexistence Application Design---SCH
or
id
rw
nf
Isolation of GNSS and LTE B13 antenna >30dB;
te
Co
wa
oc
r
Required low pass filter on the LTE B13 TX path;
Fo
is
Un
al
ti
en
id
nf
Co
ld
or
oc
rw
is
te
Un
wa
r
Fo
If the attenuation of GNSS saw at LTE B13 is less than 35dB, or the performance of LNA at B13 2H
is bad, a notch circuit is also required on GNSS path. al
ti
en
ld
id
recommended values
or
nf
C1 C2
rw
Co
te
oc
C1=C2=3.6pF
wa
is
C3=4.7pF
r
Un
Fo
C3 L1=7.4nH
L1 al
ti
den
fi
on
al
ti
ld
en
or
id
rw
nf
te
Co
wa
oc
r
Fo
is
Un
al
Antenna port Transceiver port
ti
en
id
nf
Co
ld
or
Matchingoc Matching
rw
is
network network
te
Un
wa
r
Fo
al
ti
en
ld
id
or
nf
rw
Co
te
oc
wa
This filter(TDD LTE B40/B41) is for TX. The maximum input
is
r
Un
Fo
al
ti
den
fi
on
al
ti
ld
en
or
id
rw
nf
te
Co
wa
oc
r
Fo
is
Un
al
ti
en
id
Matching
nf
Co
network
ld
or
oc
rw
is
te
Un
wa
r
Fo
al
ti
en
ld
id
or
nf
Matching
rw
Co
network
te
oc
wa
is
r
Un
Fo
MIPI Data Bus, MIPI Clk Bus and MIPI Supply VIO.
al
MIPI CLK and MIPI Data trace need reserve filter ti
capacitor position
den
fi
on
al
ti
ld
en
or
id
RF Antenna tuner circuits
rw
nf
te
Co
wa
oc
r
Fo
is
Un
al
ti
en
id
nf
Co
ld
or
oc
rw
is
te
Un
wa
r
Fo
al
ti
en
ld
id
or
nf
rw
Co
te
oc
wa
is
r
Un
Fo
In the RF Parts,
al
suggested GPIO is
ti
RFCTL 0~11.
den
fi
on
al
ti
ld
en
or
Route each group of LVDS signals as differential pairs and keep a distance away from RF
id
rw
and reference clock traces
nf
te
Avoid crossing these traces; if necessary, cross them only near their end points at SR3595D
Co
wa
Isolate from other traces, especially from digital logic and clock traces, with ground and
oc
r
Fo
ground vias on both sides, plus ground above and below if routed on internal layers. The
is
Un
al
ti
en
id
nf
Co
ld
or
oc
rw
is
te
Un
wa
r
Fo
al
ti
en
ld
id
or
nf
rw
Co
te
oc
wa
is
r
Un
Fo
The LVDS for TX/resistor
al
close to transceiver ti
den
fi
on
al
ti
ld
en
or
The Chip GND must connected like below(yellow line)
id
rw
nf
te
Co
wa
oc
r
Fo
is
Note:
Un
al
ti
en
id
In order to reduce noise from
nf
LVDS to RF RX port .The Via
Co
ld
or
oc of LVDS pin should use
rw
is
te
Un
wa
the HDI1 PCB, and the Via
r
trace(between via and pin)
Fo
al
ti should as short as possible.
en
ld
id
or
nf
rw
Co
te
oc
wa
is
r
Un
Fo
al
ti
den
fi
on
al
ti
ld
en
or
id
rw
DIV RX Port
nf
te
Co
wa
oc
r
Fo
is
Un
al
ti
en
LVDS trace need to be as far to RX port
id
nf
Co
ld
or
oc
rw
is
te
Un
wa
r
Fo
al
ti
en
ld
id
or
nf
rw
Co
Main RX Port
te
oc
wa
is
r
Un
Fo
al
ti
den
fi
on
id
en
ti
Un al
Un is Fo
is oc r
oc Co w
Co nf
nf id
id en
en ti
ti al
al
30
30
Fo
Fo r
r wa
wa te
te rw
on rw or
fi or ld
d en
ld
ti
al
Fo
r
wa
te
rw
or
ld
SPI interface for the read and write
CONFIDENTIAL
w
r
Fo
RF Design Notes
al
ti
ld
en
or
The buffer output 26MHz
id
rw
nf
te
Co
wa
oc
r
Fo
is
Un
al
ti
en
id
nf
Co
ld
or
oc
rw
is
te
Un
wa
r
Fo
al
ti
en
ld
id
or
nf
rw
Co
te
oc
REF_OUT need to isolated from other signals, especially RF traces and RF parts’ controlling
wa
is
signals
r
Un
Fo
Avoid parallel with PA ramp, GSM PA control lines and power supply traces
al
Change to inner layer using vias and surround with ground ti
den
fi
on
al
ti
ld
en
or
Matching Networks—RX
id
rw
nf
te
Co
wa
The recommended matching procedure is:
oc
r
Fo
RX:
is
Un
al
Measure the SR3595D IC RF ports S11 differential parameter
ti
en
Measure the SAW filter S22 differentially with a 50Ω input port
id
nf
Design a complex conjugate match between these two sets of measured S-parameters
Co
ld
or
oc
Matching components between outputs and SR3595D RX inputs need to be tuned for best
rw
is
te
performance
Un
wa
ANT:
r
Fo
The ant port of duplexer needs to be tuned to get a convergent S11 over the TX frequency
al
ti
range on the VNA
en
ld
id
or
nf
rw
Co
te
oc
wa
is
r
Un
Fo
al
ti
den
fi
on
al
ti
ld
en
or
id
rw
nf
te
Matching Networks—TX
Co
wa
oc
The Tx matching network near SR3595D is a PI attenuation network, the port should be
r
Fo
is
impedanced to 50Ω,it may also to improve the modulation spectrum performance. The
Un
al
ti
ANT_CON also should be impedance to 50Ω
en
id
The GSM PA’s Tx path has HB_IN and LB_IN, Be careful not to reverse
nf
Co
ld
Vramp pin need a RC LPF used to suppress harmonics, Generally use series a 1.5K resistor
or
oc
rw
is
and shunt a 470pF capacitor to GND structure
te
Un
wa
VBAT pin use 10uF,0.1uF,22pF capacitors in parallel structure to filter out noise
r
Fo
al
ti
en
ld
id
or
nf
rw
Co
te
oc
wa
is
r
Un
Fo
al
ti
den
fi
on
en
ti
Un al
Un is Fo
is oc r
oc Co w
Co nf
nf id
id en
en ti
al
Example 1. SC9863A+SR3595D TSX description
ti
al
34
34
Fo
Fo r
r wa
wa te
te rw
on rw or
fi or ld
d en
ld
ti
al
Fo
r
wa
te
rw
or
ld
CONFIDENTIAL
Un
is
oc
Co
en
ti
Un al
Un is Fo
is oc r
oc Co w
Co nf
nf id
id en
en ti
ti al
Example 2. SC9863A+SR3595D TCXO description
al
35
35
Fo
Fo r
r wa
wa te
te rw
on rw or
fi or ld
d en
ld
ti
al
Fo
r
wa
te
rw
or
ld
CONFIDENTIAL
w
r
Fo
CLK Design Notes
al
ti
ld
en
or
Example 3. UMS312+SR3595D TSX+TCXO description
id
rw
nf
te
Co
wa
PMIC Transceiver AP WCN
oc
r
Fo
SR3595D UMS312 UMW2652
is
UMP510G
Un
al
ti
en
id
REF_OUT0 XO_P CLK_AUX0 CLK32K
nf
Co
ld
or
XTAL_IN
oc
rw
is
REF_OUT3 CLK26M_SINE_IN
te
Un
wa
32K
CLK32K CLK_32K
r
Fo
XTAL_OUT
TSEN_VREFP
al
ti
TCXO
en
TSEN_IN
ld
id
or
XTAL_IN
nf
rw
Co
te
26M
oc
wa
is
r
Un
XTAL_OUT
Fo
TSEN_VREFN
al
ti
den
fi
on
al
ti
ld
en
or
Example 4. UMS512(T)+SR3595D TSX only (reserved TCXO for WCN) description
id
rw
nf
te
Co
wa
PMIC Transceiver AP WCN
oc
r
Fo
is
Un
al
ti
CLK_AUX0 CLK32K
en
REF_OUT0 XO_P
id
nf
Co
XTAL_IN
ld
or
REF_OUT3
oc CLK26M_SINE_IN
rw
NF
is
32K
te
Un
CLK26M CLK26M_OUT
wa
XTAL_OUT CLK32K CLK_32K
r
Fo
TSEN_VREFP
al
TSX_OSC_DYNAMIC_SEL
PTESTO ti GPIO0
TSEN_IN
en
REF_OUT1 XTAL_IN
ld
id
XTAL_IN
or
nf
rw
Co
te
26M TSX/TCXO
oc
NF
wa
is
r
Un
Fo
XTAL_OUT
TSEN_VREFN
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Note: AP outputs 26M(CLK26M_OUT) to PMIC for synchronous operation.
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ti
ld
en
or
Example 5. UMS512(T)+SR3595D TSX+TCXO description
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nf
te
Co
wa
PMIC Transceiver AP WCN
oc
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Fo
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Un
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ti
en
CLK_AUX0 CLK32K
id
REF_OUT0 XO_P
nf
Co
ld
XTAL_IN
or
oc
rw
is
NF REF_OUT3 CLK26M_SINE_IN
te
32K
Un
CLK26M CLK26M_OUT
wa
XTAL_OUT CLK32K CLK_32K
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Fo
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TSEN_VREFP
ti
en
TSEN_IN
ld
REF_OUT1
id
XTAL_IN
or
nf
XTAL_IN
rw
Co
te
oc
wa
26M TCXO
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r
Un
Fo
XTAL_OUT
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TSEN_VREFN ti
en
ld
en
or
id
rw
nf
te
Co
wa
oc
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Fo
is
THANKS
Un
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ld
or
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Un
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document is confidential and proprietary information of
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and the information contained therein is to be held in
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guarantees of any kind with respect to the matters addressed
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in this document. In no event shall UNISOC be responsible or
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alleged to be caused by or in connection with the use of or
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