SR3595D Device Specification - V1.2

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SR3595D RF Transceiver
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Device Specification
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Rev.1.2
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June 26, 2019

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www.unisoc.com
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UNISOC, Inc., Confidential and Proprietary

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IMPORTANT NOTICE
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COPYRIGHT NOTICE
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Copyright © 2019, UNISOC Communications, Inc. All rights reserved.
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TRADEMARKS
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UNISOC Communications, Inc. and UNISOC Communications, Inc.’s products are exclusively owned by
UNISOC Communications, Inc. References to other companies and their products use trademarks owned
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by the respective companies and are for reference purpose only.
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WARRANTY DISCLAIMER
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UNISOC Communications, Inc. makes no representations or warranties, either express or implied, by or

with respect to anything in this document, and shall not be liable for any implied warranties of
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merchantability or fitness for a particular purpose or for any indirect, special or consequential damages.
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CONFIDENTIALITY
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The information contained herein (including any attachments) is confidential. The recipient hereby
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acknowledges the confidentiality of this document, and except for the specific purpose, this document
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shall not be disclosed to any third party.

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Revision History
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Revision Date Description
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1.0 01/22/2018 Official release
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1.1 06/06/2019 Update front color and company logo
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1.2 06/26/2019 Table 1 ESD performance update
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Table of Contents
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1 Introduction .......................................................................................................................................... 8
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1.1 Key Features .................................................................................................................................... 8
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2 Operation Condition .......................................................................................................................... 11
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2.1 Absolute Maximum Ratings ........................................................................................................... 11
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2.2 Recommended Operating Condition .............................................................................................. 11
3 RX Port Specifications ...................................................................................................................... 12
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3.1 Overview ........................................................................................................................................ 12
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3.2 AC Specifications ........................................................................................................................... 13
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3.2.1 GSM RX RF........................................................................................................................... 13
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WCDMA RX RF ..................................................................................................................... 14
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3.2.3 TD-SCDMA RX RF ................................................................................................................ 15
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3.2.4 LTE RX RF ............................................................................................................................ 16

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4 TX Port Specifications ....................................................................................................................... 17

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4.1 GSM TX RF OUTPUT .................................................................................................................... 18

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4.2 GSM TX MODULATED .................................................................................................................. 18
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4.3 WCDMA TX RF OUTPUT .............................................................................................................. 19
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4.4 WCDMA TX MODULATED ............................................................................................................ 20

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4.5 TD-SCDMA TX RF OUTPUT ......................................................................................................... 21

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4.6 TD-SCDMA TX MODULATED ....................................................................................................... 22

4.7 LTE TX RF OUTPUT ..................................................................................................................... 22
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4.8 LTE TX MODULATED ................................................................................................................... 23

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5 Clock Specification ............................................................................................................................ 24

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5.1 Block Diagram ................................................................................................................................ 24

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5.2 XO Input ......................................................................................................................................... 24

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5.4 Reference Clock Output (REFOUT) .............................................................................................. 26

5.5 Power Detector .............................................................................................................................. 26
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6 Power Supply Sequencing ................................................................................................................ 27

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6.1 Overview ........................................................................................................................................ 27
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6.2 Digital (1.1V) supply ....................................................................................................................... 27

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6.2.1 Internal Supply Mode ............................................................................................................ 27

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6.2.2 External Supply mode ........................................................................................................... 27

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6.3 Valid supply sequences ................................................................................................................. 28

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7 Function Description ......................................................................................................................... 30

7.1 RCB Interface ................................................................................................................................. 30
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7.1.1 RCB Signal Description ......................................................................................................... 30

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7.1.2 RCB Datagram ...................................................................................................................... 30
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7.2 Data Interface ................................................................................................................................. 32
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7.3 Reference Clock ............................................................................................................................. 32
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8 Package Detail .................................................................................................................................... 33
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8.1 Package Dimension ....................................................................................................................... 33
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8.2 Solder Ball Dimension .................................................................................................................... 34
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8.3 Reflow Profiles ............................................................................................................................... 35
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8.4 Ball Map ......................................................................................................................................... 36
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8.5 Pin Description ............................................................................................................................... 37
8.6 Part Numbering .............................................................................................................................. 42
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9 Contact Information ........................................................................................................................... 43
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List of Figures
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FIGURE 1: BLOCK DIAGRAM ............................................................................................................................. 9
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FIGURE 2: XO BLOCK DIAGRAM ..................................................................................................................... 24
FIGURE 3: SR3595D SUPPLY DIAGRAM.......................................................................................................... 27
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FIGURE 4: INTERNAL SUPPLY FOR DIGITAL ...................................................................................................... 27
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FIGURE 5: EXTERNAL SUPPLY FOR DIGITAL .................................................................................................... 28
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FIGURE 6: VALID SUPPLY SEQUENCES ............................................................................................................ 28
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FIGURE 7: RCB DATAGRAM ........................................................................................................................... 31
FIGURE 8: RCB CONFIGURATION TIMING ......................................................................................................... 31
FIGURE 9: PACKAGE DIMENSION .................................................................................................................... 33
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FIGURE 10: SOLDER BALL DIMENSION ............................................................................................................ 34
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FIGURE 11: CLASSIFICATION PROFILE ............................................................................................................ 35
FIGURE 12: BALL MAP ................................................................................................................................... 36
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List of Tables
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TABLE 1: ABSOLUTE MAXIMUM RATINGS......................................................................................................... 11
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TABLE 2: POWER SUPPLIES ........................................................................................................................... 11
TABLE 3: PRIMARY RX PORTS ....................................................................................................................... 12
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TABLE 4: DIVERSITY RX PORTS ..................................................................................................................... 12
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TABLE 5: AC SPECIFICATIONS - GSM RX RF ................................................................................................. 13
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TABLE 6: AC SPECIFICATIONS - WCDMA RX RF ........................................................................................... 14
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TABLE 7: AC SPECIFICATION - TDSCDMA RX RF ......................................................................................... 15
TABLE 8: AC SPECIFICATIONS - LTE RX RF ................................................................................................... 16
TABLE 9: TXA PORTS .................................................................................................................................... 17
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TABLE 10: AC SPECIFICATIONS - GSM TX RF................................................................................................ 18
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TABLE 11: AC SPECIFICATION - GSM TX MODULATED ................................................................................... 18
TABLE 12: AC SPECIFICATIONS - WCDMA TX RF .......................................................................................... 19
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TABLE 13: AC SPECIFICATIONS - WCDMA TX MODULATED ............................................................................ 20
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TABLE 14: AC SPECIFICATIONS - TDSCDMA TX RF ...................................................................................... 21
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TABLE 15: AC SPECIFICATIONS - TDSCDMA TX MODULATED ........................................................................ 22
TABLE 16: AC SPECIFICATIONS - LTE TX RF ................................................................................................. 22
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TABLE 17: AC SPECIFICATIONS - LTE TX MODULATED ................................................................................... 23

TABLE 18: CLOCK SPECIFICATIONS - XO INPUT (TCXO) ................................................................................. 24
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TABLE 19: CLOCK SPECIFICATIONS - XO INPUT (DCXO) ................................................................................. 25

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TABLE 20: CLOCK SPECIFICATIONS - REFOUT1/2/3 ...................................................................................... 26

TABLE 21: AC SPECIFICATIONS - POWER DETECTOR ...................................................................................... 26
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TABLE 22: TERMS AND DEFINITIONS ............................................................................................................... 29
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TABLE 23: RCB CONFIGURATION TIMING ....................................................................................................... 32
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TABLE 24: SOLDER BALL DIMENSION.............................................................................................................. 34
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TABLE 25: CLASSIFICATION REFLOW PROFILES .............................................................................................. 35
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TABLE 26: PIN DESCRIPTION .......................................................................................................................... 37

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1 Introduction
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SR3595D is a highly integrated, single-die radio transceiver chip that supports 4G LTE
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with LTE-A for FDD-LTE, TDD-LTE, 3G WCDMA, HSDPA, HSUPA, GSM/EDGE as well
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as TD-SCDMA operation. Implemented in low cost bulk CMOS, it is optimized to meet
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the challenges of today’s small form factor, power efficient, high performance cellular
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handsets. The SR3595D has total of 6 single-ended transmit ports, 12 primary and 11
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diversity single-ended receive ports. The SR3595D provides connectivity multiple bands
of operation. The SR3595D offers a cost competitive and small footprint radio solution
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for multi-mode, multi-band applications with the highest performance at the lowest
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power.
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The linear transceiver architecture of SR3595D is utilized for 2.5G, 3G and 4G systems,
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offering excellent performance and design margins over 3GPP requirements. For 2.5G,
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a direct modulation scheme is used in the transmitter and performance of 2.5G receive
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and transmit chains is such that no additional RF filters are required to meet out-of-band
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noise specifications. The output driver stage for each transmitter chain is single-ended
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and matched to 50Ω.

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The transceiver supports digital and Digital I/Q interfaces with simple 3-wire bus
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architecture to program the radio.
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Refer to Figure 1 for Block diagram.
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1.1 Key Features
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 Fully integrated single chip multi-mode, multi-band transceiver in bulk CMOS

 TDD-LTE Band: 34, 38, 39, 40, 41
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 FDD-LTE Band: 1, 2, 3, 4, 5, 6,7, 8, 12, 13, 17, 18,19, 20, 25, 26, 28, 29 (DL only), 66
 TD-SCDMA Band: 34, 39
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 WCDMA Band: 1 to 6, 8, 9, 10
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 GSM/EDGE: GSM850, EGSM900, DCS1800, PCS 1900

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 Single-ended LNAs in all receive bands and all modes of operation

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 All TX outputs are single-ended and internally matched to 50Ω

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 Digital IQ interface
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 Ultra Low Power Consumption

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 Three sets of 26MHz reference clock outputs
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 Build-in 32k Hz clock output

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
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123balls BGA package

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 4.5mm x 4.5mm ,0.35mm pitch


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RoHS Compliance
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 Halogen Free (HF) Compliance

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N P
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XO XO
UNISOC 32 K
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REFOUT 1
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Temp Internal
V 1.1 06 / 06 /2019 SR 3595 D Sensor digital XO REFOUT 2
REFOUT 3
BBPLL
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CLK 26M
1 .8V RX VDD 1V 8RX

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1.25 V RX VDD 1V 2RX
1 .25 V TX VDD 1V 2TX

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1 BB _A DCOC 1 .8 V TX VDD 1V 8TX
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DRX L 1 2 RX _LB LB
DRX L 2 MUX 1.1 V DIG VDD 1V 1DIG
3 BAL MUX
DRX L 3 4 MIXER “A” 1 .8 V XO VDD 1V8XO
PMA LPF ADC
DRX M 1 1 1.8 V IO VDD 1V 8IO
RX_ SHML
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DRX M 2 2 HMLB TX CAP TXCAP

MUX
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3 BAL BB _B DCOC
DRX M 3 BBA_PRX +
DRX M 4 4 MIXER “B” PRX 1
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RX_ SHML MUX BBA_PRX -
DRX H 1 1
DRX
DRX H 2 2 SHM PMA LPF ADC
DRX H 3 MUX
3 BAL BBB_PRX +
DRX H 4 4 MIXER “C” PRX 2
BBB_PRX -
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GMSK
RX B
Modulator PLL
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LN LP
RX A
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PLL
LP
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LVDS
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HB /MB LP BB
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PRX H 4 4 MIXER “C” BB _B

PRX H 3 3 MUX SHM DCOC
PRX H 2 2 “C” BAL
PRX H 1 1 MUX
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HB /MB PMA LPF ADC

PRX M 4 4 MIXER “B”
PRX
PRX M 3 3 MUX HMLB

LP BB DIG
PRX M 2 2 “B” BAL
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BB _ A BBA_DRX +
PRX M 1 1 DCOC DRX 1
BBA _DRX -
PRX L 4 4 MIXER “A” MUX
PRX L 3 3 MUX LB LB
PRX L 2 2 “A” BAL PMA LPF ADC
BBB _DRX +
PRX L 1 1 DRX 2
GSM RX BB
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BBB_DRX -
X-Switch
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TX A
PLL
LN LP
MUX
Digital
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BB PLL
LVDS PLL
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SPIA _CLK
A
-
SPIA _DAT
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SPI
SPIA _LE
PDETA PDET ADC
SPIB _CLK
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B
-
SPIB _DAT
SPI
HB 1 TX MHB SPIB _LE

HB 2
HB 3 BAL MUX
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gm LPF DAC
TX
TX MB
TX LB
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LB1
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LB2 BAL
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BBA_TX +
TX A
BBA_TX -
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LVDS
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BBB_TX +
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TX B
BBB_TX -
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Figure 1: Block Diagram

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Feature Summary
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 GSM/GPRS/EDGE
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o Integrated radio transceiver fully supporting GSM, GPRS and EDGE
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o GPRS and E-GPRS all classes up to and including class 12
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o Quad-band GSM operation
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o Full digital gain control on TX and RX
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o Single-ended TX output
o Digital I/Q interface
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
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WCDMA
o Support for band 1 to 6, 8, 9 and 10
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o Full digital gain control
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o Full HSDPA and HSUPA supportti
o Programmable channel filter
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o Single-ended RX inputs
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o Single-ended TX outputs
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TD-SCDMA
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o Support for band 34, 39
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o Full HSDPA and HSUPA support

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Digital I/Q interface

 LTE
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o Support TDD-LTE band 34, 38, 39, 40, 41

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o Support FDD-LTE band 1, 2, 3, 4, 5, 6,7, 8, 12, 13, 17, 18,19, 20, 25, 26, 28, 29 (DL only), 66
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 General
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o -40°C to +85°C operation

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o Built-in temperature sensor

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o Built-in 32k Hz clock

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2 Operation Condition
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2.1 Absolute Maximum Ratings
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Attention: Absolute maximum ratings may cause permanent damage! These are stress ratings only
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and functional operation at these conditions is not implied. Exposure to maximum rating conditions for
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extended periods may reduce device reliability. The device is not guaranteed to be functional within these
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absolute maximum ranges.
Table 1: Absolute Maximum Ratings
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Parameter Minimum Typical Maximum Units Test Condition
Operating Ambient Temperature -40 25 85 °C
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Operating Junction Temperature -40 34 104 °C
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Storage Temperature -50 ti 125 °C
Total Power Dissipation - 475 mW
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Input Voltage Range (any pin) GND VDD V

ESD (HBM) 1000 - V
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2.2 Recommended Operating Condition

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Table 2: Power Supplies
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VDD1V8TX 1.75 1.8 2.15 V

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VDD1V8XO 1.75 1.8 2.15 V

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VDD1V8RX 1.75 1.8 2.15 V

VDD1V8IO 1.75 1.8 2.15 V
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VDD1V2RX 1.20 1.25 1.30 V

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VDD1V2TX 1.20 1.25 1.30 V

VDD1V1DIG 1.05 1.10 1.30 V
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3 RX Port Specifications
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3.1 Overview
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There are total 22 single-ended receive ports, grouped into 12 primary ports and
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10diversity ports. There are four bands, LB, MB, HB ports. Table 3 and Table 4 list
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corresponding ports and their operating ranges.
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Table 3: Primary RX Ports
Supported Modes Pin Name Freq Min Freq Max Units
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PRX_H1 2300 2690 MHz
PRX_H2 2300 2690 MHz
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PRX_H3 2300 2690 MHz
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PRX_H4 2300 2690 MHz
PRX_M1 1805 2170 MHz
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WCDMA PRX_M2 1805 2170 MHz

TD-SCDMA
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PRX_M3 1805 2170 MHz

FDD-LTE
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TDD-LTE PRX_M4 1805 2170 MHz

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PRX_L1 699 960 MHz
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PRX_L2 699 960 MHz
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PRX_L3 699 960 MHz
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PRX_L4 699 960

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Table 4: Diversity RX Ports

Supported Modes Pin Name Freq Min Freq Max Units
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DRX_H1 2300 2690 MHz

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DRX_H2 2300 2690 MHz

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DRX_H3 2300 2690 MHz
DRX_H4 2300 2690 MHz

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WCDMA DRX_M1 1805 2170 MHz

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FDD-LTE DRX_M1 1805 2170 MHz
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TDD-LTE
DRX_M3 1805 2170 MHz
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DRX_L1 699 960 MHz
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DRX_L2 699 960 MHz te

DRX_L3 699 960 MHz
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NOTE: Package is subject to change, please contact UNISOC for the latest ball map to confirm Ball location.
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3.2 AC Specifications
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3.2.1 GSM RX RF
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Table 5: AC Specifications - GSM RX RF
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Cascaded noise figure (25°C)
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GSM LB - 2.4 - dB Co-band with WCDMA
GSM HB - 2.4 - dB ports
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Cascaded voltage gain –
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Maximum
GSM LB - 79 - dB
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GSM HB - 77 - dB
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AGC gain range
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GSM LB - 68 - dB Set point -5dBm.
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GSM HB - 66 - dB
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Input P1dB
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GSM LB - -40 - dBm @ 600kHz offset,

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GSM HB - -40 - dBm RX gain word = x4366
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In-Band Input IP3
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Two tones at 800kHz and
GSM LB -12 dBm
1.64MHz offset at -43dBm
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GSM HB -18 dBm

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In-Band Input IP2

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Two tones at 6MHz and

GSM LB 40 - - dBm
6.1MHz offset at -31dBm
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GSM HB 40 - - dBm
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Image rejection - 40 - dB
Maximum Input Power Level - - -15 dBm
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DC offset -150 - 150 mV

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LO leakage - -85 - dBm

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3.2.2 WCDMA RX RF
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Table 6: AC Specifications - WCDMA RX RF
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WCDMA LB - 2.4 - dB
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WCDMA HB - 2.4 - dB
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Maximum
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WCDMA LB - 78 - dB
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WCDMA HB - 78 - dB
AGC gain range
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WCDMA LB - 69 dB
WCDMA HB -
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In-Band Input IP3
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Two tones at 10MHz offset at -

WCDMA LB - -14 - dBm
44dBm
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WCDMA HB - -18 - dBm

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Out-of-Band Input IP3
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Two tones at frx-fdpx_spacing at -
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WCDMA LB -12 - dBm
37dBm
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WCDMA HB - -13 - dBm
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Two tones at ftx-0.5MHz and

WCDMA LB - 50 - dBm
ftx+0.5MHz at -31dBm
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WCDMA HB - 52 - dBm
Receive EVM
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equalization of analog bbf

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WCDMA LB - 2.0 - %
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PMA Gain=xA using Data

Gaintable
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WCDMA HB - 2.0 - %
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DC offset -150 - +150 mV

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LO leakage -85 dBm
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3.2.3 TD-SCDMA RX RF
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Table 7: AC Specification - TDSCDMA RX RF
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TD-SCDMA HB - 2.4 - dB
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Maximum
TD-SCDMA HB - 81 - dB
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AGC gain range
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TD-SCDMA HB - 72 - dB
In-Band Input IP3
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Two tones at 3.2MHz and 6.1MHz
TD-SCDMA HB - ti -18 - dBm
offset at -48dBm
In-Band Input IP2
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Two tones at 4.6MHz and 4.9 MHz

TD-SCDMA HB - 30 - dBm
offset at -44dBm (No AGC)
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Receive EVM
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equalization of analog bbf

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TD-SCDMA HB - 3.5 - %
assumed
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LO leakage -85 dBm

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3.2.4 LTE RX RF
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Table 8: AC Specifications - LTE RX RF
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LTE LB - 2.4 - dB LTE 5MHz
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LTE HB - 2.4 - dB
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Maximum
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LTE LB - 78 - dB LTE 5MHz
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LTE HB - 78 - dB
AGC gain range
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LTE LB - 71 - dB Set point -7dBm
LTE HB -
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In-Band Input IP3
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- - Two tones at BW specific offset at

LTE LB (5MHz) -15 dBm
-48dBm
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LTE LB (20MHz) - -15 - dBm

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LTE HB (5MHz) - -18 - dBm
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LTE HB (20MHz) - -20 - dBm
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Two tones at frx-fdpx_spacing at -
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LTE LB - -8 - dBm 35dBm and frx-BW specific offset

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at -55dBm
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LTE HB - -8 - dBm
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LTE LB (5MHz) 50 dBm
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LTE LB (20MHz) 50 dBm

LTE HB (5MHz) 50 dBm
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LTE HB (20MHz) 50 dBm

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Receive EVM
LTE LB (5MHz) - 2.0 - % equalization of analog bbf assume
en
LTE LB (20MHz) 2.0

id
LTE HB (5MHz) - 2.2 - % RF Input power -30dBm.

nf
LTE HB (20MHz) 2.2
rw
Co
Image rejection - 40 - dB te
Maximum input power level - - -15 dBm
oc

wa
is
LO leakage - -85 - dBm

r
Un
Fo
l
ia
nt
16
de
fi
on
w
r
Fo
al
4 TX Port Specifications
ti
ld
There are 6 single-ended transmit ports, which are grouped in two ranges of operation,
en
or
2 low band (LB) ports, 4 high band ports (HB) .Each LB port, TX_L1 and TX_L2,
id
supports frequency ranges from 699MHz to 915MHz, and Each HB port, TXA_H1 to
rw
TX_H4, supports frequency range from 1710MHz to 2690MHz. Table 9lists all operating
nf
te
range for each TX port. Each of ports is internally matched to 50Ω.
Co
wa
Table 9: TXA Ports
Port Usage Pin Name Freq Min Freq Max Units Ball Location
c
r
Fo
GSM/GPRS/EDGE TX_L1 699 915 MHz
WCDMA
TX_L2 699 915 MHz
FDD-LTE
l
TX_H1 1710 2690 MHz
a
GSM/GPRS/EDGE
WCDMA ti
TX_H2 1710 2690 MHz
TDSCDMA
TX_H3 1710 2690 MHz
n
FDD-LTE
de
TDD-LTE TX_H4 1710 2690 MHz

i
nf
Co
d
rl
oc
o
rw
is
te
Un
wa
r
Fo
al
ti
en
id
nf
rw
Co
te
oc
wa
is
r
Un
Fo
l
ia
nt
17
de
fi
on
w
r
Fo
al
4.1 GSM TX RF OUTPUT
ti
ld
GSM output can only be with TXA ports
en
or
Table 10: AC Specifications - GSM TX RF
id
rw
nf
te
Maximum output power
10 / 9 dBm
Co
GSM LB/HB
wa
8PSK LB/HB 3.5 / 3.5 dBm
c
r
Minimum output power
Fo
GSM LB/HB - 1 -2 dBm
8PSK LB/HB - -33 -40 dBm
l
Gain Range
a
GSM LB/HB
ti
6 - - dB
42 - - dB
n
8PSK LB/HB
de
Power variation over -1.5 - 1.5 dB

process/frequency
i
Output load - 50 - Ω
nf
Co
d
4.2 GSM TX MODULATED
rl
oc
o
Table 11: AC Specification - GSM TX Modulated
rw
is

te
Un
RMS phase error (Max RMS)

wa
GSM LB - 1 2 °rms
GSM HB - 1 2 °rms
r
Peak phase error (Max peak)

Fo
GSM LB - 3 4 °pk
GSM HB - 4 8 °pk
al
RMS EVM
ti
8PSK LB - 1.5 3 % High Power

en
8PSK HB - 1.5 3 % High Power

id
Image Rejection
GSM LB/HB - -46 / -44 - dB High Power
nf
Spectrum Mask
rw
Co
GSM LB/HB - -69 / -67 - dBc ±400KHz

te
GSM LB/HB - -80 / -75 - dBc ±600KHz
oc
wa
8PSK LB/HB - -70 / -67 - dBc ±400KHz

is
8PSK LB/HB - -74 / -72 - dBc ±600KHz

r
Un
Output harmonics (2nd,3rd)

Fo
GSM LB/HB - - -20 dBm 2xFc 2xFc

GSM LB/HB - - -20 dBm 3xFc 3xFc
l
ia
nt
18
de
fi
on
w
r
Fo
al
4.3 WCDMA TX RF OUTPUT
ti
ld
Table 12: AC Specifications - WCDMA TX RF
en
or
id
rw
maximum output power
nf
WCDMA LB
te
WCDMA LB 6.3/5.7
- dBm 40dBc /43dBc ACLR
Co
wa
5.3/4.5
WCDMA HB
WCDMA HB
c
minimum output power
r
Fo
WCDMA LB/HB - -67 -78 dBm
Gain Range
l
WCDMA LB/HB 95 90 - dB
a
Power variation over
process/frequency
ti
-2 - 2 dB
Ω
n
Output load - 50 -
i de
nf
Co
d
rl
oc
o
rw
is
te
Un
wa
r
Fo
al
ti
en
id
nf
rw
Co
te
oc
wa
is
r
Un
Fo
l
ia
nt
19
de
fi
on
w
r
Fo
al
4.4 WCDMA TX MODULATED
ti
ld
Table 13: AC Specifications - WCDMA TX Modulated
en
or
id
rw
RMS EVM
nf
1.4
te
WCDMA LB/HB 0dBm - 4 %
WCDMA LBHB Max Pout 1.7
Co
wa
4.5
WCDMA LB Min Pout - 14 %
WCDMA HB Min Pout 5.5
c
r
Fo
ACLR
WCDMA LB 39 43 - dB ACLR 5M at 5dBm
l
WCDMA LB 57 67 - dB ACLR 10M at 5dBm
a
ti
WCDMA HB 39 40 - dB ACLR 5M at 5dBm
n
de
WCDMA HB 57 62 - dB ACLR 10M at 5dBm

i
Image Rejection
nf
WCDMA LB/HB - -47 - dB

Co
Spectrum Mask
d
- -46 - dBc/30kHz ±2.515MHz
rl
WCDMA LB
oc
WCDMA LB - -45 - dBc/30kHz ±3.485MHz
o
rw
- -44 - dBc/1MHz ±4MHz
is
WCDMA LB
WCDMA LB - -63 - dBc/1MHz ±12MHz
te
Un
Spectrum Mask
wa
WCDMA HB - -42 - dBc/30kHz ±2.515MHz
WCDMA HB - -41 - dBc/30kHz ±3.485MHz

r
Fo
WCDMA HB - -48 - dBc/1MHz ±4MHz
WCDMA HB - --68 - dBc/1MHz ±12MHz

al
nd rd
Output harmonics (2 ,3 )
- -39 - dBm
ti
WCDMA LB 2xFc 2xFc

WCDMA LB - -65 - dBm 3xFc 3xFc
en
nd rd
id
WCDMA HB - -46 - dBm 2xFc 2xFc

nf
WCDMA HB - -67 - dBm 3xFc 3xFc
rw
-156 dBm/Hz
Co
RX Band Noise at B1
-151 dBm/Hz
te
RX Band Noise at B2
oc
RX Band Noise at B5 -154 dBm/Hz

wa
-153 dBm/Hz
is
RX Band Noise at B8
r
Un
Fo
l
ia
nt
20
de
fi
on
w
r
Fo
al
4.5 TD-SCDMA TX RF OUTPUT
ti
ld
en
or
Table 14: AC Specifications - TDSCDMA TX RF
id
rw
nf
te
- 2.5 - dBm
Co
TD-SCDMA HB
wa
c
- -72 -74 dBm
r
TD-SCDMA HB
Fo
Gain Range
TD-SCDMA HB 75 - - dB
l
Power variation over -2 2 dB
a
process/frequency ti
Power variation over temperature -1.5 1.5 dB
n
i de
nf
Co
d
rl
oc
o
rw
is
te
Un
wa
r
Fo
al
ti
en
id
nf
rw
Co
te
oc
wa
is
r
Un
Fo
l
ia
nt
21
de
fi
on
w
r
Fo
al
4.6 TD-SCDMA TX MODULATED
ti
ld
Table 15: AC Specifications - TDSCDMA TX Modulated
en
or
id
rw
RMS EVM
nf
- 2.5 3 % High Power
te
TD-SCDMA HB
- 8 14 % Typical min power
Co
TD-SCDMA HB
wa
ACLR
- 44 - dB ACLR 1.6M
c
TD-SCDMA HB
r
Fo
TD-SCDMA HB - 66 - dB ACLR 3.2M
Image Rejection
l
TD-SCDMA HB -38 dB
a
Spectrum Mask ti
TD-SCDMA HB - - -45 dBc/30kHz ±0.815MHz
n
de
TD-SCDMA HB - - -59 dBc/30kHz ±1.815MHz

- - -54 dBc/1MHz ±2.9MHz
i
TD-SCDMA HB
nf

Co
TD-SCDMA HB - - -20 dBm 2xFc 2xFc
d
- - -20 dBm
rl
TD-SCDMA HB 3xFc 3xFc
oc
o
rw
is
4.7 LTE TX RF OUTPUT

te
Un
Table 16: AC Specifications - LTE TX RF

wa

r

Fo
LTE LB 4.0 - dBm

al
LTE HB - 5.5 - dBm

ti

- -79 - dBm <5% EVM
en
LTE LB
id
LTE HB - -75 - dBm <5% EVM

nf
Gain Range
rw
Co
LTE LB - 83 - dB te
Gain Range
oc
- 80 - dB
wa
LTE HB
is
Power variation over -2 - 2 dB

process/frequency
r
Un
Power variation over temperature -1.5 - 1.5 dB

Fo
l
ia
nt
22
de
fi
on
w
r
Fo
al
4.8 LTE TX MODULATED
ti
ld
Table 17: AC Specifications - LTE TX Modulated
en
or
id
rw
RMS EVM
nf
- 2.4 - % High Power (ACLR=-37dBc)
te
LTE LB
- 0.7 - % Mid Power (-5dBm)
Co
LTE LB
wa
RMS EVM
- 2.7 - % High Power (ACRL=-37dBc)
c
LTE HB
r
Fo
LTE HB - 1.3 - % Mid Power (-5dBm)
ACLR
l
LTE LB/HB 37 40 - dB ACLR EUTRA
a
LTE LB/HB 40 ti 43 - dB ACLR UTRA Near
LTE LB/HB 43 46 - dB ACLR UTRA Far

n
de
Image Rejection
-40 dB
i
LTE LB/HB
nf
Spectrum Mask
Co
LTE LB/HB - - -102.8 dBc/Hz Near offset (BW dependent)
d
- - -122.0 dBc/Hz Far offset (BW dependent)
rl
LTE LB/HB
oc
o
rw
- - -20 dBm
is
LTE LB 2xFc 2xFc

- - -13 dBm
te
LTE LB 3xFc 3xFc
Un
nd rd
wa
LTE HB - - -20 dBm 2xFc 2xFc

LTE HB - - -20 dBm 3xFc 3xFc
r
Fo
RX Band Noise - -153 - dBm/Hz

al
ti
en
id
nf
rw
Co
te
oc
wa
is
r
Un
Fo
l
ia
nt
23
de
fi
on
w
r
Fo
al
5 Clock Specification
ti
ld
Reference clock XO module in SR3595Dis used to provide 26MHz reference clock to RF internal
en
or
circuitries and three 26MHz reference clocks to peripheral. It also generates 32KHz clock output.
id
rw
5.1 Block Diagram
nf
te
Co
wa
c
r
Fo
a l
n ti
i de
nf
Co
d
rl
oc
o
rw
Figure 2: XO Block Diagram
is
te
Un
5.2 XO Input
wa
Table 18: Clock Specifications - XO Input (TCXO)

TCXO Reference Configuration (XO P port)
r
Fo
Input coupling requirement AC
Input impedance
al
crystal mode
130k kΩ
ti
Resistivity Measure at XO_p and

XO_n are grounded
en
crystal mode
id
Reactive 17.4 pF Measure at XO_p and

XO_n are grounded
nf
External drive mode

kΩ
rw
44.8 Measure at XO_p and
Co
Resistivity
XO_n are grounded
te
External drive mode
oc
18.68 pF
wa
Reactive Measure at XO_p and

is
XO_n are grounded

650 1000 mVpp
r
Un
Input voltage swing

Fo
Input duty cycle 40 50 60 %
Phase noise
l
-132 -129 dBc/Hz

ia
1kHz offset
nt
24
de
fi
on
w
r
Fo
al
Table 19: Clock Specifications - XO Input (DCXO)
ti
ld
en
With crystal observed with
or
Input Voltage Swing 1pF probe
id
rw
1.2 1.7 Vpp
XO P - XO level =5
nf
te
XO N 1.2 1.7 Vpp
Co
wa
c
r
Coarse Tune Capacitor step size
Fo
XOCbulk=0 0.275
0x44[4:0]=00000
0x44[4:0]=00001 :
:
l
0x44[4:0]=11111 8.525 pF
a
XOCbulk=1 ti
0x44[4:0]=00000
0x44[4:0]=00001 4.4
n
:
de
0x44[4:0]=11111 4.675
:
i
nf
12.925
Co
Reference Crystal Requirements (XO P and XO N ports)
d
rl
Frequency tolerance -10 0 10 ppm
oc
-10 0 10 ppm
o
Temperature stability
rw
is
Aging -1 0 1
te ppm/year
14 25 - ppm/pF
Un
Pulling sensitivity
Load capacitance (CL) 6 8 10 pF
wa
Motional series resistance (RS) - 20 60 Ω

r
Fo
al
ti
en
id
nf
rw
Co
te
oc
wa
is
r
Un
Fo
l
ia
nt
25
de
fi
on
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Fo
al
5.4 Reference Clock Output (REFOUT)
ti
ld
Table 20: Clock Specifications - REFOUT1/2/3
en
or
id
rw
Reference frequency - 26 - MHz
nf
Determined by XO input
te
Frequency compensation range - - - ppm
clock
Co
wa
Determined by XO coarse
Frequency compensation resolution - - - ppm/LSB
tune range
c
r
Output duty cycle 40 - 60 %
Fo
0.65*VppX 0.75*VppX
Output Voltage Swing (SINE wave) 1 Vpp
O_p O_p
l
-123
Phase Noise
a
1kHz Offset ti -133 dBc/Hz
10kHz Offset
200kHz Offset -138
n
de
Clock Jitter
Standard deviation 20 psec RMS
i
nf
Drive capacity - 10 - pF
Including XO and Buffer
Co
- - 3 msec
d
Power-up settling time settling time
rl
oc
o
rw
is
5.5 Power Detector te

Un
Table 21: AC Specifications - Power Detector

wa
Input Frequency Range 699 - 2690 MHz

r
-15 - +3 dBm
Fo
Input Power Range

Absolute Accuracy -0.25 - +0.25 dB
al
ti
en
id
nf
rw
Co
te
oc
wa
is
r
Un
Fo
l
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nt
26
de
fi
on
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Fo
al
6 Power Supply Sequencing
ti
ld
en
6.1 Overview
or
id
There are total of four supplies for the RFIC, proper sequencing of the power supply is required for the
rw
normal function of the device. VDD1V8 maybe shared with Connectivity; 1.1V maybe shared with
nf
te
memory.
Co
wa
VDD1V1DIG VDD1V2RF VDD1V8RF VDD1V8XO
c
r
Fo
1.1V Supply 1.5V LDOs
l
1.1V LDO XO
Detection (x3)
a
ti
1.2VLDOs 1.2V LDOs
n
DIGITAL
(x3) (x10)
i de
1.8V devices
nf
Co
Figure 3: SR3595D Supply diagram
d
rl
oc
6.2 Digital (1.1V) supply
o
rw
is
6.2.1 Internal Supply Mode

te
Un
If VDD1V2RF supply turns on before the VDD1V1DIG, the internal LDO will be activated.
wa
The 1.1V LDO will remain on even if VDD1V1DIG is turned on. The 1.1V LDO can be disabled by writing
to the SPI.
r
Fo
VDD1V2RF
al
ti
1.1V LDO
1.1V Supply
en
[ENABLED]
Detection
id
1.2VLDOs
nf
DIGITAL
(x3)
rw
Co
Figure 4: internal Supply for Digital

te
oc
6.2.2 External Supply mode

wa
is
The 1.1V is supplied externally and the supply detection will disable the internal 1.1V LDO. The
VDD1V2RF can be turned ON and OFF as long as 1.1V supply remains ON.
r
Un
Fo
The 1.1V must be on before VDD1V5RF.

TVDD1V1DIG_ON<TVDD1V5RF_ON+5uS
l
ia
nt
27
de
fi
on
w
r
Fo
al
ti VDD1V1DIG VDD1V2RF
ld
en
or
id
rw
1.1V LDO
nf
1.1V Supply
te
[DISABLED]
Detection
Co
wa
1.2VLDOs
DIGITAL
c
r
(x3)
Fo
Figure 5: External Supply for Digital
a l
ti
6.3 Valid supply sequences
n
de
VDD1V1DIG and VDD1V8XO can’t be brought up at the same time. The two supplies need to be
i
nf
brought up one after another. The following sequences are both valid.
Co
d
rl
oc
o
rw
is
Valid sequence #1 Valid sequence #2

te
Un
wa
VDD1V1DIG VDD1V1DIG
r
Vpor_start_max Vpor_start_max
Fo
Vpor_start_min Vpor_start_min
τ τ
al
VDD1V8XO VDD1V8XO
ti
Vpor_start_max Vpor_start_max
Vpor_start_min Vpor_start_min
en
id
Figure 6: Valid supply sequences

nf
rw
Co
Sequence #1:
te
oc
1. VDD1V8XO is brought up T=5µs prior to the VDD1V1DIG, satisfying requirement in Table 22.
wa
is
Sequence #2:
r
Un
Fo
1. VDD1V8XO is brought up T=5µs after the VDD1V1DIG, satisfying requirement in Table 22.
l
ia
nt
28
de
fi
on
w
r
Fo
al
Table 22: Terms and Definitions
ti
ld
Item Description Minimum value
en
Voltage above which SPI is guaranteed to be defined (over many
or
Vspi,valid: parts, over corners): 0.75V
0.75V
id
rw
Minimum Voltage above which the digital POR pulse timing COULD be
Vpor_start,min: started (over many parts, over corners): 0.4V.
0.4V
nf
te
Minimum Voltage above which the digital POR pulse is
Vpor_start,max: 0.9V
Co
wa
GUARANTEED to be started (over all parts, over corners): 0.9V
T Minimum time required ≥5µs

c
r
Fo
a l
n ti
i de
nf
Co
d
rl
oc
o
rw
is
te
Un
wa
r
Fo
al
ti
en
id
nf
rw
Co
te
oc
wa
is
r
Un
Fo
l
ia
nt
29
de
fi
on
w
r
Fo
al
7 Function Description
ti
ld
en
7.1 RCB Interface
or
id
The Radio Control Bus (RCB) is a 3-wire serial bus which accesses the device register set and configures
rw
SRAM. The baseband subsystem uses this control interface to initialize the device configuration, to
nf
te
change the mode of operation, and to adjust gain settings.
Co
wa
7.1.1 RCB Signal Description
c
DATA: The DATA signal carries the write control bit, the address bits, and the data bits. The write control
r
Fo
bit is set to 0 when writing to the device and set to 1 when reading from the device. The baseband
subsystem transmits the write bit first, followed by 15 address bits. 16 data bits follow the address bits.
a l
CLK: This signal is an input of the device, driven from the baseband subsystem. It is used to clock DATA
ti
into and out of the device. When writing to the device, DATA must be stable near the rising edge of CLK.
n
When reading from the device, DATA transitions on the rising edge of CLK And is stable on the falling
de
edge of CLK. CLK needs to be driven low on reset and should be held low when inactive.
i
nf
LE: The baseband subsystem uses signal LE to enable the RCB. LE needs to be low for DATA and CLK
Co
to be enabled. When signal LE is high, access to the device is inhibited.
d
rl
7.1.2 RCB Datagram
oc
o
rw
The datagram format is 32 bits. Bit 31 is always set as 0 for write operation and 1 for read. The next 15
is
bits (30 through 16) contain the register address information. The 16 LSBs (15 through 0) are the register
te
Un
data. Datagrams are sent from the baseband subsystem to the device with MSB first.
wa
r
Fo
al
ti
en
id
nf
rw
Co
te
oc
wa
is
r
Un
Fo
l
ia
nt
30
de
fi
on
w
r
Fo
al
SPI Port Read & Write Datagrams
ti
Word Structure
ld
 Read/Write Control Bit (MSB) Final Data Bit (LSB) 
en
or
R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
id
rw
nf
Read Operation
te
Externally Driven Internally Driven
Co
wa
(MSB) RW=1 A14 A13 A12 A11 A0 D15 D14 D0
DATA
c
r
X 31 30 29 28 27 16 15 14 0
Fo
CLK
l
LE
a
Write Operation
n ti
Externally Driven
de
(MSB) RW=0 A14 A13 A12 A11 A0 D15 D14 D0

DATA
i
nf
X 31 30 29 28 27 16 15 14 0
CLK
Co
d
rl
LE
oc
o
Multiple Read/Write:
rw
is
Multiple operations are possible keeping the 'LE' signal active low after bit D0 (clock cycle 0) and repeating the datagram
format.
te
Un
Notes:
Data is shifted into the registers on rising edge of the clock and shifted out of the falling edge of the clock.
wa
Data is shifted in and out MSB first.
Figure 7: RCB Datagram

r
Fo
al
ti
en
id
nf
rw
Co
te
oc
wa
is
r
Un
Fo
Figure 8: RCB configuration timing

l
ia
nt
31
de
fi
on
w
r
Fo
al
ti
ld
Table 23: RCB Configuration Timing
en
or
(TA = 25ºC, All VDD = 2.8V, unless otherwise noted)
id
Parameter Description Min Typ Max Unit
rw
nf
te
FCLK CLK Frequency 5 26 80 MHz
Co
wa
tDCRS DATA to CLK rising edge setup 5 ns
tDCRH DATA past CLK rising edge hold 5 ns
c
r
tCPH CLK pulse high 5 ns
Fo
tCPL CLK pulse low 5 ns
l
tCLH CLK low period before rising edge 5 ns
a
tLC LATCH to CLK setup
ti 5 ns
tLPH Latch pulse high 5 ns
n
tLCS LE rising edge past CLK rising edge 10 ns
i de
7.2 Data Interface

nf
Co
The SR3595D RF uses Digital I/Q interface to transfer data between RF and baseband. An ADC is
d
provided to convert analog transmit I/Q signals into a digital signal which can be used by the digital front
rl
end (DFE).
oc
o
rw
is
The ADC and DACs used in with the Digital I/Q interface are operated using clocks derived from the LO.
te
Un
Therefore, in order to use the Digital I/Q interface, the appropriate synthesizer for the selected receive or
transmit chain must be enabled and locked.
wa
7.3 Reference Clock

r
Fo
The XO clock contains coarse tune capacitor banks, three clock buffers for reference clock outputs, and
one fractional PLL to baseband 26MHz reference clock. Figure 2shows clock diagram.
al
The frequency of PLL clock output is adjusted by changing PLL’s frequency offset. It can be tuned to +/-
0.1ppm.
ti
The other three reference clocks are buffered outputs and they have the same clock accuracy as the
en
input and can be tuned using xo coarse tune capacitor bank.

id
nf
rw
Co
te
oc
wa
is
r
Un
Fo
l
ia
nt
32
de
fi
on
c
Co
nf
id
en
ti
Un al
Un is Fo
is oc r
oc Co w
8 Package Detail
Co nf
i
8.1 Package Dimension
nf de
id n
Figure 9:
en ti
ti a l
al
33
Fo
Fo r
r wa
wa te
Package Dimension
te rw
on rw or
fi orl ld
de d
nt
ia
l
Fo
r
wa
te
rw
w
r
Fo
al
8.2 Solder Ball Dimension
ti
ld
Table 24: Solder Ball Dimension
en
or
Parameter Size (um)
id
rw
Solder ball size 210
nf
200
te
Ball opening size
270
Co
Ball pad size
wa
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Figure 10: Solder Ball Dimension
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8.3 Reflow Profiles
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Figure 11: Classification Profile

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Table 25: Classification Reflow Profiles
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Figure 12: Ball Map

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8.5 Pin Description
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Table 26: Pin Description
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Sequence Name location Description Type
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1 DRX_M4 A1 Diversity Mid Band RX port 4 50 ohm RF
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2 DRX_H2 A3 Diversity High Band RX port 2 50 ohm RF
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3 DRX_H3 A5 Diversity High Band RX port 3 50 ohm RF
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4 PRX_H4 A15 Primary High Band RX port 4 50 ohm RF
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5 PRX_H2 A17 Primary High Band RX port2 50 ohm RF
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6 DRX_H1 B2 Diversity High Band RX port 1 50 ohm RF
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7 DRX_H4 B4 Diversity High Band RX port 4 50 ohm RF
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8 PRX_H3 B16 Primary High Band RX port 2 50 ohm RF

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9 PRX_H1 C17 Primary High Band RX port 1 50 ohm RF

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10 PRX_M4 D16 Primary Mid Band RX port 4 50 ohm RF

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11 DRX_M3 E1 Diversity Mid Band RX port 3 50 ohm RF
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12 PRX_M3 E17 Primary Mid Band RX port 3 50 ohm RF
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13 DRX_M2 F2 Diversity Mid Band RX port 2 50 ohm RF

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14 PRX_M2 F16 Primary Mid Band RX port 2 50 ohm RF

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15 DRX_M1 G1 Diversity Mid Band RX port 1 50 ohm RF

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16 PRX_M1 G17 Primary Mid Band RX port 1 50 ohm RF

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17 DRX_L3 H2 Diversity Low Band RX port 3 50 ohm RF

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18 PRX_L4 H16 Primary Low Band RX port 4 50 ohm RF

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19 DRX_L2 J1 Diversity Low Band RX port 2 50 ohm RF

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20 PRX_L3 J17 Primary Low Band RX port 3 50 ohm RF

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21 DRX_L1 K2 Diversity Low Band RX port 1 50 ohm RF

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22 PRX_L2 K16 Primary Low Band RX port 2 50 ohm RF
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23 PRX_L1 L17 Primary Low Band RX port 1 50 ohm RF

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24 TX_L1 T8 TX Low Band Port 1 50 ohm RF

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25 TX_H1 T12 TX High Band Port 1 50 ohm RF

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26 TX_H3 T16 TX High Band Port 3 50 ohm RF

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27 TX_L2 U7 TX Low Band Port 2 50 ohm RF

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28 TX_H2 U11 TX High Band Port 2 50 ohm RF

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29 TX_H4 U17 TX High Band Port 4 50 ohm RF
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30 CAP_TX M12 Decoupling cap for TX supplies Decouple
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31 SPIB_LE J13 SPI B Latch Enable Digital
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32 SPIB_CLK J15 SPI B Clock Digital
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33 SPIB_DATA K14 SPI B Data Digital
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34 SPIA_DATA L1 SPI A Data Digital
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35 SPIA_LE M2 SPI A Latch Enable Digital
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36 SPIA_CLK N1 SPI A Clock Digital
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37 BBA_DL_DN H4
n ti PCC Baseband RX signal for diversity (-) LVDS
38 BBA_DL_PP H6 PCC Baseband RX signal for Primary (+) LVDS
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39 BBB_DL_PP H10 SCC Baseband RX signal for Primary (+) LVDS

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40 BBB_DL_DN H12 SCC Baseband RX signal for diversity (-) LVDS

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41 BBA_DL_DP J5 PCC Baseband RX signal for diversity (+) LVDS
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42 BBA_DL_PN J7 PCC Baseband RX signal for Primary (-) LVDS
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43 BBB_UL_PP J9 SCC Baseband TX signal (+)

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44 BBB_DL_PN J11 SCC Baseband RX signal for Primary (-) LVDS

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45 BBA_UL_PP K4 PCC Baseband TX signal (+) LVDS

46 BBA_UL_PN K6 PCC Baseband TX signal (-) LVDS
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47 BBB_UL_PN K8 SCC Baseband TX signal (-) LVDS

48 BBB_DL_DP K12 SCC Baseband RX signal for diversity (+) LVDS
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49 NC A13 No connect NC
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50 NC B14 No connect NC
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51 NC C1 No connect NC
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52 NC D2 No connect NC
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53 NC L7 No connect NC te
54 NC L9 No connect NC
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55 NC N7 No connect NC
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56 NC N9 No connect NC
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57 NC R17 No connect NC
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58 NC T6 No connect NC
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59 NC U9 No connect NC
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62 PDET U5 TX Power Detector Pdet
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63 REFOUT2 P2 Reference clock output 2 Reference
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64 XO_N R1 Crystal Input N Reference
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65 REFOUT1 R3 Reference clock output 1 Reference
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66 CK32K R5 32K Output Reference
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67 REFOUT3 T2 Reference clock output 3 Reference
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68 CLK_26M T4
n ti BBPLL clock output 26MHz Reference
69 XO_P U1 Crystal Input P (TCXO Input) Reference
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70 VDD1V2RX D10 Supply 1.2V for RX Supply

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71 VDD1V8RX E9 Supply 1.8V for RX Supply

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72 VDD1V8IO M4 Supply 1.8V for IO Supply
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73 VDD1V1DIG M6 Supply 1.1V for Digital Supply
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74 VDD1V8TX N11 Supply 1.8V for TX te Supply

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75 VDD1V2TX P12 Supply 1.2V for TX Supply

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76 VDD1V8XO U3 Supply 1.8V for XO Supply

77 VSS A7 VSS ground VSS
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78 VSS A11 VSS ground VSS

79 VSS B6 VSS ground VSS
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82 VSS C3 VSS ground VSS

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84 VSS C7 VSS ground VSS te

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88 VSS D4 VSS ground VSS

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92 VSS E3 VSS ground VSS
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98 VSS F4 VSS ground VSS
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99 VSS F8
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103 VSS G3 VSS ground VSS
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105 VSS G13 VSS ground te VSS

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107 VSS J3 VSS ground VSS

108 VSS L11 VSS ground VSS
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109 VSS L15 VSS ground VSS

110 VSS M10 VSS ground VSS
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111 VSS N3 VSS ground VSS

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112 VSS P4 VSS ground VSS

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115 VSS P10 VSS ground VSS te

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117 VSS R7 VSS ground VSS

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Sequence
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VSS ground
VSS ground
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Description
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Type
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8.6 Part Numbering
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Part Number Part Description Package Type Operating Temperature
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SR3595D, Single Chip
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BGA-123 -40 to 85ºC
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SR3595D Multimode Multiband LTE-A Transceiver in CMOS
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9 Contact Information
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Headquarters
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UNISOC Center, Building No. 1
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Lane 2288, Zuchongzhi Rd., Shanghai 201203, P.R. China
Phone +86-21-5080-2727
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UNISOC USA Inc.
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San Diego, CA 92121, USA
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Phone: +1-858-546-0895
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Fax: +1-858-546-0896
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http://www.UNISOC.com
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© 2019, UNISOC, Inc. All Rights Reserved.
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Information in this document is provided in connection with UNISOC products. These materials are provided by UNISOC as a
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service to its customers and may be used for informational purposes only. UNISOC assumes no responsibility for errors or
omissions in these materials. UNISOC may make changes to specifications and product descriptions at any time, without notice.
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UNISOC makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to its specifications and product descriptions.
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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as
provided in UNISOC’ Terms and Conditions of Sale for such products, UNISOC assumes no liability whatsoever.
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THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED,
RELATING TO SALE AND/OR USE OF UNISOC PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO
en
FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR

INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNISOC FURTHER DOES
NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS
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CONTAINED WITHIN THESE MATERIALS. UNISOC SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY
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RESULT FROM THE USE OF THESE MATERIALS
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on

SR3595D Device Specification - V1.2

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SR3595D Device Specification - V1.2

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June 26, 2019

UNISOC, Inc., Confidential and Proprietary

Copyright © 2019, UNISOC Communications, Inc. All rights reserved.

UNISOC Communications, Inc. makes no representations or warranties, either express or implied, by or

shall not be disclosed to any third party.

3.2.4 LTE RX RF ............................................................................................................................ 16

4 TX Port Specifications ....................................................................................................................... 17

4.1 GSM TX RF OUTPUT .................................................................................................................... 18

4.3 WCDMA TX RF OUTPUT .............................................................................................................. 19

4.4 WCDMA TX MODULATED ............................................................................................................ 20

4.5 TD-SCDMA TX RF OUTPUT ......................................................................................................... 21

4.6 TD-SCDMA TX MODULATED ....................................................................................................... 22

4.8 LTE TX MODULATED ................................................................................................................... 23

5 Clock Specification ............................................................................................................................ 24

5.1 Block Diagram ................................................................................................................................ 24

5.2 XO Input ......................................................................................................................................... 24

5.4 Reference Clock Output (REFOUT) .............................................................................................. 26

6 Power Supply Sequencing ................................................................................................................ 27

6.1 Overview ........................................................................................................................................ 27

6.2 Digital (1.1V) supply ....................................................................................................................... 27

6.2.1 Internal Supply Mode ............................................................................................................ 27

6.2.2 External Supply mode ........................................................................................................... 27

6.3 Valid supply sequences ................................................................................................................. 28

7 Function Description ......................................................................................................................... 30

7.1.1 RCB Signal Description ......................................................................................................... 30

8 Package Detail .................................................................................................................................... 33

8.1 Package Dimension ....................................................................................................................... 33

FIGURE 5: EXTERNAL SUPPLY FOR DIGITAL .................................................................................................... 28

TABLE 5: AC SPECIFICATIONS - GSM RX RF ................................................................................................. 13

TABLE 17: AC SPECIFICATIONS - LTE TX MODULATED ................................................................................... 23

TABLE 19: CLOCK SPECIFICATIONS - XO INPUT (DCXO) ................................................................................. 25

TABLE 20: CLOCK SPECIFICATIONS - REFOUT1/2/3 ...................................................................................... 26

TABLE 24: SOLDER BALL DIMENSION.............................................................................................................. 34

TABLE 26: PIN DESCRIPTION .......................................................................................................................... 37

as TD-SCDMA operation. Implemented in low cost bulk CMOS, it is optimized to meet

and matched to 50Ω.

 Fully integrated single chip multi-mode, multi-band transceiver in bulk CMOS

 GSM/EDGE: GSM850, EGSM900, DCS1800, PCS 1900

 Single-ended LNAs in all receive bands and all modes of operation

 All TX outputs are single-ended and internally matched to 50Ω

 Ultra Low Power Consumption

 Build-in 32k Hz clock output

123balls BGA package

 4.5mm x 4.5mm ,0.35mm pitch

 Halogen Free (HF) Compliance

1 .8V RX VDD 1V 8RX

1 .25 V TX VDD 1V 2TX

1 BB _A DCOC 1 .8 V TX VDD 1V 8TX

DRX M 2 2 HMLB TX CAP TXCAP

PRX H 4 4 MIXER “C” BB _B

HB /MB PMA LPF ADC

PRX M 3 3 MUX HMLB

HB 1 TX MHB SPIB _LE

Figure 1: Block Diagram

o Digital I/Q interface

o Full HSDPA and HSUPA support

o Programmable channel filter

Digital I/Q interface

o Support TDD-LTE band 34, 38, 39, 40, 41

o Programmable channel filter

o Digital I/Q interface

o -40°C to +85°C operation