INTERNATIONAL ISLAMIC UNIVERSITY, ISLAMABAD

FACULTY OF ENGINEERING AND TECHNOLOGY

BS in ELCTRICAL ENGINEERING

Digital System Design LAB

Experiment No. 1: Introduction to HDL Based Designing

SUBMIITTED BY: KASHAF BAIG

REGISTRATION NO: 387/BSEE/FET/F-18
SUBMITTED TO: MAM SUMBAL
DATE: March 31, 2021

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 LAB TASK
Experiment a little bit with the interface of both IDEs and print the wave files generated and submit
with this manual in next lab.
STEPS OF SIMULATION
IN XILINX
STEP 1:
Open xilius. File/New/Folder. Create a new directory named Half_Adder.

Using File/Change Directory to change directory to Half_Adder.

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STEP 02:
Use Create New File two times to create two files
and choose Verilog as file type.

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STEP 03: Port selection

STEP 04:
Verilog Code:

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STEP 05:
IMPLEMENTATION CHECK

DESIGN SUMMARY :

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RTL SCHEMATIC:

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 SIMULATION IN XILINX ISE
STEP 01:
Open Xilinx ISE. Goto File/New Project. Create a new project named Half_Adder.
Choose HDL as top-level source type.

STEP 02:
In the next dialog box, change Simulator to VERILOG TEXT FIXTURE
(VHDL/Verilog). Don’t change anything else.

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STEP 03:
Add a new file named half_adder. (You may also use the existing file created in
last part).

STEP 04:

VERILOG TEST BENCH CODE:

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STEP 05:
Change Sources for (in the upper-left corner) from Implementation to Behavioral Simulation. In the
Processes tab, run Xilinx ISE Simulator/Behavioral Check Syntax. If any error occurs
check the file for errors.

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STEP 06:
SIMULATION

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 LAB WORKSHEET
QUESTION NO:01
What is HDL? Give its examples.
HDL :
Hardware description language (HDL) is a specialized computer
language used to program electronic and digital logic circuits.
EXAMPLE:
The examples include logical operations, counters of different moduli,
half adders, full adders, a carry lookahead adder, array multipliers,
different types of Moore and Mealy machines, and arithmetic logic
units (ALUs).

QUESTION NO:02

How many different design methodologies exist? Write their names.

There are two basic types:

1. Bottom-Up Design Flow
2. Top-Down Design Flow

QUESTION NO:03
What is the basic building block of Verilog? What are its components?
 Module is the basic building block in Verilog programming.
 Module definition always start with the keyword module, followed by module name,
port list, port declarations, parameters and ends with the keyword ‘endmodule’.

QUESTION NO:04
What is Stimulus module? Also write its function.
 Stimulus is the code written in HDL to test the design blocks.
 A stimulus is applied to the designed block and its functionality is tested by checking
the results.
 For writing a stimulus it is important to have the design specifications of the "design
under test" (DUT).

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