ISSN : 0976-8491 (Online) | ISSN : 2229-4333 (Print)
4, Issue 2, April - June 2013
Advanced Digital Signal Processing (ADSP) for Decreasing
Power Dissipation
1
Nandinii Alla, 2Suresh Badugu
1,2
Dept. of ECE, K L University, Vaddeswaram, Guntur, AP, India
Abstract
The design of the core of a fixed point general purpose Advanced
Digital Signal Processing (ADSP) processor and its instruction
set. This processor employs parallel processing techniques and
specialized addressing models to speed up the processing of
multimedia applications. The ADSP has a dual MAC structure
with one enhanced MAC that provides a SIMD, Single Instruction
Multiple Data, unit consisting of four parallel data paths that are
optimized for accelerating multimedia applications. The SIMD
unit performs four multimedia-oriented 16-bit operations every
clock cycle. This accelerates computationally intensive procedures
such as video and audio decoding. The ADSP uses a memory bank
of four memories to provide multiple accesses of source data each
clock cycle. Various techniques have been developed for reducing
the power consumption of VLSI designs, including voltage
scaling, switched-capacitance reduction, clock gating, power-
down techniques, threshold-voltage controlling, multiple supply
voltages, and dynamic voltage frequency scaling These low-power
techniques have been proven to be efficient at certain expense and
are applicable to multimedia/ Digital signal processing designs.
Among these low-power techniques, a promising direction for
significantly reducing power consumption is reducing the dynamic
power which dominates total power dissipation. This Proposed
paper can obviously decrease the switching (or dynamic) power
dissipation, which comprises a significant portion of the whole
power dissipation in integrated circuits.
Keywords
VLSI Design, Multimedia/ Digital Signal Processing, Power
Dissipation, SIMD
I. Introduction
Digital Signal Processing (DSP) is the mathematical manipulation
of an information signal to modify or improve it in some way. It
is characterized by the representation of discrete time, discrete
frequency, or other discrete domain signals by a sequence of
numbers or symbols and the processing of these signals. Digital
signal processing and analog signal processing are subfields of
signal processing. DSP includes subfields like: audio and speech
signal processing, sonar and radar signal processing, sensor array
processing, spectral estimation, statistical signal processing,
digital image processing, signal processing for communications,
control of systems, biomedical signal processing, seismic data
processing, etc.
The goal of DSP is usually to measure, filter and/or compress
continuous real-world analog signals. The first step is usually to
convert the signal from an analog to a digital form, by sampling and
then digitizing it using an Analog-To-Digital Converter (ADC),
which turns the analog signal into a stream of numbers. However,
often, the required output signal is another analog output signal,
which requires a Digital-To-Analog Converter (DAC). Even if
this process is more complex than analog processing and has
a discrete value range, the application of computational power
to digital signal processing allows for many advantages over
analog processing in many applications, such as error detection
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and correction in transmission as well as data compression.
DSP algorithms have long been run on standard computers, on
specialized processors called digital signal processor on purpose-
built hardware such as Application-Specific Integrated Circuit
(ASICs). Today there are additional technologies used for digital
signal processing including more powerful general purpose
microprocessors, Field-Programmable Gate Arrays (FPGAs),
digital signal controllers (mostly for industrial apps such as motor
control), and stream processors, among others.
A. Signal Sampling
With the increasing use of computers the usage of and need for
digital signal processing has increased. To use an analog signal on
a computer, it must be digitized with an analog-to-digital converter.
Sampling is usually carried out in two stages, discretization and
quantization. In the discretization stage, the space of signals is
partitioned into equivalence classes and quantization is carried
out by replacing the signal with representative signal of the
corresponding equivalence class. In the quantization stage the
representative signal values are approximated by values from a
finite set.
The Nyquist–Shannon sampling theorem states that a signal can be
exactly reconstructed from its samples if the sampling frequency is
greater than twice the highest frequency of the signal; but requires
an infinite number of samples. In practice, the sampling frequency
is often significantly more than twice that required by the signal’s
limited bandwidth.
Some (continuous-time) periodic signals become non-periodic
after sampling, and some non-periodic signals become periodic
after sampling. In general, for a periodic signal with period T to
be periodic (with period N) after sampling with sampling interval
Ts, the following must be satisfied:
where k is an integer.
B. DSP Domains
In DSP, engineers usually study digital signals in one of the
following domains: time domain (one-dimensional signals), spatial
domain (multidimensional signals), frequency domain, and wavelet
domains. They choose the domain in which to process a signal by
making an informed guess (or by trying different possibilities) as
to which domain best represents the essential characteristics of the
signal. A sequence of samples from a measuring device produces
a time or spatial domain representation, whereas a discrete Fourier
transform produces the frequency domain information, that is
the frequency spectrum. Autocorrelation is defined as the cross-
correlation of the signal with itself over varying intervals of time
or space.
C. Multimedia Processor
A Multimedia Processor is an application specific DSP processor
which performs a number of multimedia algorithms. The following
classes of DSP algorithms might be referred to as multimedia
types:
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• Speech coding and decoding
• Speech recognition
• Speech identification
• High-fidelity audio encoding and decoding
• Modem algorithms
• Audio mixing and editing
• Voice synthesis
• Image compression and decompression
• Image compositing
A general purpose Advanced DSP (ADSP) processor should, of
course, cover all of the above. Naturally, no processor can meet
the needs of all or even the most of the applications, and that is
why it’s a designer’s task to find the optimal trade-off between
functional covering and performance, cost, integration, power
consumption, and other factors.
II. The Processor Design Flow
The design flow of any DSP processor, as well as some certain
explanations especially for the designed one. The schematic of
the design flow is shown in fig. 1:
Fig. 1: The DSP Processor Design Flow
III. A Top-Level Data Path Architecture Design
According to the design specification we have designed a
Advanced DSP processor (ADSP). This is a DSP processor that
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ISSN : 0976-8491 (Online) | ISSN : 2229-4333 (Print)
has special architecture and hardware features to accelerate the
media applications. The data have a fixed-point representation.
The general structure of the processor is a Harvard’s one, with
different memories for programs and for data. There are several
architectural DSP features. Most of the DSP applications require
high performance in repetitive computation and data intensive
tasks. The research is aimed for designing of an efficient
architecture, for the general purpose multimedia processor, and
is concentrated on:
• Fast Multiply-Accumulate (MAC) operations (the most
DSP algorithms, including filtering and transforms, are
multiplication-intensive).
• Multiple memory access architecture (this property might
be very efficient in cases where the operations could be
accelerated by reading multiple data items at the same
instruction cycle).
• Specialized address models (efficient data managing and
special data types in the DSP applications).
• The designers should not forget about an efficient Control
Path and of the input/output organization. In this work we
did not concentrate on them.
We have stopped at the dual MAC (DMAC) architecture. The top-
level datapath architecture is shown in fig. 3.1. First, each MAC
had the same structure. It operates with data from the memory
and from the Register File. The data length is 16 bits and the same
applies to the memory.
Fig. 2: A top-Level Data Path Architecture
Each parallel data path provides eight-by-eight bit multiplication
and then provides a 20-bit accumulation. The hardware structure
of the parallel and the serial data paths are the same. The only
difference is the computational bit length and the extra hardware
for performing special instructions like PSAD and PDOT. Each
parallel data path has a final 20-bit result and each serial data path
has a 40-bit result. These bit lengths have been got by adding
the guard bits to a native length result to prevent overflow errors
during the hardware loops. For the large loops, and according to
general purpose preference of this ADSP processor, we found that
four guard bits for the final result in the parallel data paths, and
eight guard bits for the serial ones are enough.
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A. Pipeline Structure
There are several strategies in the pipeline design. The main
tricky place is the number of pipelining steps. According to
the designed hardware an instruction should be executed in the
following order:
• fetching of an instruction
• decoding of an instruction
• calculating a valid operands addresses
• performing operation (execution)
• writing the final result
We have divided the instruction execution job into six clock cycles,
see fig. 5. First we need to fetch instruction, decode it and calculate
the valid execution operand address (fetch operand). Next two
cycles are for executions of the operation. Finally, we are storing
data in a last step.

Fig. 5: Pipeline Principle

where:
Fig. 3: The Six Data Paths ADSP Structure FI . fetch instruction
DI . decode instruction
IV. Control Path FO . fetch operand
The simplified version of the Control Path is shown in figure 3.5 E1 . performing the 1-st operation
and contains the programmable Finite State Machine (FSM) or E2 . performing the 2-nd operation
the Program Flow Controller, Program memory, and Instruction ST . store the result
decoder.
The Program Flow Controller reads the flag registers and status B. Data Memory
signals from the processor. It manages the next PC address for According to the design specification all memories should be
program memory addressing according to the execution of the single port SRAM only. This gives the advantage of porting design
current instruction. The next instruction, pushes the current to different silicon processes.
instruction from the program memory to the instruction decoder. The size of the data memory addressing space should be large
The program memory is a 32-bit wide, 64kW large memory. enough for covering all functional purposes. Four 16-bit different
data accesses are supported in parallel. We have divided the
memory bank into four memories (M0, M1, M2, M3), see figure
3.10:

Fig. 6: Memory Structurea

V. Conclusion
The proposed Digital Signal Processor can obviously decrease
the switching (or dynamic) power dissipation, which comprises
a significant portion of the whole power dissipation in integrated
circuits. The designed processor should show good performance
Fig. 4: Control Path Structure for 8/16-bit convolution based algorithms. The motion estimation

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and compensation (MPEG) applications should also be solved very

well because of the architectural improvements made especially Nandinii Alla was born in   Guntur,
for them. The designed addressing models give the opportunity to Guntur Dt, Andhra Pradesh, India. She
process the multidimensional media algorithms with a high-level is pursuing B.Tech in ECE from K
of flexibility of the data accesses. L University, Vaddeswaram, Andhra
The high level of orthogonality of the instruction set and the Pradesh, India. Her Research interest
architecture gives the designers the possibility of using all available includes Digital Signal Processing.
6data paths simultaneously. In this way, six different results are
calculated at the same time, four loop results to the memories,
and two auxiliary register operations. The SIMD parallel data
paths can process 8-bit media data with a great performance for
non high-quality colour applications, up to five significant bits
per pixel. To process data with high-quality colours, programmers
should use the DMAC mode. The designed instruction set is quite Badugu Suresh did his B.Tech in ECE
flexible for future improvements and changes. from prakasam engineering college,
Kandukur in 2008 and M.Tech in
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