26th Iranian Conference on Electrical Engineering (ICEE2018)
Low-Power High -Gm Quadrature LC-VCO
Using Darlington Cell
Yasaman Majd
M.Sc. Graduated
Faculty of Electrical Engineering and Robotic
Shahrood University of Technology
Shahrood, Iran
Email: y_majd92@yahoo.com
Abstract—This paper presents a new low power and low phase-
noise quadrature voltage controlled oscillator (QVCO). The
proposed QVCO contains two cross-connected LC-VCOs with
Darlington cell. Using Darlington cells increases the
transconductance of the cross-connected pair and facilitates the
startup of oscillation with lower power consumption. Oscillators
are coupled to each other via the substrates of the Darlington cell's
transistors. No extra noisy elements are used for coupling the core
oscillators and consequently low phase noise quadrature signals
can be generated. The suggested topology was designed and
simulated in TSMC 180nm CMOS process. The simulation results
show that the proposed QVCO phase noise is -122.4 dBc/Hz at
1MHz offset from 5.37 GHz operation frequency. The total power
consumption of the QVCO is 6.1 mW at 1.8 V supply voltage and
the tuning range of this topology is 5.3-6.2 GHz.
Keywords: QVCO; Darlington cell; low power; high
transconductance.
I. INTRODUCTION
QVCOs have played prominent role in recent modern
communication systems. They have been utilized in different
range of applications, such as zero-IF receivers, image rejection
architectures, clock and data recovery (CDR), and QPSK
modulators.
Due to development of communication systems, QVCOs
with low-phase noise, low power, high accuracy and high
integration are required. For generating quadrature signals,
several methods have been proposed so far, like generating
quadrature signals with poly phase RC-CR filters [1]. Although
the advantage of this method is its simplicity, it suffers from
high noise and low accuracy [1].The other techniques like
master–slave flip–flops and ring oscillators are not appropriate
for using in high frequencies because of high phase noise and
high power dissipation [2]. An appropriate technique, which
has drawn lots of attention, is LC QVCOs. The LC QVCOs
have a better phase noise performance in high frequency bands
compared to the other structures. Generally, the LC-QVCOs are
comprised of two cores LC-VCOs and a coupling network.
Rofougaran [3] presented the first structure of two coupled
LC VCOs for generating quadrature signals. It was named
parallel coupled QVCO (P-QVCO) since the coupling
978-1-5386-4916-9/18/$31.00 ©2018 IEEE
Emad Ebrahimi
Assistant Professor
Faculty of Electrical Engineering and Robotic
Shahrood University of Technology
Shahrood, Iran
Email: eebrahimi@shahroodut.ac.ir
transistors are placed in parallel with the switching pairs. The
extra elements for coupling in PQVCO results in higher power
consumption and phase noise degradation [4,5].
Using current-reused technique can reduce the power
consumption [6]. As shown in Fig. 1 the NMOS cross-
connected pair shares the same bias current with PMOS pair
that is tied to it [7]. Therefore, this structure dissipates lower
DC power by reusing the DC current drawn from the supply
voltage. Due to use of two cross-connected pairs, this structure
introduces higher transconductance (Gm) at a given current.
However, the current-reused structure decreases the power
dissipation but the voltage headroom is limited by stacking of
transistors [4].The modified configuration of current-reused
QVCO has been presented in [8]. Unlike the VCO in [6], in this
circuit both NMOS and PMOS transistor are on and off at the
same time such that the overall current drawn from the supply
voltage is reduced [9]. According to [8], while this structure
does not suffer from the phase noise degradation caused by
second harmonics ,but it has imbalanced differential outputs [9].
Many other structures [10, 11] are presented to decrease the
power by increasing the negative transconductance (-Gm).
Another important point for improving the performance of a
QVCO is design of efficient coupling network. The noiseless
coupling network can decrease the phase noise of the circuit and
introduce no excess power consumption to the QVCO Using
substrates of MOS transistors is one of the main approach for
Fig. 1: The current reused topology
53
26th Iranian Conference on Electrical Engineering (ICEE2018)

low noise injection locking [12, 13]. The big advantages of

using the substrates for coupling network is elimination of any
extra coupling elements and their related noises.
This work exploits a Darlington cell, based on [14], to
enhance the transconductance of negative ‫ܩ‬௠ pairs in such a
way, the proposed QVCO can start up at a lower bias current
than traditional ones. Also the substrates are used for coupling
network due to elimination of noisy elements.
The paper is organized as follows. In section II, the
Darlington cell is presented and discussed. The proposed QVCO
architecture and its analysis are introduced in section III. Section
IV is the simulation results of the proposed QVCO and finally
the conclusion is in section V.
Fig. 2: (a) The Darlington cell and (b) small signal circuit of Darlington cell

II. THE DARLINGTON CELL

The Darlington cell, which is used in a mixer in [14], is
shown in Fig. 2(a). Transistors M1 and M2 are Darlington pair
and M3 (which is diode-connected) provides bias current. This
cell can be used instead of a single transistor in cross-connected
pairs and enhances the transconductance of the pairs at a given
DC current. In order to analyze the transconductance of the cell,
its equivalent small signal circuit is depicted in Fig. 2(b).
Applying KCL at output node, we have:

ios = g m1v gs1 + g m 2 v gs 2 (1)

Fig. 3: Transconductance of Darlington cell versus the transistor size ratio

v gs 2 can be defined in terms of v gs1 by (2):
( g m1 + sc gs1 )
v gs 2 =
gm 3 + s (c gs1 + c gs 3 )
and the input voltage vi can be written as (3):
vi = v gs1 + v gs 2
transconductance can be increased by properly sizing of M1 and
M2. For this simulation the length of transistors are same. Fig.
4 also shows the comparison between Gm of the Darlington cell
.v gs1 (2)
and that of conventional cross-connected pair for different bias
current. It could be figured out that at the same bias current, the
Darlington cell has a higher transconductance than the
conventional cross-connected cell. So using Darlington cell as
negative Gm in LC QVCOs can facilitate the oscillation at lower
(3) power consumption.

By replacing (2) and (3) in (1) the transconductance is achieved:

ios
Gm = (4)
vi

g m1 g m 2 + g m1 g m3 + s[ g m1 (c gs 2 + c gs 3 ) + g m 2 c gs1 ]
=
g m1 + g m3 + s (c gs1 + c gs 2 +c gs 3 )

Based on (4), the size of transistor M1 and M 2 can determine

the Gm. Therefore, the transconductance of cell would be
optimized by choosing proper size values for M1 and M 2 .
ௐ
In order to investigate the effect of భ on the overall
ௐమ
transconductance, Darlington Gm was simulated and calculated Fig 4: the comparison between the Darlington cell and simple ࡳ࢓
for different transistors' size. As shown in Fig. 3 Darlington cell

54
26th Iranian Conference on Electrical Engineering (ICEE2018)

III. STRUCTURE OF A PROPOSED QVCO

Schematic of the proposed QVCO is shown in Fig. 5. The
circuit consists of two identical cross-connected LC VCOs in
each of which the higher transconductance of Darlington cell is
replaced with conventional cross-connected pairs. In the
proposed circuit the bulk of Darlington transistor (M1,4,7,10) are
utilized for in-phase anti-phase injection and quadrature signal
generation.
As seen in this circuit no extra noisy elements are used for
coupling the two VCOs so both the phase noise and power
consumption could be improved. Besides, using Darlington cell
improve negative transconductance and start-up conditions of
the QVCO at lower power consumption.
Fig. 5: Schematic of proposed Darlington-based QVCO
A. Start-up Condition
According to [7], the start-up condition for simple cross-
connected LC oscillator is achieved from (5):

gm Rp >1 (5)

Which ܴ௣ represents loss of the LC tank. To find the start-up

condition for Darlington cell, the small signal impedance of the
VCO must be calculated. By neglecting the capacitances, the
impedance of VCO can be described as:

−( g m 1 + g m 3 )
Z in ≈ (6) Fig. 6: Comparison between the start-up current
( g m 1g m 2 + g m 1g m 3 )

By assuming g m 1 = g m 3 , Z in can be simplified as: The KCL for the node specified as the Q- can be written as

−2 iQ − =G m1 (vQ + − αvQ + ) + G m 2αvQ + + G b1 (v I − − α vQ + ) (9)

Z in ≈ (7)
(g m 2 + g m1 )
where ‫ܩ‬௕ଵ denotes the bulk's transconductance of M1 and ߙ can
To maintain oscillation, the negative resistance of the active be obtained from (10). Actually ߙ shows the gain through the
circuit should be higher than the passive element loss of the gate of M 1 to its source (zs is overall impedance connected to
resonator circuit:
source of M1).
gm2 g
Rp. (1 + m 1 ) > 1 (8) zs
2 gm2 α= (10)
1
+ zs
Gm1
So by changing the ratio of g m 1 and g m 2 , the start-up bias
current and negative G m can be improved. Fig. 6 shows the The voltage of Q- is expressed in (11):
current for simple cross-connected VCO and Darlington cell.
Compared with simple cross-connected VCO, the proposed vQ − = −iQ − .Z ( jω ) (11)
circuit has lower start-up current.
B. The Analysis of QVCO Where ܼሺ݆߱ሻ is the overall tank impedance Ǥ Due to the
To show that outputs of the proposed circuit at nodes I+ and differential behavior of the circuit, we have vQ − = −vQ + and
Q- in Fig.5 are in quadrature, a simple and linear analysis of the v I − = −v I + . Replacing the (9) into (11), Eq. (12) is obtained:
circuit operation is presented. The currents of one VCOs are
presented in Fig. 5 and the large signal transconductance of
each transistor considered as Gm Ǥ

55
26th Iranian Conference on Electrical Engineering (ICEE2018)

Gm2 The third factor depends on the parasitic capacitances. In fact,

v Q − = − Z ( j ω ).G m1 .( −[1 − α − α G b1 + ].v Q − the oscillation frequency of conventional cross connected
G m1
structure is obtained:
G b1
+ .v I − )
G m1 1
(12) ωos = (18)
L .CT
For simplicity, (12) can be rewritten as:
Where CT is equal to (19):
vQ − = − Z ( jω ).G m1 ( − m.vQ − + n.v I − ) (13)
CT = C 1 + C db 1 + C gs + 4C gd + C var (19)
Gm 2 G
in which m is 1 − α − αGb1 + and n is b1 .Due to the Where C1 denotes the parasitic capacitance of inductor plus the
Gm1 Gm1
symmetry, the parameters of the circuit are the same, i.e input capacitance of next stage and C var is varactors'
Gm1 = Gm10 , Gm2 = Gm11 and Gb1 = Gb10 , so the same capacitance. The CT for Darlington cell of Fig. 5 is described
derivation can be written for node I+ as follow: as follow:

v I + = − Z ( jω ).G m1 .( − m.v I + + nv Q − ) (14) 1

CT ≈ C var +C gs 4 +Cdb1 + 4C gd + (1 + )C gd 2 +C1 + Cdb 2 (20)
Av
By multiplying the both sides of (13) and (14) by vQ− and v I +
1
respectively, (15) and (16) can be derived as: The term (1 + ) shows the Miller's effect, which Av is the
Av
gain through the gate of ‫ܯ‬ଶ to source. Since M 2 ,5 ,9 ,11 size is
vQ2 − = − Z ( jω ).Gm1 .(−m.vQ2 − + n.v I − .vQ − )
(15) small, the parasitic capacitors of them are ignorable. Hence this
structure does not provide large parasitic capacitances and does
not decreases the maximum attainable oscillation frequency.
v I2+ = − Z ( jω ).Gm1.(−m.v I2+ + n.v I + .vQ − ) IV. SIMULATION RESULTS
(16)
The proposed quadrature LC-VCO is simulated in TSMC
0.18ȝm CMOS process by ADS with circuit parameters in
And sum of (15) and (16) results in (17): Table 1.
Fig. 7 shows the waveform of the proposed circuit in 5.37
(1 − Z ( jω ).Gm1 .m).(v I + ) 2 + GHz oscillation frequency that are quadrature. The VCO’s
(17) output frequency tuning range is depicted in Fig. 8. As seen in
(1 − Z ( jω ).Gm1 .m).(vQ − ) 2 = 0 → vQ − = ± j.v I + Fig. 8, the range of frequency tuning for this circuit can vary
from 4.6 to 5.3 GHz (%16.5) so this circuit has high tuning
Consequently, (17) shows that the vQ- and vI+ are in quadrature. range without using the capacitor bank. In this design, the
The same analysis as above shows that the other outputs are in PMOS transistors are adopted as the varactors that have a lower
quadrature too. flicker noise. Fig. 9 shows the simulated phase noise of this
work. The phase noise at 1 MHz offset is -122.4dBc/Hz while
C. Maximum Attainable Oscillation Frequency the carrier is 5.37 GHz.
According to [15], the maximum attainable frequency can
be affected by different factors three of which, are mentioned Table 1. The parameters of proposed structure
as follows; parameters values parameters values
1. Negative resistance cell
2. Buffer stage design (W / L ) M 1,4,7,10 8μm/0.18μm L 1 nH
3. Parasitic capacitance and tuning range
The first one depends on the transition frequency, which in turn (W / L ) M 2,5,9,11 0.5μm/0.18μm V DD 1.8 V
depends on ωT and considers the effect of gate resistance for
high frequencies. Therefore, the structure with higher ωT has (W / L ) M 3,6,8,12 8μm/0.18μm V tune 0.5 V

higher transition frequency. Reference [14] proved that ωT of

(W / L )V aractors 220μm/0.18μm C1−4 3 pF
Darlington cell is 1.5 larger than simple gm, that improves the
transition frequency.

56
26th Iranian Conference on Electrical Engineering (ICEE2018)

Fig. 7: Output waveforms of the proposed QVCO

Fig.10: The variation of ‫ܩ‬௠ with temperature.

The variations of ‫ܩ‬௠ with temperature results in center

frequency changes between 5.36-5.4 GHz.
Table 2 shows the performance of the proposed structure
and presents the results from previously published QVCOs. For
a more comprehensive comparison, a figure of merit (FOM) is
used [7] to normalize the performance of the circuit:

f
FOM = PN (Δf ) − 20Log ( osc ) + 10Log ( pQVCO ) (21)
Δf

Where PN(߂݂) is the phase noise at the offset frequency f osc

in dBc/Hz, f osc is the center frequency and p QVCO is the total
Fig. 8: The output frequency versus the control voltage of QVCO
power consumption.
V. CONCLUSION
A new QVCO structure based on Darlington cell has been
presented for low power and low phase noise applications.
Using the Darlington-cell instead of conventional cross-
connected pairs results higher Gm, better start-up condition and
lower power consumption. Analytic derivation and simulation
results show that the Darlington cell has a higher Gm than the
simple conventional transconductance.
In order to generate quadrature signals, two core VCOs were
coupled to each other via the bulk of the Darlington transistors.

Table 2. Comparison of the proposed circuit and other QVCO structures

CMOS Technology Frequency Power Phase FOM
Fig. 9: The phase noise of proposed circuit QVCO [ȝm] [GHz] [mW] noise [dBc]
[dBc/Hz]
In this circuit the transistors M 6 ,3 ,8 ,12 which provides the bias [16] 0.18 6.4 2 -117.7 -190.8
current, operate in saturation region and do not enter into triode fabricated [@1MHz]
region. While in conventional cross connected pairs [3], tail [17] 0.18 4.3 1.9 -116 -185.8
MOS enters into deep triode region and degrades the phase fabricated [@1MHz]
noise [4]. The power consumption is 6.12mW that means a 3.4 [18] 0.18 6.9 17 -120 -184.4
mA current is drawn from 1.8V power supply. Fig. 10 shows fabricated [@1MHz]
the variation of Darlington cell's transconductance versus [19] 0.18 5 9.7 -125 -189
simulated [@1MHz]
temperature. The temperature varies between -85cƕ to 90 cƕ.
This work 0.18 5.37 6.1 -122.4 -189.2
Compared with simple ‫ܩ‬௠ , Darlington cell is more sensitive to
simulated [@1MHz]
the temperature.

57
26th Iranian Conference on Electrical Engineering (ICEE2018)
Four coupling capacitors are also used to isolate the DC point
of bulks.
The proposed coupling method do not introduce extra noise
and power dissipation and also enhance –Gm to facilitate the
startup. Compared to conventional current-reused structures,
this structure has higher voltage headroom, whereas voltage
headroom decreases in comparison with simple cross coupled
VCO. This proposed structure has Simulation results of the
QVCO in TSMC 0.18um CMOS technology verify the good
performance of the circuit with FOM of -189.2dBc/H.
REFERENCES
[1] M. A. T. Sanduleanu and J. P. Frambach, “1GHz tuning range, low phase
noise, LC oscillator with replica biasing common-mode control and
quadrature outputs,” in Proc. ESSCIRC, 2001, pp. 506–509.
[2] C. Lin and C. Wang, “A 1-V 27mW 10-GHz LC-NOR-Ring QVCO for
UWB-OFDM Direct Frequency Synthesizer,” in Asian Solid-State
Circuits Conference, 2005, pp. 437–440.
[3] A. Rofougaran, J. Rael, M. Rofougaran, and A. Abidi, “A 900 MHz
CMOS LC-oscillator with quadrature outputs,” in IEEE Int. Solid states
Circuits Conference (ISSCC) Dig. Tech. Papers, 1996, pp. 392–393.
[4] O. Casha, I. Grech, and J. Micallef, “Comparative study of gigahertz
CMOS LC quadrature voltage-controlled oscillators with relevance to
phase noise,” Analog Integr. Circuits Signal Process, vol. 52, no. 1–2, pp.
1–14, 2007.
[5] L. Romanò, S. Levantino, A. Bonfanti, C. Samori, and A. L. Lacaita,
“Phase noise and accuracy in quadrature oscillators,” in proc. IEEE Int.
Symposion. Circuit Systems , 2004, pp. 10–13.
[6] Y.-C. Tsai, Y.-S. Shen, and C. F. Jou, “A low-power quadrature VCO
using current-reused technique and back-gate coupling,” in Proceedings
of PIERS, vol. 3, no. 7, pp. 971–975, 2007.
[7] B. Razavi, RF microelectronics (2nd Edition), New Jersey: Prentice Hall,
2011.
[8] S.-J. Yun, S.-B. Shin, H.-C. Choi, and S.-G. Lee, “A 1mW current-reuse
CMOS differential LC-VCO with low phase noise,” in IEEE ISSC Tech.
Dig, 2005, pp. 540–616.
[9] Ghorbel, F. Haddad, and W. Rahajandraibe, “Optimization of voltage-
controlled oscillator VCO using current-reuse technique,” in
Microelectronics (ICM), pp.212–215, 2014.
[10] J.-F. Huang, W.-C. Lai, and Y.-J. Lin, “Chip Design of 5.1~6 GHz
Colpitts QVCO for WIMAX,” in Control Engineering and
Communication Technology (ICCECT), 2012, pp. 715–718.
[11] K. W. Cheng and M. Je, “A current-switching and gm-enhanced colpitts
quadrature VCO,” IEEE Microw. Wirel. Components Lett, vol. 23, no. 3,
pp. 143–145, 2013.
[12] H.-R. Kim, C.-Y. Cha, S.-M. Oh, M.-S. Yang, and S.-G. Lee, “A very
low-power quadrature VCO with back-gate coupling,” IEEE J. Solid-
State Circuits, vol. 39, no. 6, pp. 952–955, 2004.
[13] E. Ebrahimi and S. Naseh, “A Colpitts CMOS quadrature VCO using
direct connection of substrates for coupling,” IEEE Trans. Very Large
Scale Integr. Syst, vol. 21, no. 3, pp. 571–574, 2013.
[14] K. C. Lin et al., “A 4.2-mW 6-dB gain 5-65-GHz gate-pumped down-
conversion mixer using darlington cell for 60-GHz CMOS receiver,”
IEEE Trans. Microw. Theory Tech, vol. 61, no. 4, pp. 1516–1522, 2013.
[15] B. Jung and R. Harjani, “/spl Sigma/High-frequency LC VCO design
using capacitive degeneration,” IEEE J. Solid-State Circuits, vol. 39, no.
12, pp. 2359–2370, 2004.
[16] H.-J. Chang, C. Lim, and T.-Y. Yun, “CMOS QVCO with current-reuse,
bottom-series coupling, and forward body biasing techniques,” IEEE
Microw. Wirel. Components Lett, vol. 24, no. 9, pp. 608–610, 2014.
[17] W.-C. Lai, S.-L. Jang, and S.-S. Su, “A 4.9 GHz low power QVCO using
injection locked techniques for wireless wearable applications,” in
Microsystems, Packaging, Assembly and Circuits Technology Conference
(IMPACT), 2016, pp. 266–269.
[18] T. Arai and A. Hajimiri, “A 7GHz wideband self-correcting quadrature
VCO,” in Electronics, Circuits and Systems (ICECS), 2012, pp. 61-64.
[19] M. J. Hemmati and S. Naseh, “A second-harmonic LC-quadrature voltage
controlled oscillator with direct connection of MOSFETs’ substrate,”
Analog Integr. Circuits Signal Process., vol. 70, no. 3, pp. 437–442, 2012
58