SƠ ĐỒ TRIGGER VÀ BỘ GHI

1. Sơ đồ trigger
Bảng D6-1
Q V(Q) Q V( Q ) V(B1) V(B2)
V(B1) -> 0V 1 130,6mV 0 2,3 0,1mV 4,62V
V(B2) -> 0V 0 131,6mV 1 2,3 4,69mV 0,2V

Bảng D6-2
Q Q
1 0
0 1
2. Sơ đồ Trigger R-S trên cổng logic
Bảng D6-3
PS1 PS2 Q Q
R S
↑ 0 1
↑ 1 0

Bảng D6-4
PS1 PS2 Q Q
R S
↓ 0 1
↓ 1 0

3. Sơ đồ Trigger R-S điều khiển bằng xung trên cổng logic

Bảng D6-5
LS1 LS2 PS1 Q Q
S R
0 0 ↑ 0 0
1 0 ↑ 1 0
0 1 ↑ 0 1
1 1 ↑ 1 1

4. Trigger D
Bảng D6-6
LS4 LS1 LS2 PS1 Q Q
D PR CLR xung
X 0 1 X 1 0
X 1 0 X 0 1
0 1 1 ↑ 0 1
1 1 1 ↑ 1 0
 0 1 1 ↑ 0 1
1 1 1 ↑ 1 0

5. Thanh chốt dữ liệu - Latch

Bảng D6-11
O C 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
C K D D D D D D D D Q Q Q Q Q Q Q Q
1 ↑ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 ↑ 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 ↑ 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0 ↑ 1 1 0 0 1 1 0 0 1 0 1 0 1 1 0 0

6. Bộ ghi dịch - Shift register

Bảng D6-12
LS4 LS1 PS1 4Q 3Q 2Q 1Q
LOAD SER IN CK
0 1 ↑ 0 0 0 1
0 0 ↑ 0 0 1 0
0 0 ↑ 0 1 0 0
0 0 ↑ 1 0 0 0
0 1 ↑ 0 0 0 1
0 0 ↑ 0 0 1 0
0 0 ↑ 0 1 0 0
0 0 ↑ 1 0 0 0

Bảng D6-13
LS4 LS1 PS1 LS8 LS7 LS6 LS5 4Q 3Q 2Q 1Q
LOAD SER IN CK 4D 3D 2D 1D
1 0 ↑ 0 1 0 1 0 1 0 1
0 0 ↑ 0 1 0 1 1 0 1 0
0 0 ↑ 0 1 0 1 0 1 0 0
0 0 ↑ 0 1 0 1 1 0 0 0
0 1 ↑ 0 1 0 1 0 0 0 1
0 0 ↑ 0 1 0 1 0 0 1 0
0 0 ↑ 0 1 0 1 0 1 0 0
0 0 ↑ 0 1 0 1 1 0 0 0

Bảng D6-14
PS2 SH/ DS2 DS3 PS1 LS8 LS7 LS6 LS5 LS4 LS3 LS2 LS1 SER
CLR LD SR CK1 CK H G F E D C B A OUT
0 X X X X X X X X X X X X 0
1 X X 0 0 0 0 0 1 1 0 0 1 0
1 0 X 0 ↑ 0 0 0 1 1 0 0 1 0
1 1 1 0 ↑ 0 0 0 1 1 0 0 1 1
1 1 0 0 ↑ 0 0 0 1 1 0 0 1 0
1 1 0 0 ↑ 0 0 0 1 1 0 0 1 0
1 1 0 0 ↑ 0 0 0 1 1 0 0 1 0
1 1 0 0 ↑ 0 0 0 1 1 0 0 1 0
1 1 0 0 ↑ 0 0 0 1 1 0 0 1 0
1 X X 1 ↑ 0 0 0 1 1 0 0 1 0