Alabang-Zapote Road, Pamplona 3, Las Piñas

City, Metro Manila 1740, PHILIPPINES

www.perpetualdalta.edu.ph • +63(02) 871-06-39

College of Engineering

University of Perpetual Help System Dalta

Alabang-Zapote Road, Las Piñas City

College of Engineering

55459 Thursday 2:30-5:30PM Xepto LMS

Section Day Time Room

CPE 3111L: Introduction to Hardware Description Language

Machine Problem No. 2

Universal Logic Gates

October 1 , 2020 October 8, 2020

Date Performed Date Submitted

Remarks Grade

FAUSTINO, Vicente S.
BSCpE / 3rd Year

Engr. Cyd Laurence B. Santos, CpE

Instructor

CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATORY

 Machine Problem 2

UNIVERSAL LOGIC GATES

I. OBJECTIVES

1. To demonstrate the operation of the universal logic gates (NAND and

NOR) using Verilog Hardware Description Language.

2. To interpret the function/operation of the universal logic gates.

3. To design and create a program of the universal logic gates using Verilog
Hardware Description Language.

II. EQUIPMENT / MATERIALS

1. Icarus Verilog Hardware Description Language

2. Computer System

3. Cmd Application

Machine Problem 2: UNIVERSAL LOGIC GATES 1

ENGR. JENNELYN PEREZ-
CABALE
 Alabang-Zapote Road, Pamplona 3, Las Piñas
City, Metro Manila 1740, PHILIPPINES
www.perpetualdalta.edu.ph • +63(02) 871-06-39

College of Engineering

CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATORY

III. DISCUSSION

While many digital circuits can be constructed with just the three basic
digital elements – AND, OR, and NOT – most digital equipment are
implemented with special versions of these circuits known as NAND and
NOR gates, or the so-called Universal Gates. Such Circuits are basically
AND and OR gates combined with an INVERTER. Universal gates are
the most widely used types of digital logic element because they offer
numerous advantages over the simple gates considered earlier. In large
complex digital logic networks, it is difficult to cascade more than just a
few of the simple logic gates. Because there is no buffering between the
gates, loading problems occur and the speed of the operation suffers. For
these reasons, it is generally desirable to combine a simple logic gate with
some types of transistor buffer (such as an inverter) to permit more
flexible interconnection of circuits.

The term NAND gate is a contraction of the expression NOT – AND. A

NAND gate, therefore is an AND gate followed by an INVERTER. The
NAND output is simply the compliment of the AND output.

Like the NAND gate, the NOR gate is an improved logic element used for
implemented decision-making logic functions. The term NOR is a
contraction for the expression NOT – OR. Therefore, the NOR gate is
essentially a circuit
Machine Problem 2: UNIVERSAL LOGIC GATES 2
ENGR. JENNELYN PEREZ-
CABALE
 Alabang-Zapote Road, Pamplona 3, Las Piñas
City, Metro Manila 1740, PHILIPPINES
www.perpetualdalta.edu.ph • +63(02) 871-06-39

College of Engineering

CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATORY

combining the logic functions of an OR gate and an INVERTER.

IV. ACTIVITY

Create a Verilog HDL program that emulates the function of a NAND and
NOR gate. Show your program listing using primitive gates and Boolean
expression. Display your output in command prompt and in gtkwave
simulation window.
NAND GATE: ̅̅

(a) (b)

Input
Output
X Y
0 0 1
0 1 1
1 0 1
1 1 0

Machine Problem 2: UNIVERSAL LOGIC GATES 3

ENGR. JENNELYN PEREZ-CABALE
 Alabang-Zapote Road, Pamplona 3, Las Piñas
City, Metro Manila 1740, PHILIPPINES
www.perpetualdalta.edu.ph • +63(02) 871-06-39

College of Engineering

CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATORY

NOR GATE:̅̅̅
̅

(a) (b)

Input
Output
X Y
0 0 1
0 1 0
1 0 0
1 1 0

Machine Problem 2: UNIVERSAL LOGIC GATES 4

ENGR. JENNELYN PEREZ-
CABALE
 Alabang-Zapote Road, Pamplona 3, Las Piñas City, Metro
Manila 1740, PHILIPPINES www.perpetualdalta.edu.ph •
+63(02) 871-06-39

College of Engineering

CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATORY

V. SOURCE CODE

module experiment2_variables(x, y, outnand, outnor);

input x, y;
output outnand, outnor;

nand n1(outnand, x, y);

nor n2(outnor, x, y);

endmodule

module experiment2_main;
reg x, y;
wire outnand, outnor;

experiment2_variables X(x, y, outnand, outnor);

initial
begin
$dumpfile("experiment2.vcd");
$dumpvars(0, experiment2_main);
$display("| INPUT | OUTPUT |");
$display("| x | y | Nand | Nor |");
$monitor("| %b | %b | %b | %b |",x ,y , outnand, outnor);
$display("|------------------------|");

#0 x=0; y=0;
#1 x=0; y=1;
#2 x=1; y=0;
#3 x=1; y=1;
end
endmodule

Machine Problem 2: UNIVERSAL LOGIC GATES 5

ENGR. JENNELYN PEREZ-
CABALE
 Alabang-Zapote Road, Pamplona 3, Las Piñas City, Metro
Manila 1740, PHILIPPINES www.perpetualdalta.edu.ph •
+63(02) 871-06-39

College of Engineering

CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATORY

VI. PRINTED OUTPUT
Machine Problem 2: UNIVERSAL LOGIC GATES 6
ENGR. JENNELYN PEREZ-
CABALE
 Alabang-Zapote Road, Pamplona 3, Las Piñas City, Metro
Manila 1740, PHILIPPINES www.perpetualdalta.edu.ph •
+63(02) 871-06-39

College of Engineering

CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATOR

ACTIVITY REPORT RUBRICS
Novice Average Expert
Criteria Score
(0-4) (5-7) (8-10)
Does not follow the Follows the given Neat and follows the
Title Page
given format format given format
Presented an Presented correct Presented correct
Preliminary
incorrect result/data but result/data and
Program
result/data and incomplete complete
(X4)
incomplete
Has printed source Has printed source Has printed source
Source Code code but incorrect code and has minimal code, correct and with
errors pleasing designs
Has printed output Has printed output Has printed output,
Printed Output but incorrect and has minimal errors correct and with
pleasing designs
Ideas are not in Ideas are in reference Ideas are taken from
reference to the to result/data the result/data
result/data gathered. gathered.
Observation
gathered. Not Clear, but not Very clear, complete
clear, incomplete complete and short. and sufficient to form a
and too short. discussion.
Ideas are Ideas are somehow Ideas are very much
inappropriate to appropriate to the appropriate to the
the problem. problem that has been problem that has been
Not clear, performed. performed.
incomplete and too Clear but not Very clear, complete
short. complete and short. and sufficient to form a
Conclusion
Failed to link the A general theorem or conclusion.
results with a law was cited that A general theorem or
general theorem or supports the data law is formulated and
law. gathered. discussed reasonably
well to explain the
results.
Untidy Report. Neat Report. Neat and well-
Submitted Submitted Laboratory presented report.
Laboratory report report follows the Submitted Laboratory
Appearance
does not follow the given format, report follows the given
/Presentation
given format Did not use format and uses
/Organization
Did not use Engineering lettering. Engineering lettering.
/Completeness
Engineering Not organized and Organized, original
of Laboratory
lettering. with incomplete and with complete
Report
Not organized and required contents. required contents
not original and
with incomplete
required contents
TOTAL

Machine Problem 2: UNIVERSAL LOGIC GATES 7

ENGR. JENNELYN PEREZ-
CABALE