COMPUTER ORGANIZATION AND

ARCHITECTURE
Dr.M.Sindhuja
Assistant Professor(Senior Grade)
School of Electronics
VIT, Chennai
 MODULE-6

PIPELINING AND PIPELINING HAZARDS

 PIPELINING

Pipelining is an speed up technique where multiple instructions are overlapped in

execution on a processor

Instruction pipelining has six operations

Fetch instruction (FI)
Decode instruction (DI)
Calculate operand (CO)
Fetch operands (FO)
Execute instruction (EI)
Write operand (WO)

Overlap these operations

INSTRUCTION FETCH
Obtain the requested instructions from memory

DECODE INSTRUCTION
Determine operand and opcode specifiers

CALCULATE OPERANDS
calculate effective address of each source operands

FETCH OPERAND
fetch each operand from memory.

EXECUTE INSTRUCTION
Perform indicate operations and store result in destination operand location

WRITE OPERAND
Store the result in memory
SIX STAGE INSTRUCTION PIPELINE
 TIMING DIAGRAM FOR PIPELINE OPERATIONS

Total execution time of 9 instructions in

6 stages pipeline is 14-time unit.

Without pipeline, total time required to

complete 9 instructions is 54 (9 X 6) time
unit.

Hence, speed up in pipeline processing

and the speed up is related to the number
of stages.

Reference:William Stallings, “Computer Organization and Architecture”, 2016, 10th edition, Pearson / PHI, USA
 PIPELINING PERFORMANCE
Cycle time of an instruction pipeline is the time needed to advance a set of instructions
one stage through the pipeline.

The cycle time can be determined as,

  max[  i ]  d   m  d 1  i  k
Where,
 i - time delay of the circuitry in the ith stage of the pipeline
 m - number of stages in the instruction pipeline.
d - time delay of a latch

In general,
Time delay d is equivalent to a clock pulse and  m >> d
n instructions are processed with no branch, k stage to execute all n instructions is,
 k  [k  (n  1)]
k cycles for first instruction, and (n-1) for remaining cycles
For non pipelined processor,

T1  k

 speed up factor for the instruction pipeline compared to execution without the
pipeline is defined as:

T1 nk nk nk
Sk    
Tk [k  (n  1)] k  (n  1) (k  1)  n

 The speed up factor is a function of the number of stages in the instruction pipeline.
 PIPELINING HAZARDS
STRUCTURAL HAZARDS
attempt to use the same resource by two different instructions at the same time

DATA HAZARDS
attempt to use data before it is ready
- An instruction’s source operand(s) are produced by a prior instruction still in the
pipeline

CONTROL HAZARDS
attempt to make a decision about program control flow before the condition has
been evaluated and the new PC target address calculated
- branch instructions

Eliminate hazards by pipeline bubbling/stall

- delay in execution of instructions