PARALLEL PROCESSING, PIPELINING

AND
PIPELINING HAZARDS

Dr. Sampath Kumar,

Associate Professor
Dept. of ECE,
Manipal Institute of
Technology, Manipal.
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 Parallel processing: Improving the performance of a computer system by
carrying out several tasks simultaneously

Ex: A real-time 1024 point FFT processor is expected to perform 1024

floating-point multiplications in 1μsec (1MHz Bandwidth).

Usually, parallelism is included at the instruction-execution level.

Instruction Execution includes: op-code fetch, instruction decode, operand
fetch, operation execution, and result saving.

Instruction Pipeline: All the above operations carried out by overlapping

the instruction fetch phase and execution phase.

Dr. Sampath Kumar, Dept. of ECE, MIT

Dr. Sampath Kumar, Dept. of ECE, MIT 3
Dr. Sampath Kumar, Dept. of ECE, MIT 4
Let a Task, T is executed by performing four activities: A1, A2, A3, A4 in that
order

H/W ( segment) → Hi to perform the activity → Ai

Latch is used to feed the result of one segment as input to the next segment
during the next clock period

Figure: A Four-segment Pipeline

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Dr. Sampath Kumar, Dept. of ECE, MIT

CLK 1: T1 is handled by S1
CLK 2: T1 is handled by S2, T2 is handled by S1
CLK 3: T1 is handled by S3, T2 is handled by S2, T3 is handled by S1
CLK 4: T1 is handled by S4, T2 is handled by S3, T3 is handled by S2, T4 is
handled by S1

Figure: Execution of Four Tasks using a Pipeline

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Note: One task is executed per CLK.
(Here, several tasks are performed, but not on the same instruction)
Pipelining means executing machine instructions concurrently
F Fetch : read the instruction from the memory
D Decode : decode the instruction and fetch the source operands
O Operand fetch
E Execute : perform the operation specified by the instruction
W Write : store the result in the destination location

Each stage in a pipeline is expected to complete its operation in one clock

cycle

Dr. Sampath Kumar, Dept. of ECE, MIT 7

 5 SEGMENT
INSTRUCTION
PIPELINE

Dr. Sampath Kumar, Dept. of ECE, MIT 8

PIPELINING
PIPELINING
• Total number of clock cycles = k + (n-1) = 12
• Speedup = 40/12 (NP/P)
• Efficiency(utilization) = No. of used boxes/ Total boxes = 40/60
• Clock per instruction (CPI) ~ 1
• If clock pulse (tp) is given, say 1ms
• Total time = [k+(n-1)] tp = 12ms
 PIPELINING HAZARDS
Any condition that causes the pipeline to stall is called a “ Hazard ”
Data Hazard (Instruction Hazard): is a condition in which either the
source or the destination operands of an instruction are not available at
the time expected in the pipeline. As a result the pipeline stalls
Control Hazard : is because of a delay in the availability of an instruction

Ex: result of miss in the cache( required the instruction to be fetched from
the main memory)
Structural Hazard : is because of when the two instructions require the use
of a same hardware simultaneously

Dr. Sampath Kumar, Dept. of ECE, MIT 14

 DATA HAZARDS
Ex. 1: Let C= 5, Instr1: A  3 + C
Instr2: B  4 X C
Instructions 1 and 2 are independent to each other. So no data hazard will
takes place.
Ex., 2: Let A= 5, A  3 + A Ex., 3: MUL R4, R3, R2
B 4XA ADD R6, R4, R5
• In Ex., 2 and Ex., 3, Instructions 1 and 2 are dependent to each other. So
data hazard will takes place.

• Control H/W discover the data dependencies and delays reading

register R4 by introducing 2-cycles stall unless operand forwarding is
used.
• In S/W implementation, compiler can introduce 2-cycle delay by
inserting NOP instructions.
• I1: Mul R4, R2, R3
• NOP
• NOP 15

• I2: Add R6, R4, R5

 INSTRUCTIONAL HAZARDS

Ex.,: Situations of Cache Miss, Branch Instructions

Solution : Using Instruction Queue, Dispatch Units we can address
Instructional Hazards.

Structural Hazards
Ex.,: Situations when two instructions demands the buses. ( Instruction
under operand fetch, Instruction under write result units demands data
buses)

Dr. Sampath Kumar, Dept. of ECE, MIT 16

 Thank you

Dr. Sampath Kumar, Dept. of ECE, MIT 17