INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VOLUME 8, ISSUE 10, OCTOBER 2019 ISSN 2277-8616

System On Chip Architecture Information Model

Based VLSI Hierarchical Floorplanning
Rajasekhara Reddy Kallam, Srinivasulu Gundala

Abstract: In Very large scale integration technology few billions of transistors are integrating on a single chip. As more
number of devices are designing on less core area. For designing more blocks with less area makes the more challenging task
on the chip designer and EDA tools. floorplanning is the initial step in the VLSI hierarchical design flow. Floorplanning takes the
most of the design time in hierarchical Design flow and for designing bigger circuits EDA tools having size, memory limitations.
To avoid these problems now a days all core companies follows hierarchical design flows. In This project we use a method of
System on chip Architecture information model with Blackboxes based chip level hierarchical floorplanning. The main of this
project is to design chip planning with less amount time with less memory requirements and getting a good quality of prototype
model in floorplanning stage by analysing hierarchical System on Chip Architecture information provided by EDA tool after
importing design. This project designed by using Cadence (Innovas) Encounter tool.

Index Terms: System on chip architecture information, Chip planning, VLSI, Instances.
——————————  ——————————

1. INTRODUCTION incremental guided floorplanning algorithm with effectively

Physical design is a process of designing physical layout for
the gate level logical netlist. In Hierarchical physical design
there are various levels of designing stages are there i.e.
Partitioning, chip floorplanning, powerplan, placement, clock
tree design, global routing, detailed routing, timing verification
for each and every stage in design, physical verification,
formal verification, Signal integrity analysis, Voltage drop
analysis, ECO and finally generating GDSII file. After GDSII
file generated it is used for creating masking in the fabrication
process. In the lower technologies the feature size of CMOS
cells having very less area, For integrating billions of
transistors on few centimetres Die area there so many
challenges are facing while design such a big designs [2].
Chip planning is most complicated task for top-level chip
planning engineers in the entire Hierarchical physical design
flow. The accuracy of chip planning will effect on the
placement stage, CTS stage ,routing stage [1]. If chipplanning
is designed badly that will results in next level there facing
some critical issues are facing various problems like more
congestion, getting more timing violations etc will result in the
design will taking more number of iterations, and taking more
CPU runtime. Even though doing more number of iterations
some times the design may not get the requirements. Aim of
any chipplanning is to design a prototyping floorplanning. The
prototype floorplan is obtain by doing many iterations and
making the best quality of floor as finalized floorplanning [1] .
During the top level VLSI chip planning dealing with millions of
gate-level logic cells, R.Otten proposed the method called
―Automatic floorplan design in the year of 1982 [3]. There are
so many algorithms, methods implemented in VLSI for doing
floorplanning like simulated anneling algorithm in [4] and
reduce IR-drop violations with the help of B*-tree
representation in [5], power and ground network and
floorplanning method for fast design convergence in [6]. By
using these algorithms, methods also taking more timing while
we are dealing with bigger designs, they are taking more
iterations and large number of instances which are not
required in floorplanning. It reduces some amount of
complexity in chipplanning by masking register to register logic
levels while designing Top level chipplanning [7]. The existing
technique having more instances actually that is not required
in top level chipplanning which results in more iterations. To
get the better prototype we are using System on chip
Architecture information model with Blackboxes in
Chipplanning. The System on Chip Architecture information
model helps to analyze floorplan after importing design that is
very helpful to get better chipplanning with less iterations. We
designed chipplanning by SoC Architecture information based
by creating Blackboxes for the modules.
2. EXISTING METHOD
The Existing method uses active logic reduction technique
with flex model. The active logic reduction method means in
computer science point of view it will mask the inside logic. By
using flexmodel in top-level chipplanning it reduces the
number of instances which will help CPU to reduce CPU run
time and reducing CPU peak memory usage. Flexmodel mask
the logic levels which are in between registers to register.
Flexfillers are used in flexmodel creation. The advantage of
flexfiller is to making the masks on the various logic levels
which are in between reg2reg path in the each logic blocks
which will result in reduction of number of instances during
floorplanning of any chip.

---------------------------------------------
 Rajasekhara Reddy Kallam, Electronics and Communication
Engineering, Lakireddy Bali Reddy College of Engineering
(Autonomous), Mylavaram, Krishna Dt, Andhra Pradesh, INDIA.
 Srinivasulu Gundala, Professor, Electronics and Communication
Engineering , Lakireddy Bali Reddy College of Engineering
(Autonomous), Mylavaram, Krishna Dt, Andhra Pradesh, INDIA.
If we reduce instances that will helps the EDA tool somewhat
to complete floorplan with less time for the design in
floorplanning. The physical view of flex model shown in figure
[1]. After completion of chipplanning is completed the flexfillers
are replaced with original standard cells and the remaining
flow is same as normal hierarchical physical design flow. The
existing method flow shown in figure [2]

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 INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VOLUME 8, ISSUE 10, OCTOBER 2019
Fig.1 Flex filler physical view
Fig.2 Existing method hierarchical foorplanning flow
3. PROPOSED METHOD
The drawback of existing system is it masks only the logic
levels which are in between register to register of each block
in the design. But while doing chip planning we don’t need the
logic inside the each and every block logic, because in top
level floorplanning we are only focus on critical nets between
the blocks. But existing model not mask entire logic in each
block. To reduce instances we used System on Chip
Architecture Information model with Blackboxes. First we
analyse the system architecture information and creating
Blackboxs for each and every module in the design. Blackbox
is created by using area of each block. The design flow for
proposed method shown in figure [3]. The System on Chip
Architecture information model helps the top level chip
planning designers and advantage of creating Blackboxes is
it mask the entire logic in the each and every module used in
the design and we assigns pins for that Blackboxes and doing
the timing budgeting for the critical paths. After that we
analyse the quality of floorplanning by timing and congestion
analysis. With the help of this model the top level chip
planning is completed with less number of iterations, less CPU
runtime.
IJSTR©2019
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ISSN 2277-8616
Fig.3 proposed method design flow
5. RESULTS
With the help of System on Chip Architecture Information (SAI)
model with Blackboxes we got a good quality of floorplanning
with less number of iterations and less CPU runtime. The
initial design and schematic for the design shown in figure [4,
5]. First we analyzed the Architecture obtained in EDA tool
after importing design. Initial design having 5981 instances
after model creation we got 348 instances. We obtain final
prototype floorplanning with less iterations shown figure [6].
After that we checked the quality of floorplanning by global
placement and global routing, getting 0% vertical and
horizontal congestion. We did powerplanning by creating
power ring, power mesh shown in figure [7]. And we did power
analysis for the design based on switching activity and design
frequency and power details of design in milli watts shown in
figure [8].All the stages in the floorplanning we calculated CPU
runtime, peak memory and compared total CPU time, peak
memory, their improvements with existing model shown in
figure [9-12].
Fig.4 Initial design
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INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VOLUME 8, ISSUE 10, OCTOBER 2019 ISSN 2277-8616

Without model With model Memory

Improvement
Peak memory 997.51Mb 312.031Mb 3.196

Fig.9 Memory improvement of without model and with

model

Existing method System architecture

improvement information model with
Fig.5 Schematic of design Blackboxes in design
improvement
CPU total run time 5.57 13.09
in floorplanning
stage
Peak memory 2.22 3.78

Fig.10 Comparing existing method, SAI model with

Blackboxes method

Fig.6 SAI model with Blackboxes floorplanning
6. CONCLUSION
System on Chip Architecture Information model floorplanning
having more advatage in chipplanning because it helps the top
level designers to get best quality of floorplannig. The
prototype design is obtain in the floorplanning with less
numbers of iterations which will result in quality of
floorplanning with less CPU runtime. We used this model for
small design. If we use this method in bigger circuits it may
give better quality of chipplanning with less iterations and CPU
runtime.

REFERENCES
[1] Y.Zhou,Y.Yan, and W.Yan "A method to speed up VLSI
Hierarchical physical design in floorplanning",2017 IEEE
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Fig.7 Power planning of design [2] S.N. Adya and I.L. Markov, ―Fixed-outline Floorplanning:
Enabling Hierarchical Design‖, IEEE Trans. on VLSI
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[4] R. Otten. ―Automatic floorplan design,‖ 19th Design
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[9] Rajasekhara Reddy Kallam, Srinivasulu Gundala

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