Silvaco TCAD Tutorial MOS

TCAD Simulation
Introduction to TCAD Software an

its Operations
• Introduction to TCAD.
• Overview of Athena (A Process Simulator).
• Overview of Atlas (A Device Simulator).
• Overview of Tonyplot (A graphical post
processing tool).
• A Tutorial MOSFET Example
TCAD, C. Lien Slide1

遠端連線伺服器&啟動Silvaco (I)
使用MobaXterm
1. 開啟MobaXterm
2. 點選Session
3. 點選SSH
4. remote host
輸入 140.114.24.31 port22
輸入 140.114.24.33 port22
5. login as:
輸入使用者名稱(s106XXXXXX)
6. 選擇工作站伺服器
輸入 ssh -X ws43
7. 輸入 password
8. 輸入 deckbuild &

遠端連線伺服器&啟動Silvaco (II)
使用Xmanager
1. 開啟 Xshell
2. 左上方點選新增
3. 點選SSH
主機 140.114.24.31或140.114.24.33
port22
4. 輸入使用者名稱(s106XXXXXX)
5. 輸入password
6. 選擇工作站伺服器
輸入 ssh -X ws43
7. 再輸入password
8. 輸入deckbuild &

Introduction to TCAD Software an its Operation
Introduction to TCAD.
Overview of Athena (A Process Simulator).
Overview of Atlas (A Device Simulator).
Overview of Tonyplot (A graphical post processing
tool).
A Tutorial MOSFET Example.

TCAD Simulation Tools (I)
Technology Computer Aided Design(TCAD)?

T: semiconductor Technology
C: Computer hardware and softwave
A:physics model and numerical methods Aided
D:process and device Design

TCAD Simulation Tools (II)
Commercial TCAD Tools

Silvaco: Athena, Atlas
Synopsys: Tsupprem, Medici,
Sentaurus(Process, Structure Editor, Device)
Non- Commercial Programs

Nano hub(Purdue U)
More,…

TCAD Simulation Tools(III)
Process simulation
Category
 Epitaxy
 Photolithography
 Deposition
 Etching
 Diffusion
 Annealing
 Ion implantation
 Oxidation
 CMP Hong Xiao, Introduction to semiconductor manufacturing technology, 2012

TCAD Simulation Tools(IV)
Device simulation
Electrical characteristics Physical characteristics
 Current-voltage, I-V curve  Potential

 Capacitance-voltage, C-V curve  Electrical field
 Threshold voltage, Vt  Electron and hole density
 Current gain  Temperature
 Trans-conductance  energy
 Output resistance  velocity
 Contact resistance  Energy band diagram
 Cut-off frequency  Mobility
 Generation and recombination rate

Device Modeling and Simulation (I)
Process
Recipies
Doping profile Electrical Device

Device Geomrtry Characteristics
Process Device Device
Simulation Simulation Simulation
Poisson’s Equation
TEM, SIMS Drift-Diffusion
Measurements Boltzmann Energy Transport
Equation Spherical Harmonics
Monte Carlo
Wigner Quantum Monte Carlo

Equation Density-Gradient
Schrodinger Quantum Corrections

Equation Green’s Function

Device Modeling and Simulation (II)
Physical Models Boundary conditions

Input Output
 Recombination  Ohmic/Schottky
Process  Bandgap/DOS  Insulator/Neumann
 Mobility  Interface charge/traps
Structure  Statistics  Lumped/distributed RC
Terminal
Mesh
Numencal methods Analysis characteristics
Doping
 Decoupled(Gummel)  Transient
 Coupled(Newton)  Small-signal a.c.
 Linear matrix  Impact ionization
 Jacobian matrix  Gate current

The Drift-Diffusion Model
 dn 
J nx  q  n nE  Dn  Electron Curent
 dx 
 dp 
J px  q  p pE  D p  Hole Current
 dx 
n 1 J nx n  n0
  Continuity equations for electrons
t q x 
p 1 J px p  p0
  Continuity equations for holes
t q x 
 2 q
  ( p  Nd  n  Na ) Poisson's equation
x 2 

Introduction to Silvaco Tools
Silvaco Tools
 Deckbuild ： An interactive and graphic runtime environment for

developing process and device simulation input decks.
 Athena：A simulator that provides general capabilities for numerical,

physically-based, two-dimensional simulation of semiconductor processing.
 Atlas：Provides general capabilities for physically-based two (2D) and

three-dimensional (3D) simulation of semiconductor devices
 Tonyplot ： A graphical post processing tool for use with all Silvaco
simulators and display simulation structure and electrical results.

Silvaco Inputs and Outputs

Running Syntax Command
Running Silvaco tools inside Deckbuild
The GO statement tells DeckBuild to shut down the current simulator and start up
the specified simulator when the statement is executed.
 go Athena
 go atlas simflags="-P 4" Number of CPU
Select version by Silvaco tools
This statement will append "-V 5.0.8.R " to the default DevEdit argument to start
version 2.2.1.R of the tool.
 go atlas simflags ="-V 5.0.8.R“
Running Silvaco tools without Deckbuild
To run Silvaco tools directly under unix use the following command line.
 athena <input filename>
 atlas –V 5.0.8.R <input filename>

Silvaco File Information
File Information
File type Syntax Features
Input File .in Save simulation code by DeckBuild.
Save the device structure obtained by process
Structure File .str
simulation or devices editor.
Simulation File .log Save devices simulation data results.
Define variables for substitution into Atlas syntax.
Set File .set
set commands are executed by DeckBuild.
Electrical
.dat Extract data obtained by simulation calculation.
result file
Example :
structure outfile=MOSFET.str
log outfile=MOSFET.log master

What is a simulation mesh grid? (I)
 The number of nodes in the grid (Np) has a direct influence on

simulation convergence, accuracy and time.
 A finer grid should exist in those areas of the simulation structure

where ion implantation will occur, where p-n junction will be formed,
or where optical illumination will change photoactive component
concentration.
 To maintain the simulation time within reasonable bounds, the fine

grid should not be allowed to spill over into unnecessary regions.
 The maximum number of grid nodes is 20,000 for Silvaco simulations.

What is a simulation mesh grid? (I)
 The number of nodes in the grid (Np) has a direct influence on

simulation convergence, accuracy and time.
 A finer grid should exist in those areas of the simulation structure

where ion implantation will occur, where p-n junction will be formed,
or where optical illumination will change photoactive component
concentration.
 To maintain the simulation time within reasonable bounds, the fine

grid should not be allowed to spill over into unnecessary regions.
 The maximum number of grid nodes is 20,000 for Silvaco simulations.

What is a simulation mesh grid? (II)
Close Loose

tool).

Athena Overview
Athena : is a simulator that provides general capabilities for numerical.
Physically-based: two-dimensional simulation of semiconductor processing. (Include
the Epitaxy, Photolithography, Deposition, Etching, Diffusion, Annealing, Ion
implantation, Oxidation, CMP)
Athena licensable
 Athena: This tool performs structure initialization and manipulation, and

provides basic deposition and etch facilities
 SSuprem4: This tool is used in the design, analysis, and optimization of silicon
semiconductor structures. It simulates silicon processing steps such as ion
implantation, diffusion and oxidation.
 Elite: This tool is a general purpose 2D topography simulator that accurately
describes a wide range of deposition, etch and reflow processes used in modern
IC technologies.
 Optolith: This tool performs general optical lithography simulation including 2D
aerial imaging, non-planar photoresist exposure, and post exposure bake and
development.

Process Simulation by Athena
Initial geometry
Creating structure and mesh
Initial substrate
Sequence of process steps
Epitaxial growth
Layers deposition
Geometrical etching
Ion implantation
Diffusion
CMP
Physical models
Implant models
Diffusion models
Oxidation models

Process of Creating the Device Structure
Process Flow
go athena
Defining initial mesh grid
Defining initial substrate
Conformal layer deposition

Photoresist coating
Defining Masks
Geometric etches
Ion implantation and diffusion
Specifying the electrodes
Saving the structure file

Defining Initial Mesh Grid (I)
line x loc=0 spac=0.1 line x loc=0.0 spac=0.1
line x loc=1 spac=0.1 line x loc=0.3 spac=0.02
line y loc=0 spac=0.1 line x loc=1 spac=0.1
line y loc=1 spac=0.1 line y loc=0 spac=0.03
line y loc=0.2 spac=0.02
line y loc=1 spac=0.1
x1, x2, y1, and y2 are location
s1, s2, s3, and s4 are spacing
Uniform grid Non uniform grid

Defining Initial Mesh Grid (II)
1. Open Deckbuild
2. Choose the Commamds
3. Select Mesh initialize
4. Select Material
5. Select Orientation
6. Select Impurity
7. Select Concentration (or Resistivity)
8. Enter Concentration value (or Resistivity)
9. Select Dimensionality (1D , 2D , Cylindrical)
10. Choose the Write
Composition fraction：
Used to select the ratio of compound materials.
The input value is the composition ratio of the first material in the compound.

Defining Initial Mesh Grid (III)
Example(1):
init silicon c.boron=1e14 orientation=100 two.d space.mult=3
Example(2):
init germanium phosphor resistivity=0.001 orientation=111 two.d cylindrical
space.mult=2
Pressing the Write button the

corresponding command line
will appear in the Deckbuild
Text Subwindow.
The STRUCT OUTFILE line is

generated in the Deckbuild
Output Subwindow.

Layer Deposition (I)
1. Open Deckbuild
3. Select Process  Deposit
4. Select Basic Parameters
5. Select Material
6. Enter Thickness value
7. Select Grid (Define Mesh)
8. Select Impurities or default
9. Choose the Write
Example:
deposit oxide thick=1 divisions=5 dy=0.05 ydy=0.3 min.dy=0.05 min.space=0.2

Layer Deposition (II)
Total number of grid layers : cut the deposition layer into N equal parts.
Nominal grid spacing (μm) : dy is similar to defining the spacing parameter.
Grid spacing location (μm) : ydy is similar to defining the location parameter.
Minimum grid spacing (μm) : min.dy replaces the minimum spacing.
Minimum edge spacing (μm): min.space replaces the minimum spacing.

Etch (I)
1. Open Deckbuild
3. Select Process  Etch
4. Select Geometrical
5. Select Geometrical type
Different syntax for etching types:
Example1： left、right、above、below:
Enter the Etch coordinate position.
Example2： dry: Enter the Thickness value.
Example3： any shape: Enter the coordinate
position of the selected range 。
6. Choose the Write

Etch (II)
Example1:
etch oxide all
#Etch the oxide completely.
Example2:
oxide left p1.x=0.5
#Oxide layer should be etched to the left from x= 0.5 μm
Example3:
etch oxide dry thick=0.01
#Etch oxide 10nm.
#Here, the dry etched surface topography unchanged, and the overall thickness
decreases.

Etch (III)
Example4:
etch oxide start x= 4.00 y= -1.00
etch cont x= 4.00 y= 3.00
etch cont x= 6.00 y= 3.00
etch done x= 6.00 y= -1.00
#A rectangular shape is created in a counterclockwise direction, and the oxide on
the surface is completely etched.

Ion Implantation (I)
1. Open Deckbuild
3. Select Process  Implant
4. Select Impurity
5. Enter Dose and Energy value
6. Select Model
7. Enter Tilt and Rotation value
8. Select Material type

Ion Implantation (II)
Impurity： Type of impurity implanted.
Dose： The implant dose (cm-2), determines the doping concentration .
Energy：The energy of the ion (KeV). The position of the front end of the
impurity concentration is related to the injection energy.
Model： Choose the doping model.
Tilt：The initial angle of ion beam injection, the default value is 7°.
Rotation：The angle between the implanted ion beam and the wafer surface, the
default value is 30°
Continual rotation：Rotate wafer during injection.
Point defects：The calculation of implant damage refers to the vacancy of lattice
atoms caused by ion implantation.
Example:
implant boron dose=2.0e12 energy=80 tilt=7 rotation=30 crystal unit.damage
dam.factor=1

Diffusion(I)
1. Open Deckbuild
3. Select Process  Diffuse
4. Select Time/Temp
5. 輸入Time/Temp值
6. Select Ambient
7. Select Gas, pressure, flow rate
8. Select Impurities (可以不選)
9. Select Model (可以不選)

Diffusion(II)
Time: The total time of diffusion.
Temperature: The temperature of the environment (℃).
Temp constant: Temperature is constant temperature.
Temp reamped: Set the rate of change when the temperature is changing.
Dry O2, Wet O2, Nitrogen, GasFlow: Diffusion gas environment.
HCL: Percentage of HCl in the oxidant gas stream.
Gas Pressure: Gas ambient pressure (atm), the default value is 1.
Impurities: Impurities and concentration in the gas environment (atoms/cm3).
Diffusion: Model selection for diffusion.
Compressible and A simplification of the hydrodynamic flow equation is solved
to obtain the flow of oxide elements.
Viscous: Viscous Model calculates stresses in the growing oxide and creates
almost the same shape for the silicon/oxide interface as does the Compress
model.
Reflow: Consider surface reflow when diffusion.
Diffusion(III)
Example1:
diffus time=10 minutes temp=1050 dryo2
#Dry oxygen grows at 1050°C and the diffusion time is 8 minutes.
Example2:
diffus time=6 minutes temp=1000 nitro c.phosphor=1e13
#The phosphorus impurity contained in the gas environment and its
concentration is 1e13cm-3.
Example3:
method fermi
diffus time=15 minutes temp=1050 weto2
#Consider the fermi model.

Structure Mirror
1. Open Deckbuild
3. Select Structure
4. Select Mirrior
5. Select Left or Right
6. Choose the Write
Example:
struct mirror right

Define Electrode
1. Open Deckbuild
3. Select Structure
4. Select Electrode
5. Select Type(Specified position or Backside)
(Specified position: Enter coordinates)
6. Enter Name of Electrode
6. Choose the Write
Example:
electrode name=gate x=3.5 y=0.5
electrode name=source x=1.5 y=0.7
electrode name=drain x=5.5 y=0.7
electrode name=body backside

tool).

Atlas Overview
Athena : Provides general capabilities for physically-based two (2D) and three-
dimensional (3D) simulation of semiconductor devices.
Fully Integrated Capabilities
Atlas works well with other software from Silvaco. For example, Atlas
 Runs in the DeckBuild interactive run-time environment.
 Is interfaced to TonyPlot, the interactive graphics and analysis package
 Accepts input from the Athena and SSuprem3 process simulators.
 Is interfaced to Utmost parameter extraction and device modeling software.

Comprehensive Set of Atlas Models
 DC, AC small-signal, and full time-  Advanced mobility models.

dependency.  Heavy doping effects.
 Drift-diffusion transport models.  Full acceptor and donor trap dynamics.
 Energy balance  Ohmic, Schottky, and insulating contacts.
 Hydrodynamic transport models.  SRH, radiative, Auger, and surface
 Lattice heating and heatsinks. recombination.
 Graded and abrupt heterojunctions.  Impact ionization (local and non-local).
 Optoelectronic interactions with general  Floating gates.
ray tracing.  Band-to-band and Fowler-Nordheim
 Amorphous and polycrystalline materials. tunneling.
 General circuit environments.  Hot carrier injection.
 Stimulated emission and radiation.  Quantum transport models.
 Fermi-Dirac and Boltzmann statistics.  Thermionic emission currents.

Standard atlas steps
Simulation Flow
Building structure
(or input Athena structure )
mesh
region
doping
electrode and contact
Physical models selection
mobility
recombination
carrier statistics
impact ionization
tunneling
Set numerical methods
Set bias conditions

Defining ATLAS Mesh Grid
1. Open Deckbuild
3. Select Structure
4. Select Mesh
5. Enter Location value (Axis position)
6. Enter Spacing value
(Expand the spacing of the grid
lines outward from the axis position.)
7. Choose the Write
範例：mesh space.mult=1.0
x.mesh location=0.0 spacing=0.05
x.mesh location=3.0 spacing=0.05
y.mesh loc=0.0 spac=0.02
y.mesh loc=2.0 spac=0.02

Defining ATLAS Region
1. Open Deckbuild
3. Select Add Region
4. Select Device coordinates or Grid indices
5. Enter X, low and high value
6. Enter Y, low and high value
7. 點選Material
8. Choose the Write
範例： region number=1 x.min=0 x.max=0.5 y.min=0 y.max=0.5 material=Silicon

region name=silicon x.min=0 x.max=0.5 y.min=0 y.max=0.5 material=Silicon

Defining ATLAS Doping
1. Open Deckbuild
3. Select Structure
4. Select Doping  Analytic
5. Select Profile Type
6. Enter Conc. and Select N or P Type
7. Select Direction (X or Y)
7. Choose the Write
Example：
doping uniform conc=1e+19 n.type x.left=0 x.right=0.2 y.top=0 y.bottom=0.2 direction=x
or
profile n-type n.peak=1e+19 uniform x.min=0 x.max=0.2 y.min=0 y.max=0.2

ATLAS Electrode and Contact
1. Open Deckbuild
3. Select Structure
4. Select Electrode selection
5. Select Electrode name and enter the value
(The coordinate position of the rectangle)
6. Select Contact and materials
(If Athena has already set Electrode, only the
coordinates of the contact need to be set here.)
Commamds Models  Contact(set Contact)
7. Choose the Write
Eample：
electrode name=gate number=1 x.min=0 x.max=1 y.min=0 y.max=1
contact name=drain ALUMINUM
or contact name=anode workfunction=4.9 barrier alpha=1e-7
Physical Models
1. Open Deckbuild
3. Select Models
4. Select Models
5. Select suitable models
（Different devices are suitable
for different models.）
6. Select Write
The physical model can be divided into five types:

mobility, recombination, carrier statistics, impact ionization, and tunneling.
Add temperature considerations :
Energy Balance Models and Heat flow equation

Mobility Models
Model Syntax Notes
Lookup table valid at 300K for Si and GaAs
Concentration Dependent CONMOB only. Uses simple power law temperature
dependence.
Concentration and Caughey-Thomas formula. Tuned for 77-
ANALYTIC
Temperature Dependent 450K.
Arora’s Model ARORA Alternative to ANALYTIC for Si.
Dorkel-Leturq Model. Includes n, N and T
Carrier-Carrier Scattering CCSMOB dependence. Important when carrier
concentration is high.
Parallel Electric Field Si and GaAs models. Required to model any
FLDMOB
Dependence type of velocity saturation effect.
Complete model including N, T, E//, and E⊥
Lombardi (CVT) Model CVT
effects. Good for non-planar devices.
YAMAGUCH Includes N, E// and E⊥ effects. Only
Yamaguchi Model
I calibrated for 300K.

Generation-Recombination Models
Model Syntax Notes

Uses fixed minority carrier lifetimes. Should be
Shockley-Read-Hall SRH
used in most simulations.
CONSR Uses concentration dependent lifetimes.
Concentration Dependent
H Recommended for Si.
Direct transition of three carriers. Important at
Auger AUGER
high current densities.
Band-band recombination. For direct materials
Optical OPTR
only.
Recombination at semiconductor to insulator
S.N
Surface interfaces. This is set in the INTERFACE
S.P
statement.

Impact Ionization Models
Model Syntax Notes

IMPACT Recommended for most cases. Includes
Selberherr’s Model
SELB temperature dependent parameters.
Similar to Selberherr’s model but with
IMPACT
Grant’s Model different
GRANT
coefficients.
IMPACT
Crowell-Sze Uses dependence on carrier scattering length.
CROWELL
Non-local model used with Energy Balance.
IMPACT
Toyabe Model Any
TOYABE
IMPACT syntax is accepted.
N.CONCAN Non-local model developed in Flash EEPROM
Concannon
P.CONCAN technologies.

Tunneling Models and
Carrier Injection Models
Model Syntax Notes

For direct transitions. Required with very
Band-to-Band (standard) BBT.STD
high fields.
Concannon Gate Current N.CONCAN Non-local gate model consistent with
Model P.CONCAN Concannon substrate current model.
QTUNN.EL Quantum tunneling through conduction band
Direct Quantum tunneling
QTUNN.HO barrier due to an insulator.
FNORD Self-consistent calculation of tunneling
Fowler-Nordheim
FNHOLES through insulators. Used in EEPROMs.
Klaassen Band-to-Band BBT.KL Includes direct and indirect transitions.
Models energetic carriers tunneling through
Hot Electron Injection HEI
insulators. Used for gate current and Flash
Hot Hole Injection HHI
EEPROM programming.

Specifying Material and Model Paramater
Example (Material and Region):

MATERIAL MATERIAL=Silicon EG300=1.12 MUN=1500 MUP=500 AFFINITY=4.05
MATERIAL REGION=2 TAUN0=2e-7 TAUP0=1e-5
Example (Alloys):
region num=4 material=SiGe x.comp=0.25
material material=SiGe taun0=1.e-7 taup0=1.e-7 nv300=1.55e19 nc300=2.86e19
# x.comp, This is the composition fraction (X) for a region with a composition dependent cations (e.g.,
Si(1-x)Ge(x)).
Example(Models):
MODELS BTBT BBT.A_KANE=3.5e21 BBT.B_KANE=2.25e7 BBT.GAMMA=2.5
Example (Interface):
INTERFACE QF=3e10 X.MIN=1.0 X.MAX=2 Y.MIN=0.0 Y.MAX=0.5
Example (Floating contact):

CONTACT NAME=fgate FLOATING

Choosing Numerical Methods(I)
Atlas solves up to six equations. There are basically three types of solution methods：
GUMMEL、 BLOCK、 NEWTON
NEWTON
Each iteration of the Newton method solves a linearized version of the entire non-linear
algebraic system.
It is useful when the system of equations is strongly coupled and has quadratic
convergence.
It may spend extra time solving for quantities that are essentially constant or weakly
coupled. However for almost all cases, this method is preferred and it is the default.
GUMMEL
The Gummel method solves for each unknown in turn, keeping the other variables
constant and repeating the process until a stable solution is achieved.
This method tolerates relatively poor initial guesses Generally, it is useful where the
system of equations is weakly coupled but has only linear convergence.
BLOCK
The Block method solves some equations fully coupled while others are decoupled.
It is useful when lattice heating or energy balance equations are included.

Choosing Numerical Methods(II)
Numerical methods cases:
Example1: Basic Drift Diffusion Calculations
method gummel newton
Example2: Drift Diffusion Calculations with Lattice Heating
method block newton
Example3: Energy Balance Calculations：
method block newton
Example4: Energy Balance Calculations with Lattice Heating
method gummel block newton
Atlas can solve the electron and hole continuity equations. You can choose through the
“CARRIERS” syntax.
carriers=2 (Solve the results of electron and hole simulations.)
method carriers=1 hole (Only solve the results of the hole simulation.)
method carriers=0 (Only solve the simulation results of the potential energy distribution.)

Obtaining Solutions
 The “log” and “save” syntax is to save the calculated results as log files and
structure files respectively.
 The log syntax needs to be before solve, so that the solved data can be saved.
Example:
solve init  The electrode voltage conditions start from zero.
method newton trap carriers=2
log outf=EE2.log The information data is saved after this line.
solve vdrain=0.1
solve vgate=-2 vstep=0.5 vfinal=3 name=gate
save outf=EE2.str structure
tonyplot MOSFET.str Use tonyplot to open the solved structure file.
tonyplot MOSFET.log Use tonyplot to open the solved data file.
log off Stop recording.
quit

Run-time output
Lists the XNORM and RHSNORM errors
Voltage at the contact surface
Iteration tolerance values

numbers
error values
This error has

met its tolerance
Solution Method
N = Newton
G = Gummel
B = Block Electron, hole, conduction, and total currents
A = newton with autonr
S = coupled Poisson-Schrodinger solution

tool).

TonyPlot
TonyPlot is a graphical post processing tool for use with all
Silvaco simulators.

Tonyplot function menu (I)
The main operations of the “File” list:
 Open: Open the file to be displayed.

 Save As: Save as a picture file.
 Save Series: Save multiple files as series picture files.
 Export: Export data files.
 Open Set Files: Import display setting files.
 Save Set Files: Save the display setting file.

Tonyplot function menu (II)
The main operations of the “Edit” list:
 Select All: select all files displayed by Tonyplot

 Swap Two Plots: If two results are displayed in Tonyplot and both are selected (execute
Select All to select all graphs), then the display order of the two results will be changed.
 Make Overlay: Overlay several results displayed by Tonyplot.
 Split Overlay: Release the overlapping graphs of Make Overlay and open several new
subgraphs afterwards.
 Plot Difference: Display the difference between two similar results (a new subgraph is
opened).
 Duplicate Selected: Duplicate the selected graph and open a new subgraph at the end.
 Delete Selected: Delete the displayed image.
 Aspect Ratio: set Tonyplot aspect ratio
 Materials: Customize the color for materials
 Functions: The displayed vector can be calculated.

Tonyplot function menu (III)
The main operations of the “Edit” list:
 Select All: select all files displayed by Tonyplot

 Swap Two Plots: If two results are displayed in Tonyplot and both are selected (execute
Select All to select all graphs), then the display order of the two results will be changed.
 Make Overlay: Overlay several results displayed by Tonyplot.
 Split Overlay: Release the overlapping graphs of Make Overlay and open several new
subgraphs afterwards.
 Plot Difference: Display the difference between two similar results (a new subgraph is
opened).
 Duplicate Selected: Duplicate the selected graph and open a new subgraph at the end.
 Delete Selected: Delete the displayed image.
 Aspect Ratio: set Tonyplot aspect ratio
 Materials: Customize the color for materials
 Functions: The displayed vector can be calculated.

Tonyplot function list (IV)
The main operations of the “Plot” list:
 Annotation: Annotation. You can set the title name, axis position and name,
and the axis display range.
 Labels: Add labels to the Tonyplot interface.
 Level Names: Change the name of each line when displaying in the “Overlay”
mode. The default is to use the file name.
 Set Zoom: zoom in a specific area, the area is given by the x and y coordinate
values;
 Zoom Out: Revert from the zoomed state to the fully displayed state.
 Display: The Display (2D Mesh) window will appear to set the display mode
of the analog data.

TonyPlot Display
 Mesh: Display the mesh distribution in the devices structure.
 Edges: Display the boundaries for the devices structure.
 Region: Display material regions.
 Contours: Display the physical quantities inside the devices structure. (Some need to be listed in
"output", such as: con.band, val.band is the information of conduction band and valence band position).
 Vectors: Display the vector information inside the devices (such as electric field distribution, current
distribution...).
 Light: Shows the characteristics of light inside the devices (such as light intensity, wavelength and
reflectivity...).
 Junction: Displays the boundary of the junction in the devices structure.
 Electrodes: Display the name of the electrode.
 3D: Display three-dimensional information.
 Lines: Display according to color.

Mesh

Contours

Vectors

Junction

Electrodes

Electrodes

Cutline
 When the “Cutline” tool is used on an overlay 2D Mesh plot, a section is taken from each
level.
 TonyPlot automatically overlays each of these when it creates the new cross section plot.

Ruler
 The Ruler tool can be used on any type of plot. It provides coordinate geometry
information of any line drawn over a structure.
 The Ruler shows useful data such as length, gradient, and intercepts of a line you
defined

Probe
 The Probe tool can be used to look at structure information in a 2D Mesh. It provides
both geometry and impurity data and can be used to find specified structural features.

Display of Data Plot (I)
Open log file，Edit  Select All  Make Overlay ， draw all the graphs as a
comparison.

Display of Data Plot (II)
Raw data

Display of Data Plot (III)
1. Open Display
2. Select X-axis Scale
3. Select X-axis Quantity
4. Select Y-axis Scale
5. Select Y-axis Quantity
6. Select Apply

Display of Data Plot (IV)
Adjusted new plot

Display of Data Plot (IV)
1. Open File
2. Select Export
3. Select Format
4. Enter Base Directory
5. Enter File Basename
6. Enter Extension
7. Select OK

tool).

Tutorial MOSFET Example (I)
How to open the tutorial MOSFET example given by Silvaco.

Tutorial MOSFET Example (II)
Define the structure mesh and initialization.
go athena simflags="-P 4"
#
line x loc=0 spac=0.1
line x loc=0.2 spac=0.006
#
#
init orientation=100 c.phos=1e14 space.mul=3
structure outfile=mos1ex01.str

Tutorial MOSFET Example (III)
P-Well implantation and drive in.
#pwell formation including masking off of the nwell
#
diffus time=30 temp=1000 dryo2 press=1.00 hcl=3
#
etch oxide thick=0.02
#
#P-well Implant
#
implant boron dose=8e12 energy=100 pears
#
diffus temp=950 time=100 weto2 hcl=3

Tutorial MOSFET Example (IV)
N-Well implantation and drive in.
#N-well implant not shown -
# welldrive starts here
diffus time=50 temp=1000 t.rate=4.000 dryo2 press=0.10 hcl=3
#
diffus time=220 temp=1200 nitro press=1
#
diffus time=90 temp=1200 t.rate=-4.444 nitro press=1
#
etch oxide all

Tutorial MOSFET Example (V)
Gate stack formation along with threshold adjustment.
#sacrificial "cleaning" oxide
diffus time=20 temp=1000 dryo2 press=1 hcl=3
#
etch oxide all
#
#gate oxide grown here:-
#
#vt adjust implant
implant boron dose=9.5e11 energy=10 pearson
#
depo poly thick=0.2 divi=10

Tutorial MOSFET Example (VI)
Lightly doped source/drain implantation.
#from now on the situation is 2-D
#
etch poly left p1.x=0.35
#
method fermi compress
diffuse time=3 temp=900 weto2 press=1.0
#
implant phosphor dose=3.0e13 energy=20 pearson

Tutorial MOSFET Example (VII)
Spacer formation and source/drain implantation.
depo oxide thick=0.120 divisions=8
#
#
implant arsenic dose=5.0e15 energy=50 pearson
#
diffuse time=1 temp=900 nitro press=1.0

Tutorial MOSFET Example (VIII)
Aluminum metal contact for source/drain.
#
etch oxide left p1.x=0.2
deposit alumin thick=0.03 divi=2

etch alumin right p1.x=0.18

Tutorial MOSFET Example (IX)
MOSFET structure parameter extraction for device simulator.
# Extract a design parameter.....
extract name="gateox" thickness oxide mat.occno=1 x.val=0.49
# Extract another design parameters...
# extract final S/D Xj...
extract name="nxj" xj silicon mat.occno=1 x.val=0.1 junc.occno=1
# extract the long chan Vt...
extract name="n1dvt" 1dvt ntype vb=0.0 qss=1e10 x.val=0.49
# extract a curve of conductance versus bias....
extract start material="Polysilicon" mat.occno=1 bias=0.0 bias.step=0.2 bias.stop=2 x.val=0.45
extract done name="sheet cond v bias" curve(bias,1dn.conduct material="Silicon" mat.occno=1
region.occno=1) outfile="extract.dat"
# extract the N++ regions sheet resistance...
extract name="n++ sheet rho" sheet.res material="Silicon" mat.occno=1 x.val=0.05 region.occno=1
# extract the sheet rho under the spacer, of the LDD region...
extract name="ldd sheet rho" sheet.res material="Silicon" mat.occno=1 x.val=0.3 region.occno=1
# extract the surface conc under the channel....
extract name="chan surf conc" surf.conc impurity="Net Doping" material="Silicon" mat.occno=1
x.val=0.45

Tutorial MOSFET Example (X)
The complete MOSFET device structure by mirroring.
structure mirror right
electrode name=gate x=0.5 y=0.1
electrode name=source x=0.1
electrode name=drain x=0.9
electrode name=substrate backside
structure outfile=mos1ex03_0.str
# plot the structure

tonyplot mos1ex03_0.str -set mos1ex03_0.set

Tutorial MOSFET Example (XI)
The use of device simulator, atlas, to find its behavior.
The use of tonyplot to graphically display the results.
go atlas
# set material models
models cvt srh print
contact name=gate n.poly
interface qf=3e10
# get initial solution
solve init
method newton trap
solve pre
# Bias the drain a bit...
solve vdrain=0.025 vstep=0.025 vfinal=0.1 name=drain
# Ramp the gate to a volt...
log outf=mos1ex03_1.log master
solve vgate=0 vstep=0.1 vfinal=2 name=gat
# extract the device parameter SubVt...
extract init inf="mos1ex03_1.log"
extract name="nsubvt" 1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")))))
tonyplot mos1ex03_1.log -set mos1ex03_1_log.set
quit
FEOL CMOS Process Flow
• FEOL CMOS process flow.

• Active region definition.
• Well implantations.
• Gate stack formation.
• Source/Drain implantations

Objectives
The use of process simulator to complete CMOS
transistors using the front end of line (FEOL) CMOS
process with shallow trench insolation (STI) as shown
below.
The outline of the FEOL process flow is given as follow.
Pad OX /SiN depo
AA (Active Area) Photo
STI STI etch (Shallow Trench Isolation)

HDP depo (STI depo)
STI CMP / clean
Well define and drive-in
Well Vt adjust implant
Gate OX define (Core and I/O)
Poly depo / poly etch
LDD implant
Poly loop Spacer
S/D implant

Pad OX /SiN depo

STI CMP / clean
Well
Vt adjust implant
Poly loop LDD implant
Spacer
S/D implant

Initialization (I)
Define the structure mesh and initialization.
go athena simflag="-P all"
#define parameter
set STI=0.5
set Lg=0.25
set Lsd=0.25
set Ldd=0.25
set Tpoly=-0.2
Set NMOS=$"STI"+($"Lsd"*2)+($"Ldd"*2)+$"Lg"

Initialization (II)
Define the structure mesh
# define mesh
line x loc=0 spac=0.02
#width of STI N
line x loc=$"STI" spac=0.02
#width of NMOS Source
line x loc=$"STI"+$"Lsd" spac=0.02
#width of NMOS Source LDD
line x loc=$"STI"+$"Lsd"+$"Ldd" spac=0.02
#width of NMOS hChannel
line x loc=$"STI"+$"Lsd"+$"Ldd"+($"Lg"*0.5) spac=0.02
#width of NMOS Channel
line x loc=$"STI"+$"Lsd"+$"Ldd"+$"Lg" spac=0.02
#width of NMOS Drain LDD
line x loc=$"STI"+$"Lsd"+($"Ldd"*2)+$"Lg" spac=0.02
#width of NMOS Drain
line x loc=$"STI"+($"Lsd"*2)+($"Ldd"*2)+$"Lg" spac=0.02
#width of STI NP
line x loc=$"NMOS"+$"STI" spac=0.02

Initialization (III)
Define the structure mesh
#width of PMOS Source
line x loc=$"NMOS"+$"STI"+$"Lsd" spac=0.02
#width of PMOS Source LDD
line x loc=$"NMOS"+$"STI"+$"Lsd"+$"Ldd" spac=0.02
#width of pMOS hChannel
line x loc=$"NMOS"+$"STI"+$"Lsd"+$"Ldd"+($"Lg"*0.5) spac=0.02
#width of pMOS Channel
line x loc=$"NMOS"+$"STI"+$"Lsd"+$"Ldd"+$"Lg" spac=0.02
#width of PMOS Drain LDD
line x loc=$"NMOS"+$"STI"+$"Lsd"+($"Ldd"*2)+$"Lg" spac=0.02
#width of PMOS Drain
line x loc=$"NMOS"+$"STI"+($"Lsd"*2)+($"Ldd"*2)+$"Lg" spac=0.02
#width of STI P
line x loc=$"NMOS"+($"STI"*2)+($"Lsd"*2)+($"Ldd"*2)+$"Lg" spac=0.02
line y loc=1 spac=0.15

Pad OX /SiN depo

STI CMP / clean
Well
Spacer
S/D implant

Active Region Definition (I)
Pad oxide growth and nitride deposition.
# Defining the Initial Substrate
init orientation=100 c.boron=1e12 space.mul=2
#init silicon c.boron=1e14 orientation=100 two.d space.mult=2
save outf=01.str
# clean
diffus time=20 temp=1000 dryo2 press=1 hcl=3
etch oxide all
# Grow pad oxide

diffuse time=30 temp=1000 dryo2 press=1 hcl=3
save outf=02.str
# deposit nitride
deposit nitride thick=0.4 divisions=10
save outf=03.str

Active Region Definition (II)
Define the active region (STI Mask)
# spin on photoresist
deposit photoresist thick=1 POSITIVE
save outf=04.str
# STI Mask
etch photoresist start x=0.00 y=-2.00
etch cont x=$"STI" y=-2.00
etch cont x=$"STI" y=1.00
etch done x=0.00 y=1.00
etch photoresist start x=$"NMOS" y=-2.00
etch cont x=$"NMOS"+$"STI" y=-2.00
etch cont x=$"NMOS"+$"STI" y=1.00
etch done x=$"NMOS" y=1.00
etch photoresist start x=$"NMOS"+$"STI"+($"Lsd"*2)+($"Ldd"*2)+$"Lg" y=-2.00
etch cont x=$"NMOS"+($"STI"*2)+($"Lsd"*2)+($"Ldd"*2)+$"Lg" y=-2.00
etch cont x=$"NMOS"+($"STI"*2)+($"Lsd"*2)+($"Ldd"*2)+$"Lg" y=1.00
etch done x=$"NMOS"+$"STI"+($"Lsd"*2)+($"Ldd"*2)+$"Lg" y=1.00
save outf=05.str

Active Region Definition (III)
STI Etch
# etch nitride
etch nitride dry thick=0.5
save outf=06.str
# etch oxide
save outf=07.str
#
#etch photoresist all
strip photo
save outf=08.str
# etch silicon
rate.etch machine=trench_etch rie silicon iso=0.1 dir=0.9 u.m
rate.etch machine=trench_etch rie oxide iso=0.1 dir=0.9 u.m
etch machine=trench_etch time=0.42 minute dx.mult=0.5
save outf=09.str

Active Region Definition (IV)
HDP deposition (USG) and CMP
# Grow barrier oxide (USG)
deposit oxide thick=0.55 div=10
save outf=10.str
# CMP USG
rate.polish machine=CMP oxide u.h max.hard=3 min.hard=3 isotropical=0.5
polish machine=CMP time=9.6 minutes
save outf=11.str
# strip nitride and pad oxide
strip nitride
etch oxide above p1.y=0.031
save outf=12.str
# Grow screen oxide

deposit oxide thick=0.021 div=10
save outf=13.str
save outf=14.str

Pad OX /SiN depo

STI CMP / clean
Well
Spacer
S/D implant

Well Implantation (I)
Define N-Well
# N-Well mask
etch photoresist start x=$"NMOS"+$"STI" y=-2.00
etch cont x=$"NMOS"+$"STI"+($"Lsd"*2)+($"Ldd"*2)+$"Lg" y=-2.00
etch cont x=$"NMOS"+$"STI"+($"Lsd"*2)+($"Ldd"*2)+$"Lg" y=1.00
etch done x=$"NMOS"+$"STI" y=1.00
save outf=15.str
# N-Well implant phosphorus
implant phosphor dose=8e12 energy=70 tilt=7 pearson fullrot crystal
save outf=16.str
# strip photoresist
strip photo
save outf=17.str
# Anneal and drive-in
diffus temp=950 time=30
save outf=18.str
diffus time=20 temp=1000 press=0.10 hcl=3
save outf=19.str

Well Implantation (II)
Define P-Well
save outf=20.str
# P-Well Mask
etch photoresist start x=$"STI" y=-2.00
etch cont x=$"NMOS" y=-2.00
etch cont x=$"NMOS" y=1.00
etch done x=$"STI" y=1.00
save outf=21.str
# P-Well implant boron

implant boron dose=8e12 energy=25 tilt=7 pearson fullrot crystal
save outf=22.str
# strip photoresist
strip photo
save outf=23.str

Well Implantation (III)
Well annealing and drive-in
# Anneal and drive-in
save outf=24.str
diffus time=50 temp=20 press=0.10 hcl=3
save outf=25.str
# clean and etch screen oxide

save outf=26.str
# Grow sacrificial oxide

deposit oxide thick=0.01 divisions=5
save outf=27.str
save outf=28.str

Well Implantation (IV)
N-channel Vt adjust implant
# Reuse the P-Well mask
save outf=29.str
# vt n-channel adjust implant
implant phosphor dose=1e12 energy=10 tilt=30 pearson fullrot crystal
save outf=30.str
# strip photoresist
strip photo
save outf=31.str
# RTA
diffuse temp=1000 time=5
save outf=32.str

Well Implantation (V)
P-channel Vt adjust implant
save outf=33.str
#Reuse the N-Well mask

save outf=34.str
# vt p-channel adjust implant
implant boron dose=1e12 energy=10 tilt=30 pearson fullrot crystal
save outf=35.str
# strip photoresist
strip photo
save outf=36.str
# RTA
save outf=37.str
Pad OX /SiN depo

STI CMP / clean
Well
Spacer
S/D implant

Gate Stack Formation (I)
Gate oxide growth and polyslilcon deposition
#clean and sacrificial oxide
save outf=38.str
# Grow gate oxide

save outf=39.str
# deposit polysilicon
deposit poly thick=0.2 div=10
save outf=40.str
save outf=41.str

Gate Stack Formation (II)
Polysilicon etching to define polygate
# Gate mask
etch photoresist start x=0.00 y=-2.00

etch cont x=$"STI"+$"Lsd"+$"Ldd" y=-2.00
etch cont x=$"STI"+$"Lsd"+$"Ldd" y=1.00
etch photoresist start x=$"STI"+$"Lsd"+$"Ldd"+$"Lg" y=-2.00

etch cont x=$"NMOS"+$"STI"+$"Lsd"+$"Ldd" y=-2.00
etch cont x=$"NMOS"+$"STI"+$"Lsd"+$"Ldd" y=1.00
etch done x=$"STI"+$"Lsd"+$"Ldd"+$"Lg" y=1.00
etch photoresist start x=$"NMOS"+$"STI"+$"Lsd"+$"Ldd"+$"Lg" y=-2.00

etch done x=$"NMOS"+$"STI"+$"Lsd"+$"Ldd"+$"Lg" y=1.00

Gate Stack Formation (III)
Polysilicon etching to define polygate
# Gate mask
etch poly start x=0.00 y=-2.00

etch cont x=$"STI"+$"Lsd"+$"Ldd" y=-2.00
etch cont x=$"STI"+$"Lsd"+$"Ldd" y=1.00
etch poly start x=$"STI"+$"Lsd"+$"Ldd"+$"Lg" y=-2.00

etch cont x=$"NMOS"+$"STI"+$"Lsd"+$"Ldd" y=-2.00
etch cont x=$"NMOS"+$"STI"+$"Lsd"+$"Ldd" y=1.00
etch done x=$"STI"+$"Lsd"+$"Ldd"+$"Lg" y=1.00
etch poly start x=$"NMOS"+$"STI"+$"Lsd"+$"Ldd"+$"Lg" y=-2.00

etch done x=$"NMOS"+$"STI"+$"Lsd"+$"Ldd"+$"Lg" y=1.00
save outf=42.str

Gate Stack Formation (IV)
PolySilicon annealing and oxidation
# strip photoresist
strip photo
save outf=43.str
# PolySi anneal/oxidation
save outf=44.str
save outf=45.str

Pad OX /SiN depo

STI CMP / clean
Well
Spacer
S/D implant

Source/Drain Implantation (I)
N-channel lightly doped S/D implantation with phosphorus.
# n-channel LDD msak
save outf=46.str
# n-channel LDD doping

implant phosphor dose=3.0e13 energy=12 tilt=7 pearson fullrot crystal
save outf=47.str
# strip photoresist
strip photo
save outf=48.str

Source/Drain Implantation (II)
N-channel lightly doped S/D implantation with boron.
save outf=49.str
# P-channel LDD msak

save outf=50.str
# P-channel LDD doping

implant boron dose=3.0e13 energy=4 tilt=7 pearson fullrot crystal
save outf=51.str
#strip photoresist
strip photo
save outf=52.str

Source/Drain Implantation (III)
Nitride spacer
# thermal oxide
save outf=53.str
# deposit nitride spacer

deposit nitride thick=0.1 divisions=10
save outf=54.str
# etching nitride turns into nitride spacer

etch nitride dry thick=0.11
save outf=55.str
save outf=56.str

Source/Drain Implantation (IV)
Heavily doped S/D implantation with arsenic (N+ Mask).
# n-channel S/D n+ mask
save outf=57.str
# n-channel S/D n+ doping

implant arsenic dose=5.0e15 energy=50 tilt=74 fullrot crystal
save outf=58.str
#strip photoresist
strip photo
save outf=59.str
# RTA
save outf=60.str

Source/Drain Implantation (V)
Heavily doped S/D implantation with boron (P+ Mask).
#spin on photoresist
save outf=61.str
# p-channel S/D n+ mask

save outf=62.str
# p-channel S/D n+ doping

implant boron dose=5.0e15 energy=20 tilt=74 fullrot crystal
save outf=63.str
# strip photoresist
strip photo
save outf=64.str

Source/Drain Implantation (VI)
Rapid thermal annealing (RTA) and oxide etching
# RTA
save outf=65.str
# etch oxide
save outf=65.str
#

Metal-Oxide-Semiconductor Capacitor
(MOSC)

(MOSC)
MOS capacitor under applied bias.
Threshold Voltage.
C-V Characteristics.
The Impact of Interface Traps, Dit.
TCAD Simulation for MOSCs and their C-V Characteristics.
 C-V with and without Quantum Mechanical Model.
 The Effect of Substrate Doping Concentration.
 The Impact of Interface Traps, Dit.
 Polygate Depletion.
 Gate Oxide Direct Tunneling Leakage.

Objectives
Structure of MOS capacitors
MOS capacitor at equilibrium.
Flat-band condition and flat-band voltage
MOS capacitor under applied bias
Surface accumulation
Surface Depletion
Surface Inversion
Threshold Voltage
C-V Characteristics
Split C-V Measurement
Real C-V curve
Oxide charges
Interface traps

Structure of MOS Capacitors and MOSFET
MOS Capacitor MOS Field Effect Transistor

MOS Capacitor at Equilibrium

Rules of Band Diagram
In a given material, Eg
and qχ are given. They do
not change spatially.
The vacuum level (free
electron level) is
continuous at the interface
between two different
materials.
The electric flux dendity D
(D = εE ) is continuous at
the interface between two
different materials.

Poly Gate MOS Capacitor at Equilibrium
A rather complex band diagram at Vg = 0 V

Flat-Band Condition and Flat-Band Voltage
The energy band is flat at flat-band voltage
V fb  m  s  ms

Flat-Band Condition and Flat-Band Voltage
The band is flat at flat-band Voltage

E0 : Vacuum level V fb  m  s  ms
E0 – Ef : Work function 
E0 – Ec : Electron affinity c
Si/SiO2 energy barrier

Flat-band voltage

(MOSC)
Threshold Voltage.

Gate Voltage Equation
QSi
Voltage Equation: Vg  V fb  ox  si   Cox
Charge Balance:  Qg  Qsi

Surface accumulation
Negative Bias: Vg  V fb
Ef is closer to Ev at the surface.  more holes near the surface than
bulk  ACCUMULATION
Assuming accumulation layer is very thin  ox  si Vg  V fb  ox
 Qg  Qsi  Qacc Qg  Coxox
Qacc  Cox (Vg  V fb )

Surface Depletion
Positive Bias: V fb  Vg  Vt
The holes are repelled away from the surface. A surface
depletion region is formed.
Voltage Equation: Vg  V fb  ox  si
Charge Balance:  Qg  Qsi  Qdep

Surface Depletion
Voltage Equation:Vg  V fb  ox  si
Charge Balance: Qg  Qsi  Qdep
Qg Qdep
Qg  Coxox  ox  
Cox Cox
qN aWd2
Qdep  qN aWd and Si 
2 si
qN aWd qN aWd2
Vg  V fb  ox  Si  
Cox 2 si
The depletion width Wd can be found by solving above

equation with known Vg. Si and Qdep can also be found
from Wd.

Surface Electron Concentration nsurf
We can express the electron concentration at the surface in terms of
surf (or Si), Na and p.
qSi
nsurf  n p 0 e kT

q Si ( 2 p ) 
nsurf  N a e kT
nsurf increases very rapidly

(exponentially) with Si.
nsurf  ni when Si   p ; This
point devides the depletion region
and the weak inversion region.
nsurf  N a when  Si  2 p ; This
point called the threshold voltage separate the weak inversion region
and the strong inversion region.

(MOSC)
Threshold Voltage.

Threshold Condition
Threshold (of strong inversion): nsurf = Na
i.e. (Ec–Ef)surface= (Ef – Ev)bulk
that is A=B, and C = D
At threshold, we have
Si = 2p
kT  N a 
p   ln 
q  ni 

Threshold Voltage
The threshold voltage Vtn for NMOSFET is:
Qdep (2 p )
Vtn  V fb  si  ox  V fb  2 p 
Cox
2 si qN a (2 p )
Vtn  V fb  2 p  V fb  m  s  ms
Cox
kT  N a 
p   ln 
q  ni 
The threshold voltage Vtp for PMOSFET is:

2 si qN d 2n
Vtp  V fb  2n  V fb  m  s  ms
Cox
kT  N d 
n  ln 
q  ni 

Max. Depletion Width in MOS
In contrast to p-n junctions, Wd reaches a maximum value
Wdm at the onset of strong inversion.
4 si kTn( N a / ni )
2 si (2 p ) kT N Wdm 
Wdm 
qN a
 2 p  2 n a
q ni  q2 Na
This defines the threshold

condition of a MOSFET.
Wdm also plays a key role in
the short-channel scaling of
a MOSFET, namely, Lmin ∝
Wdm.

Threshold Voltage Vs Body doping density

Surface Inversion
Large Positive Bias: Vg  Vt
Vg  V fb  ox  2 p
Qdep  Qinv
ox  
Cox
Qdep  Qinv
Vg  V fb    2 p
Cox
Qdep
Qinv
Vg  V fb  2 p  
Cox Cox
Qinv  Cox (Vg  Vt )

Depletion Width
qN aWd qN aWd2
Vg  V fb  ox  Si  
Cox 2 si

Surface Potential
 si qN a
  si   2   si   Vg  V fb   0
2
2
2Cox
 si qN a  si qN a
si   2
 2
 (Vg  V fb )
2Cox 2Cox

Charges on the Silicon
Qacc  Cox (Vg  V fb )
 si qN a  Si
2 2 2
q Na
Qdep    2 si qN a (Vg  V fb )
Cox Cox
Qinv  Cox (Vg  Vth )

(MOSC)
Threshold Voltage.

MOS CV Characteristics
dQg dQSi
C 
dVg dVg

Surface Accumulation
Vg  V fb

Surface Inversion
Vg  Vt

Surface Depletion
The width of the depletion Wd: Cox
Cg 
2
qN aWd qN aWd2 2Cox (V g  V fb )
Vg  V fb   1
Cox 2 si  Si qN a
2
 Wd  1  Wd  2(Vg  V fb )
   2    0
  si  Cox   si   si qN a
Wd 1 1 2(Vg  V fb )
  
 si Cox Cox  si qN a
1 1 2(Vg  V fb ) 1 1 1 1 Wd
     
Cg 2
Cox  Si qN a C g Cox CSi Cox  Si
Cox
Cg 
2
2Cox (V g  V fb )
1
 Si qN a V fb  Vg  Vt

Surface Depletion
V fb  Vg  Vt Cg 
Cox
2
2Cox (V g  V fb )
1
 Si qN a
1 1 1 1 Wd
   
C g Cox CSi Cox  Si

MOSC CV Characteristics

High Frequency C-V of MOSC

High Frequency C-V of MOSFET

C-V Curves

Quasi-Static C-V of MOS Capacitor
The quasi-static C-V is obtained by the application of a slow linear-

ramp voltage (< 0.1V/s) to the gate, while measuring Ig with a very
sensitive DC ammeter. C is calculated from Ig = C·dVg/dt. This allows
sufficient time for Qinv to respond to the slow-changing Vg .

Split C-V Measurement
V2
dQ
C  Q(V2 )  Q(V1 )   CdV
dV V1

(MOSC)
Threshold Voltage.

Oxide Charges
Oxide Charges–a modification to Vfb and Vt
Flat-band condition (no band bending at body surface)
without any oxide charge (left); and with Qox at the oxide–
substrate interface (right). Q Q
V fb  V fb0  ox  ms  ox
Cox Cox

Types of oxide charge:
Fixed oxide charges, Si+.

Mobile oxide charges, due to Na+ and K+ contamination.
Interface traps, neutral or charged depending on Vg.
Voltage/temperature stress induced charge and traps--a
reliability issue.

Example
Interpret these measured Vfb of three capacitors with
different oxide thicknesses. The gate electrode is N+ poly-
silicon.
What does it tell us? Body work function? Doping type?
Other?
Qox
V fb  ms  tox
 ox

Channel Doping Profile Evolution
1 qD
VTh  V fb  2B  2 Si qN a 2B  I
Cox Cox
 tox 
VTh  V fb  1  6  (2B )
 Wd 
 t 
VTh  V fb  1  3 ox  (2B )
 Wd 

Poly Depletion
1 1
 1 1   tox Wdpoly 
C      
 Cox C poly 
    ox s 
 ox
C
Wdpoly
tox 
3
Qinv  C Vg  Vtp 

Poly Depletion
 ox
 1 
1
 tox Wdpoly 
1 Cg 
Cg   
1
 
Wdpoly
C    tox 
 ox C poly  
 ox  s  3
 Si qN poly
C poly 
 Si
 Qinv  qN polyWdpoly  Cox Vg  VTh 
Wdpoly Cox (Vg  VTh )
 Cox2
(Vg  VTh ) 

C g  Cox 1 
  Si qN poly 


Poly depletion
Poly-gate depletion degrades MOSFET current and circuit
speed.
How can poly-depletion be minimized?

Quantum Confinement Effect
Quantum confinement of the inversion carriers in the
suface triangular well lead to the formation of the discrete
energy level and different centroid of carrier distribution
n(x).

Charge-Layer Thickness
Average inversion-layer location below the Si/SiO2
interface is called the inversion-layer thickness, tinv.
Wdpoly tinv
toxe  tox  
3 3

Equivalent circuit
Equivalent circuit for understanding the C–V curve in
the depletion region and the inversion region. (a) General
case for both depletion and inversion regions; (b) in the
depletion regions; (c) Vg ≈ Vt; and (d) strong inversion.
General case Depletion regions Vg ≈ Vt Strong inversion

Wdm tox design plan

Boron Penetration and Gate leakage
Boron penetration effects for pFET and high gate tunneling
leakage current are two limitations for gate dielectric scaling.
Oxynitride gate dielectric can prevent B diffusion and
reduce gate leakage.
3-5% N in gate oxide prevent B diffusion.

Gate Tunneling Leakage Current

Fowler-Nordheim tunneling (High field) Current
4 2 me* 3B
3 2  tox
q me V 2 2
J ox 3 q Vox
e
8 hme  B t
* 2
ox


 AEox2 e Eox
 J   1
 
Log  2   LogA 
 Eox  2.3 Eox

Fowler-Nordheim (F-N) Plot

Fowler-Nordheim Tunneling to Direct Tunneling
Onset of the direct tunneling for tox ~ 40Å

Direction tunneling (Low field) Current
2m
 q B t ox
  B Ltunnel  2
J e e
Important parameters: m B tox
 
3
 Vox  
  1 1  
2
Eox 
  B  
J  AE oxe
q 3me 4 2me* 3B
A and 
8hme* B 3  2q 2

Direction tunneling (Low field) Current

For SiO2 films thinner than 1.5nm, tunneling leakage

current has become the limiting factor.
HfO2 has several orders lower leakage for the same EOT.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

Replacing SiO2 with HfO2---High-k Dielectric
(After W. Tsai et al., IEDM’03)
HfO2 has a relative dielectric constant (k) of ~24, six times

large than that of SiO2.
For the same EOT, the HfO2 film presents a much thicker
(albeit a lower) tunneling barrier to the electrons and holes.
Toxe can be further reduced by introducing metal-gate
technology since the poly-depletion effect is eliminated.
Jg/EOT Scaling Trajectory
Existence of base oxide (interfacial oxide) significantly
affects on the scalability of HfO2 for 32 nm and beyond.
IEEE TRANSACTIONS ON ELECTRON DEVICES, P. 1027, 2003

The Use of High K Dielectric

Jg/EOT Scaling Trajectory
• Existence of base oxide (interfacial oxide) significantly
affects on the scalability of HfO2 for 32 nm and beyond.
IEEE TRANSACTIONS ON ELECTRON DEVICES, P. 1027, 2003

Choices of high-k Dielectric
R. Hauser, IEDM Short Course, 1999

Band Gap Vs K
Band gap of high-k materials are inversely proportional to the k-value.

Recent MOS (CMOS) Technology
High k dielectric to replace SiO2 and metal gate to
replace PolySi gate in Recent CMOS technology

Gate Workfunction
• We need WF around 5.17 eV for PMOS and WF around
4.05 eV for NMOS.

(MOSC)
Threshold Voltage.

MOS Capacitors (MOSC)

MOS Capacitors
Simulation Steps for MOScap.
Step:
(1) Define MOS Structure
1. Define Device Parameter
2. Define Structure
a. Mesh
b. Region
c. Electrode
d. Doping
(2) Electrical analysis
1. Define Contact
2. Select Models
3. Solve Methods
4. Bias conditions (C-V)
(3) Experimental project
1. Show the MOS structure, mesh and doping profile
2. Show the CV-curve with quantum model.

MOS Capacitors (I)
Define Device Parameter.
#MOSFET C-V curve example
go atlas simflag="-P 4“
#set parameter
set Lg=0.1
set Tb=0.5
#set Lsd=0.03
#set hLsd=$"Lsd"*0.5
set Tox=-0.002
set Tpoly=-0.1
set Nb=5e17
#set Nsd=7e19
#set xj=0.05
#set Vd=0
set Vg=5
set 1000Lg=$"Lg"*1000
#set Et=acceptor
set wf=4.17

MOS Capacitors (II)
Define Structure.
#save mesh
mesh outf=NMOS_$"1000Lg"nm_mesh.str
#Define structure
#x.mesh
x.m loc=0.0 spacing=0.01
x.m loc=$"Lg" spacing=0.005
#y.mesh
y.m loc=($"Tox")+($"Tpoly") spacing=0.01
y.m loc=$"Tox" spacing=0.001
y.m loc=0 spacing=0.0001
y.m loc=$"xj" spacing=0.005
y.m loc=$"xj"+0.06 spacing=0.01
y.m loc=$"Tb“ spacing=0.02

MOS Capacitors (III)
Define Structure.
#define region
region num=1 silicon y.min=0.0
region num=2 oxide y.max=0.0
electrode name=gate number=3 x.min=0 x.max=$"Lg" y.min=($"Tox")+($"Tpoly") /

y.max=$"Tox“
electrode name=base bottom
#define doping
doping uniform conc=$"Nb" p.type x.left=0 x.right=$"Lsd"+$"Lg"+$"Lsd" y.top=0 /
y.bottom=$"Tb" direction=y
#save structure
save outf=MOS_$"1000Lg"nm_quantum.str

MOS Capacitors (IV)
Define Contact and Select Models.
# Set the workfunction of the Poly gate
CONTACT NAME=gate workfunction=4.17

models cvt srh print BBT.STD n. quantum p. quantum
#trap
#inttrap $"Et" e.level=0.4 density=4.65e12 degen=1 sign=1e-14 sigp=1e-14 x.min=$"Lsd"
x.max=$"Lsd"+$"Lg" y.min=0 y.max=0 fast
#solve
method newton carriers=2 maxtrap=10
solve outfile=MOS_$"1000Lg"nm_CV.str master
output QFN QFP CHARGE CON.BAND VAL.BAND E.MOBILITY H.MOBILITY

E.VELOCITY H.VELOCITY J.DRIFT J.DIFFUSION J.TOTAL TRAPS t.quantum

MOS Capacitors (V)
Solve accumulation and inversion C-V curves.
#CV Cruve
#solve vdrain=0
#solve vdrain=0 vstep=0.1 vfinal=$"Vd" name=drain
log outfile=MOS_CV_$"1000Lg"nm_Vd$"Vd"_accumulation_quantum.log master
solve vgate=0 vstep=-0.1 vfinal=-$"Vg" name=gate ac freq=1e6 direct
save outf=MOS_CV_$"1000Lg"nm_Vd$"Vd"_accumulation_quantum.str
log off
load infile=MOS_$"1000Lg"nm_CV_quantum.str master

solve
#solve vdrain=0
#solve vdrain=0 vstep=0.1 vfinal=$"Vd" name=drain
log outfile=MOS_CV_$"1000Lg"nm_Vd$"Vd"_inversion_quantum.log master
solve vgate=0 vstep=0.1 vfinal=$"Vg" name=gate ac freq=1e6 direct
save outf=MOS_CV_$"1000Lg"nm_Vd$"Vd"_inversion_quantum.str

MOS Capacitors (VI)
C-V Characteristics Extraction.
#extract
extract init inf="MOS_CV_$"1000Lg"nm_Vd$"Vd"_accumulation_quantum.log"
extract name="tox_accumulation_quantum" (3.9*8.85e-
18*$"Lg")/abs(max(c."gate""gate"))
extract init inf="MOS_CV_$"1000Lg"nm_Vd$"Vd"_inversion_quantum.log"
extract name="tox_inversion_quantum" (3.9*8.85e-18*$"Lg")/abs(max(c."gate""gate"))
quit

MOS Capacitors (VII)
Solve accumulation and inversion C-V curves.

MOS Capacitors (XIII)
C-V and I-V Characteristics with and without Quantum Model.
C-V Id-Vg
2.2
-3
Lg=0.13m 10
Lg=0.13m
2.0 10-4
-5
10 Vd=1V
1.8 10-6
Drain Current (A/m)

10-7
Capacitor (fF/m2)
1.6 10
-8
w/o QM 10-9
1.4 w QM -10
10
10-11
1.2 w/o QM
10-12
-13
w QM
1.0 10
10-14
-15
0.8 10
10-16
0.6 10-17
-5 -4 -3 -2 -1 0 1 2 3 4 5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Gate Voltage (V) Gate Voltage (V)

MOS Capacitors (IX)
Carrier Concentration with and without Quantum Model.
Hole conc. Electron conc.
22 22
Electron Concentration (1/cm3)
Electron Concentration (1/cm3)

20 20 Classical
Classical Quantum
Quantum
18 18
16 16
-0.005 0.000 0.005 0.010 0.015 0.020 0.025 -0.005 0.000 0.005 0.010 0.015 0.020 0.025
Distance to Oxide (m) Distance to Oxide (m)

MOS Capacitors (X)
C-V and I-V Characteristics with Various Nsub.
C-V Id-Vg
2.0
Lg=0.13m 10-3 Lg=0.13m
1.8
Vd=1V
10-5

1.6
Capacitor (fF/m2)
10-7
1.4
10-9
1.2 Nsub
Nsub 5x1016cm-3
1.0 10-11 17 -3
17 -3 1x10 cm
5x10 cm 17 -3
17 -3 5x10 cm
1x10 cm
0.8 10-13
5x1016cm-3
0.6 10-15
-5 -4 -3 -2 -1 0 1 2 3 4 5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

Metal-Oxide-Semiconductor
Field-Effect Transistors (MOSFETs)

Semiconductor Device Physics
and its TCAD Simulation
MOS Transistors (MOSFETs)
• On State Current for MOSFETs.
• Output Id-Vd Characteristics.
• Off State Current for MOSFETs.
• Transfer Id-Vg Characteristics.
• TCAD Simulation for MOSFETs and their I-V Characteristics.
– Output Id-Vd Characteristics with and without Velocity Saturation.
– Transfer Id-Vg Characteristics along with DIBL and SS.
– Transfer Id-Vg Characteristics with GIDL.
– Energy Band Diagram Profile along with Quasi Fermi Level profile.

MOS Field-Effect Transistors (MOSFETs)
On State Current for MOSFETs.
Output Id-Vd Characteristics.
Off State Current for MOSFETs.
Transfer Id-Vg Characteristics.
TCAD Simulation for MOSFETs and their I-V
Characteristics.
Output Id-Vd Characteristics with and without Velocity
Saturation.
Transfer Id-Vg Characteristics along with DIBL and SS.
Transfer Id-Vg Characteristics with GIDL.
Energy Band Diagram Profile along with Quasi Fermi
Level profile.
Objectives
Basic MOSFET structure and IV characteristics
Complementary MOS (CMOS)
Surface Mobilities
MOSFET Vt and Body Effect
QINV in MOSFET
Basic MOSFET IV Model
Strain Silicon Technologies
Nanosheet FETs
Velocity Saturation
MOSFET IV Model with Velocity Saturation
Parasitic Source-Drain Resistance
Extraction of the Series Resistance and the Effective
Channel Length
MOS Transistor
The MOSFET (MOS Field-Effect Transistor) is the
building block of Gb memory chips, GHz microprocessors,
analog circuits, and RF cellular phones.
Match the following MOSFET characteristics with their

applications:
Small Size
High Speed
Low Power
High Gain

Basic MOSFET structure and IV characteristics
What is desirable: Large Ion and Small Ioff

Early Patents on the Field-Effect Transistor
In 1935, a British patent was issued to Oskar Heil. A
working MOSFET was not demonstrated until 1955.
Using today's terminology, what are 1, 2, and 6?

Yesterday's MOSFETs Technology
Polysilicon gate and 1.2nm SiO2
1.2 nm SiO2 used in production. Leakage current
through the oxide limits further thickness reduction.

Recent MOS (CMOS) Technology
High k dielectric to replace SiO2 and metal gate to
replace PolySi gate in Recent CMOS technology

Today's MOS (CMOS) Technology
From Planar FET (2D) to FinFET (3D)
Planar FET Fin FET
Transistor Fin
Images
(Intel,iedm 2014)
Gate-Cut Images (Intel,iedm 2014)

Complementary MOSFET (CMOS) Technology
NMOSFET PMOSFET

Surface Mobilities
How to measure the surface mobility? For small Vds:
Vds W
I d  WQinv v  WQinv eff  Cox (Vgs  Vt ) eff Vds
L L
L Id
eff 
W Cox (Vgs  Vt )Vds

Surface Mobilities
What do we expect the dependence of μeff on Vgs , tox , and

Na?

Surface Mobilities
Can we reconcile these three variables, i.e. Vgs , tox , and Na ,

for μeff into one variable?
Surface mobility can be thought as a function of the
average of the electric fields at the bottom and the top of
the inversion charge layer, Eb and Et .
Et  Eb 1  QB  Qinv QB 
Eeff     
2 2  si  si 
1  1 
Eeff   B
Q  Qinv 
 si  2 
QB  Cox (Vt  V fb  2 p )
Qinv  Cox (Vgs  Vt )

Surface Mobilities
The average of the electric fields, Eeff .
  ox 1
Cox  ox 
tox  Si 3
Vt  V fb  2 p Vgs  Vt
Eeff  
3tox 6tox
Vgs  Vt  2V fb  2  2 p
Eeff 
6tox
Vgs  Vt  0.2
Eeff 
6tox

Universal Surface Mobilities
Surface roughness scattering is stronger (mobility is lower)
at higher Vg, higher Vt, and thinner tox.
Vgs  Vt  0.2
Eeff 
6tox

Example
What is the surface mobility at Vgs=1 V in an N-channel
MOSFET with Vt=0.3 V and tox=2 nm?
Solution:
Vgs  Vt  0.2 (1  0.3  0.2) V
Eeff  
6tox 6  2 nm
Vgs  Vt  0.2 (1  0.3  0.2) V 1.5 V
Eeff   
6tox 6  2 nm 12 10-7 cm
MV
Eeff  1.25
cm
1 MV is a megavolt (106 V). From the mobility figure,
eff=190 cm2/Vs, which is several times smaller than the
bulk mobility.

Threshold Voltage
How to Measure the threshold Vt of a MOSFET
Method A. Vt is measured by extrapolating the Ids versus Vgs curve to

Ids=0. W
I d  Cox (Vgs  Vt ) eff Vds  (Vgs  Vt )
L
Method B. Vt is the Vgs at which Ids = 0.1 μA × W/L.

The Body Effect
Two capacitors  two charge components:
Qinv  Cox (Vgs  Vt )  CSiVbs
Qinv  Cox (Vgs  Vt )  CSiVsb
  CSi 
Qinv  Cox Vgs  Vt  Vsb  
  Cox 
Redefine Vt as:
CSi
Vt (Vsb )  Vt 0  Vsb  Vt 0  Vsb
Cox

The Body Effect
Body effect: Vt is a function of Vsb. When the source-body
junction is reverse-biased, Vt increases.
Body effect coefficient:
Vt (Vsb )  Vt 0  Vsb
CSi tox
 3
Cox Wd
Body effect slows down circuits?

How can it be reduced?

Uniform Body Doping
When the source/body junction is reverse-biased, there are
two quasi-Fermi levels (Efn and Efp) which are separated
by qVsb. An NMOSFET reaches threshold of inversion
when Ec is close to Efn , not Efp . This requires the band-
bending to be 2B + Vsb , not 2B.
2q Si N a
Vt  Vt 0 
Cox
 (2B  Vsb )  2B 
Vt  Vt 0    (2B  Vsb )  2B 
g is the body-effect parameter.

MOS Field-Effect Transistors (MOSFET)
Characteristics.
Saturation.
Level profile.
Qinv in MOSFET
Channel voltage Vc = Vs at x = 0 and Vc = Vd at x = L.
Qinv:
Qinv  Cox Vgs  Vcs  Vt 0  Vcb 
Qinv  Cox Vgs  Vcs  Vt 0   (Vsb  Vcs ) 
Qinv  Cox Vgs  Vcs  (Vt 0  Vsb )  Vcs 

Qinv  Cox Vgs  (Vt 0  Vsb )  (1   )Vcs 
Qinv  Cox Vgs  Vt  mVcs 
Where m  1   and Vt  Vt 0  Vsb

m is called the body-effect factor or bulk-charge factor.

Basic MOSFET I-V Model
I ds ( x)  W  Qn ( x)  v( x)  W  Qn ( x)  eff E
       
dVcs
 eff Cox Vgs  Vt Vds  Vds
W  m 2  dsI ( x ) W C V
ox gs Vt mV cs eff
I ds dx
L  2 

L
0 ds
I ( x )dx  L
0 WC V
ox gs  Vt  mV  
cs eff
dVcs
dx
dx
 1 
I ds  L  WCox eff Vgs  Vt  mVds Vds
 2 
eff Cox Vgs  Vt  mVds Vds

W 1
I ds 
L  2 
 eff Cox Vgs  Vt Vds  Vds 

W  m 2
I ds
L  2 

Drain Saturation Voltage and Saturation Current
Drain Saturation Voltage Vdsat

dI ds
dVds
W

 0  eff Cox Vgs  Vt  mVds
L

V gsVt
 Vdsat 
m
Drain Saturation current Idsat
I dsat 
1W
eff Cox
Vgs  Vt 2
2L m

Intuitive DC I-V characteristics

Intuitive DC I-V characteristics

Saturation Current and Transconductance
Drain Saturation current Idsat
I dsat 
1W
eff Cox
Vgs  Vt 2
2L m
Drain Saturation
Transconductance gmsat
dI dsat W Vgs  Vt
g msat   eff Cox
dVgs L m

Inverter Speed - Impact of Ion
1
 d  (pull - down delay  pull - up delay)
2
CVdd
pull - down delay 
2 I dsatn
CVdd
pull - up delay 
2 I dsatp
CV  1 1 
 d  dd   
4  I dsatn I dsatp 
How can the speed of an inverter circuit be improved?

The Need of Mobility Enhancers

The Mobility Vs The Energy Gap
From left to right, III–V compounds

are InSb, InAs, In0.53Ga0.47As, InP,
GaAs, In0.49Ga0.51P, and GaN
F. Schwierz, Nat. Nanotechnol. 5, 487 (2010)

Strain and Stress

Strained Silicon – Biaxial strain
J. Hoyt, MIT

Effect of biaxial strain on Silicon energy bands
J. Hoyt, MIT

The E(x) Energy Band Model
Energy Gap EG
Conduction Band Edge EC
Valence Band Edge EV
Vacuum Level
Electron Affinity

Biaxial Strain

Strained Si to enhance the mobility

Strained Si to enhance the mobility

Strain-dependence of mobility
K. Rim et al., IEDM, 2003

Poor Hole Mobility Gain
At high Eeff , the LH-HH separation is reduced and the hole

mobility gain is lost.
K. Rim et al., IEDM, 2003

Uniaxial and Biaxial Stress

Uniaxial Strain

Uniaxial Strain

Contact-Etch-Stop-Liner (CESL) Technology
NMOS: Longitudinal tensile + vertical compressive stress

PMOS: Longitudinal compressive + vertical tensile stress
H. Yang et al., IEDM, 2004

Stress-Memorization-Technology (SMT)
SMT induced mask-edge dislocation
K. Lim et al., IEDM, 2010

Strain Mobility Enhancement
• Embeded SiGe source/drain has been the leading strain

enhancer since 90 nm node.
• Many strain enhancement techniques have been proposed
for NMOS transistor.
From 2019 Symp. of VLSI Technology and Circuits Short Course 1

Evolution of SiGe Source/Drain Enhancer
• Ge concentration has been increased to 50%.

• SiGe Source/Drain continue to be performance enhancer
for FinFET.
From 2019 Symp. of VLSI Technology and Circuits Short Course 1

Velocity Saturation
Velocity saturation has large and deleterious effect on the
Ion of MOSFETS.
eff E
v E < Esat
E
1
E sat
= vsat E > Esat
2vsat
E sat 
n

eff E ( y )

I d  I d ( y )  WQ ( y )v( y )  WCox Vgs  Vt  mVc ( y )  E ( y)
1
Esat
L 
0 I d 1 
E ( y) 
 
dy  0L WCox Vgs  Vt  mVc ( y ) eff E ( y )dy
 Esat 
L 
0 I d 1 
1 dVc 
 dV
dy  0L WCox Vgs  Vt  mVc ( y ) eff c dy
 Esat dy  dy
Id L  Id
Vds 
 1
 2
 Weff Cox  Vgs  Vt Vds  mVds 
Esat  2
 
eff Cox Vgs  Vt )Vds  mVds2 
W 1
Id 
 Vds   2 
L1  
 Esat L 

 
eff Cox Vgs  Vt )Vds  mVds2 
W 1
Id 
 V   2 
L1  ds 
 Esat L 
 
eff Cox Vgs  Vt )Vds  mVds2 
1 W 1
Id 
V
1  ds L  2 
Esat L
Long channel I d
Id 
Vds
1
Esat L

Drain Saturation Voltage and Current
From the following 2 relations:
W  1 
I ds  eff Cox  Vgs  Vt )Vds  mVds2  
 V   2 
L 1  ds 
 Esat L 
I ds  WCox Vgs  Vt  mVds  vsat
W  1 2 
I dsat  eff Cox  Vgs  Vt )Vdsat  mVdsat 
 V   2 
L 1  dsat 
 Esat L 
I dsat  WCox Vgs  Vt  mVdsat  vsat

Saturation Current Idsat 1
Vgs  Vt 2
I dsat  Wv satCox m
Vgs  Vt   E L
sat
m
1 m 1
Saturation Voltage Vdsat  
Vdsat Vgs  Vt E sat L

PMOS and NMOS I-V Characteristics
The PMOS I-V is qualitatively similar to the NMOS I-V, but the
current is about half as large. How can we design a CMOS
inverter so that its voltage transfer curve is symmetric?

Measured MOSFET I-V
Long-channel Short-channel
What is the differences between these two (long- and short-

channel length) I-V curves?

Output Conductance
Idsat does NOT saturate in the saturation region, especially
in short channel devices!
The slope of the Ids-Vds curve in the saturation region is
called the output conductance (gds),
I d
gd 
Vds
A smaller gds is desirable for

a large voltage gain, which
is beneficial to analog and
digital circuit applications.

Characteristics.
Saturation.
Level profile.
Objectives
Subthreshold current
Charges in Silicon
Qinv in weak inversion
Subthreshold current
Si and Vgs
Subthreshold swing
Drain Induced Barrier Lowering (DIBL)
Leakage Currents
Gate Induced Drain Leakage (GIDL)

Subthreshold Current
The leakage current that flows at Vg<Vt is called the
subthreshold current.
The current at Vgs = 0 and Vds = Vdd is called Ioff.
90nm technology.
Gate length: 45nm
Vt = 0.35V Vt = 0.35V

The subthrshold current is mostly diffusion current.

The Subthreshold Behavior
Subthreshold current is one of the most important

concerns in the scaled device design. It determines the
standby power and the power supply voltage Vdd.
The substhreshold swing St is the amount of gate needed to
reduce the subthreshold current by 10.
A small St is desirable such that smaller can Vdd be
applied for low power (i.e. low voltage) CMOS
approximation.

Charges in Si
The Poisson's equation:
d 2 dE q
     p( x)  n( x)  N d  N a 
dx 2
dx  Si
p( x)  p0e q / kT n( x)  n0e q / kT
d 2 q  q / kT  q / kT
  
 p ( e  1)  n ( e  1) 
dx 2
 Si 0 0
d 2 1 d  d 
2
  
dx 2
2 d  dx 
Si Si
  qkT q Si    qkT q Si 
QSi   2 si kT  p0  e   1  n0  e   1
 kT   kT 
Charges in Si
Si Si
  qkT q Si    qkT q Si 
QSi   2 si kT  p0  e   1  n0  e   1
 kT   kT 
q
q Si ni2  kTSi
QSi   2 Si kTN a  2e
kT Na

Qinv in Weak Inversion
q
QSi  Qdep  Qinv   2 Si kTN a  2e
kT Na
q
Na  e
kT Na
 Si qN a kT ni2  qkT
Si
QSi   2 Si qN aSi  e
2 Si q N a 2
Qdep   2q Si N aSi
 Si qN a kT ni2  qkT
Si
Qinv   e
2 Si q N a 2

VDS
dVc W
I D ( y )   nWQinv (Vc )
dy
I D   n
L   Q
0
inv (Vc ) dVc
 Si qN a kT ni2  q (kTV )
Si c
Qinv   e
2 Si q N a 2
2 2 qSi  qV 
W  Si qN a  kT   ni    ds
1  e kT 
I Dst   eff     e kT
L 2 Si  q   Na   
 
2
 Si qN a  kT   ni   qkT
2
W kT Si
I Dst  eff     e when Vds  3

L 2 Si  q   N a  q

Si in terms of Vgs
2 Si qN aSi
Vgs  V fb   Si 
Cox
 si qN a  si qN a
Si   2
 2
 (Vgs  V fb )
2C ox 2C ox
Vgs  VT  m(Si  2B )

Si in terms of Vgs
Vgs  VT  m(Si  2 B )
 Si qN a
CSi 3tox 2(2 B )
m  1  1 ＝1 
Cox Wdm Cox
d Si Cox 1
 
dVg Cox  CSi m
Vgs  VT
Si  2 B 
m
Subthrehold Current
2
 Si qN a  kT   ni   qkT
2
W Si
I Dst  eff     e
L 2 Si  q   N a 
Vgs  VT
Si  2 B 
m  Si qN a
 Si qN a 2(2 B )
＝(m  1)Cox m  1
2(2 B ) Cox
2 q (Vgs Vth )
W  kT  
I Dst  eff Cox (m  1)   e mkT
L  q 

Subthreshold Leakage Current IDst.
qSi q  Vgs  qVgs
 constant  
 
I Dst  ns  e e  e mkT
kT kT 
qVgs CSi
m  1
I dst  e mkT Cox
Subthreshold current changes 10× for m × 60mV change in

Vgs
60mV is (ln10)·kT/q
Subthreshold swing S: the change in Vgs corresponding to
10× change in subthreshold current. S = m × 60mV,
typically 80-100mV.

Practical definition of Vt: the Vgs at which Ids= 100nA×W/L.
qVgs
I dst  Ke mkT
qVt
W
100nA   Ke mkT
L
q (Vgs Vt )
 W
I dst  100nA  e mkT
 L
Ioff is determined only by Vt and subthreshold swing S.

q (0Vt ) qVt
 W  mkT  W 
I off  100nA   e  100nA  e mkT
 L  L

Subthreshold Swing
Subthreshold swing S:  C 
S  1  Si   60 mV
 Cox 
Smaller S is desirable (lower Ioff for a given Vt). Minimum
possible value of S is 60mV/dec.
How do we reduce swing?
Thinner tox  larger Cox
Lower substrate doping  smaller CSi
Lower temperature
Limitations
Thinner tox ― oxide breakdown reliability or oxide leakage current.
Lower substrate doping ― doping is not a free parameter but set by Vt.

Effect of Interface States on Subthreshold Swing
Vg1
Vg2>Vg1
Interface states may be filled by electrons or empty

depending on its energy relative to EF, i.e., depending on Vg.
dQint/d  s (number or interface state per eV-cm2) presents
another capacitance in  Cdep  dQint / ds 
parallel with Cdep S  60mV  1  
 Coxe 

Gate Induced Drain Leakage (GIDL)
Gate Drain Overlap
210  7
VGD  1.2 
E Si  I dGIDL  e ESi
t ox

MOSFET Design Space
L L L
tox ,max  ＝ 
6m 21 20
m 1
If tox limit is 1 nm (QM tunneling), then

gate length limit is 20 nm.

Characteristics.
Saturation.
Level profile.
MOSFETs (I)
Simulation Steps for MOSFET.
Step:
(1) Define MOSFET Structure
1. Define Device Parameter
2. Define Structure
a. Mesh
b. Region
c. Electrode
d. Doping
(2) Electrical analysis
1. Define Contact
2. Select Models
3. Solve Methods
4. Bias conditions (Id-Vg or Id-Vd)
(3) Experimental project
1. Show the MOSFETs structure, mesh and doping profile
2. Show the MOSFETs IV-curve and Band-diagram

MOSFETs (II)
Device Parameter.
#MOSFET example
go atlas simflag="-P 4“
#set parameter
Set Lg=0.13
Set Tb=0.5
Set Lsd=0.05
Set hLsd=$"Lsd"*0.5
Set Tox=-0.003
Set Nb=5e17
set Nsd=7e19
Set xj=0.05
set Vd=1
set Vg=2
set 1000Lg=$"Lg"*1000
set 1000Tox=$"Tox"*1000
#Set Et=acceptor
#set trap=1e18
MOSFETs (III)
Define mesh and structure.
#save mesh
mesh outf=NMOS_$"1000Lg"nm_mesh.str
#Define structure
#x.mesh
x.m loc=0.0 spacing=0.005
x.m loc=$"Lsd" spacing=0.002
x.m loc=$"Lsd"+$"Lg" spacing=0.002
x.m loc=$"Lsd"+$"Lg"+$"Lsd" spacing=0.005
#y.mesh
y.m loc=$"Tox" spacing=0.002
y.m loc=0 spacing=0.002
y.m loc=$"xj" spacing=0.002
y.m loc=$"xj"+0.1 spacing=0.005
y.m loc=$"Tb" spacing=0.02

MOSFETs (IV)
Define structure.
#define region
#define electrode
electrode name=gate number=3 x.min=$"Lsd" x.max=$"Lsd"+$"Lg“ y.min=$"Tox“ /
y.max=$"Tox“
electrode name=source number=4 x.min=0 x.max=$"Lsd"*0.5 y.min=$"Tox" y.max=0
electrode name=drain number=5 x.min=$"Lsd"+$"Lg"+$"hLsd“ /

x.max=$"Lsd"+$"Lg"+$"Lsd" y.min=$"Tox" y.max=0

MOSFETs (IV)
Define region and contact.
#define region
#define electrode
electrode name=gate number=3 x.min=$"Lsd" x.max=$"Lsd"+$"Lg" y.min=$"Tox"/
y.max=$"Tox“
electrode name=source number=4 x.min=0 x.max=$"Lsd"*0.5 y.min=$"Tox" y.max=0
electrode name=drain number=5 x.min=$"Lsd"+$"Lg"+$"hLsd"/

x.max=$"Lsd"+$"Lg"+$"Lsd" y.min=$"Tox" y.max=0

MOSFETs (V)
Define Doping and Contact.
#define doping
doping uniform conc=$"Nb" p.type x.left=0 x.right=$"Lsd"+$"Lg"+$"Lsd" y.top=0 /
y.bottom=$"Tb" direction=y
doping uniform conc=$"Nsd" n.type x.left=0 x.right=$"Lsd" y.top=0 y.bottom=$"xj“ /
direction=y
doping uniform conc=$"Nsd" n.type x.left=$"Lsd"+$"Lg“ /
x.right=$"Lsd"+$"Lg"+$"Lsd" y.top=0 y.bottom=$"xj" direction=y
#save structure
save outf=MOS_$"1000Lg"nm.str
# Set the workfunction of the Poly gate

CONTACT NAME=gate workfunction=4.17

MOSFETs (VI)
Set Material Models and Trap Model.

models cvt srh print temperature=300
# Q.fix
#trap $"Et" e.level=0.4 density=$"trap" degen=1 sign=1e-14 sigp=1e-14 x.min=$"Lsd"
x.max=$"Lsd"+$"Lg" y.min=0 y.max=0.001 fast

MOSFETs (VII)
Solve Id-Vg Characteristics.
method newton carriers=2
solve init
#IDVG
# Bias the drain
solve vdrain=0 vstep=0.1 vfinal=$"Vd" name=drain
log outfile=MOS_IDVG_$"1000Lg"nm_Vd$"Vd".log master
# Ramp the gate

solve vgate=0 vstep=-0.1 vfinal=-1 name=gate
solve vgate=-1 vstep=0.1 vfinal=$"Vg" name=gate

MOSFETs (VIII)
Id-Vg Characteristics Extraction.
#output file
output QFN QFP CHARGE CON.BAND VAL.BAND E.MOBILITY H.MOBILITY /
E.VELOCITY H.VELOCITY J.DRIFT J.DIFFUSION J.TOTAL TRAPS
#save bias condition str

save outf=MOS_IDVG_$"1000Lg"nm_Vd$"Vd"_Vg$"Vg".str
#extract
extract name="vt" (xintercept(maxslope(curve(abs(v."gate"),abs(i."drain")))) -
abs(ave(v."drain"))/2.0)
#
extract name="swing" 1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")))))
#
quit

MOSFETs (IX)
Solve Id-Vd Characteristics.
method newton carriers=2
solve init
#IDVD
# Bias the gate
solve vgate=0 vstep=0.1 vfinal=$"Vg" name=gate
# Ramp the drain

log outfile=MOS_IDVD_$"1000Lg"nm_Vg$"Vg".log master
solve vdrain=0 vstep=0.1 vfinal=$"Vd" name=drain
#save bias condition str

save outf=MOS_IDVD_$"1000Lg"nm_Vg$"Vg".str
quit

MOSFETs (X)
Mesh and Doping Profile.

MOSFETs (XI)
Ouput Id-Vd Characteristics for Long Channel and
Short Channel MOSFETs.
Long channel Short channel
-4
1.8x10 1.2x10-3
Lg=2m Vgs=2.5V Lg=0.15m Vgs=2.5V
-4 -3
1.5x10 1.0x10

1.2x10-4 -4
8.0x10 Vgs=2V
-5
Vgs=2V
9.0x10 6.0x10
-4
Vgs=1.5V
6.0x10-5 -4
Vgs=1.5V 4.0x10
3.0x10-5 Vgs=1V
Vgs=1V 2.0x10-4
0.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5
Drain Voltage (V) Drain Voltage (V)

MOSFETs (XII)
Output Id-Vd Characteristics for P and N MOSFETs.
PMOS NMOS
-3
1.2x10 1.2x10-3
Lg=0.15m Lg=0.15m Vgs=2.5V
-3 -3
1.0x10 1.0x10

8.0x10-4 8.0x10
-4
Vgs=2V
6.0x10-4 6.0x10
-4
Vgs=1.5V
-4 -4
4.0x10 4.0x10
Vgs=1V
2.0x10-4 2.0x10-4
0.0 0.0
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5
Drain Voltage (V) Drain Voltage (V)

MOSFETs (XIII)
Tranfer Id-Vg Characteristics.
Simulated with defect

10-3 10-3 10-3 Lg=0.13m
-4 -4
10 10 Vd=1V
10-5
-5 -5
10 10

PMOS NMOS

10
-6
10
-6
10-7
10-7 10-7
10-9
10
-8
10
-8
Nsub
DIBL=44mV/V
5x1016cm-3
10-9 St=83mV/decade 10-9 10-11 17 -3
1x10 cm
17 -3
10-10 10-10 5x10 cm
Lg=0.15m 10-13
10-11 10-11
Vds=0.1,1V
10-12
10-12 10-15
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

MOSFETs (XIV)
Tranfer Id-Vg Characteristics with GIDL.
Simulated with gate/drain overlap structure and band-to-band tunnel
model under Vd>Vg.
-3 -3
10 10
Lg=0.15m Lg=0.15m
10-4 10-4
10
-5
G/D overlap=5nm 10
-5
10-6 10-6

Vd=2V
10-7 10-7
-8 -8
10 10 G/D overlap=3nm
10-9 10-9
-10 -10 Vd=2V G/D overlap=5nm
10 10
10-11 10-11
10-12 w Band-to-Band model 10-12
-13 w/o Band-to-Band model -13
10 10
Vd=1V
10-14 10-14
-15 -15
10 10
10-16 10-16
10-17 10-17
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

MOSFETs (XV)
Tranfer Id-Vg Characteristics with GIDL.
210  7
VGD  1.2 
E Si  I dGIDL  e ESi
t ox
10-3
Nsub
10-4
1x1017cm-3
10-5
2x1017cm-3
10-6 17
5x10 cm
-3
18 -3
10-7 1x10 cm
10
-8 2x1018cm-3
10-9
-10
10
10-11
10-12
10-13 Vd=1V
10-14 Lg=0.15m
-15
10
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Gate Voltage (V)

MOSFETs (XVI)
Energy Band Diagram Profile from Source to Drain
along Quasi Fermi Level Profile. 1.0
Vd=1V
0.5 Vg=0V
0.0
Electron Energy (eV)

-0.5
X X’ -1.0
-1.5
-2.0
-2.5
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35
Distance (m)
1.0
Vd=1V
0.5 Vg=2V
0.0

-0.5
-1.0
-1.5
-2.0
-2.5
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35
Distance (m)
MOSFETs (XVII)
Energy Band Diagram Profile from Gate to Substrate.
4
Vd=1V
Vg=0V
2

0
Y -2
-4
-6
-8
0.00 0.05 0.10
Distance (m)
4
Vd=1V
Vg=2V
2

0
-2
Y’
-4
-6
-8
0.00 0.05 0.10
Distance (m)

Silvaco TCAD Tutorial MOS

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Silvaco TCAD Tutorial MOS

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TCAD Simulation

Introduction to TCAD Software an

TCAD, C. Lien Slide1

TCAD, C. Lien Slide2

TCAD, C. Lien Slide3

TCAD, C. Lien Slide4

Technology Computer Aided Design(TCAD)?

TCAD, C. Lien Slide5

Commercial TCAD Tools

Non- Commercial Programs

TCAD, C. Lien Slide6

TCAD, C. Lien Slide7

 Current-voltage, I-V curve  Potential

TCAD, C. Lien Slide8

Doping profile Electrical Device

Wigner Quantum Monte Carlo

Schrodinger Quantum Corrections

TCAD, C. Lien Slide9

Physical Models Boundary conditions

TCAD, C. Lien Slide10

TCAD, C. Lien Slide11

 Deckbuild ： An interactive and graphic runtime environment for

 Athena：A simulator that provides general capabilities for numerical,

 Atlas：Provides general capabilities for physically-based two (2D) and

TCAD, C. Lien Slide12

TCAD, C. Lien Slide13

TCAD, C. Lien Slide14

TCAD, C. Lien Slide15

 The number of nodes in the grid (Np) has a direct influence on

 A finer grid should exist in those areas of the simulation structure

 To maintain the simulation time within reasonable bounds, the fine

 The maximum number of grid nodes is 20,000 for Silvaco simulations.

TCAD, C. Lien Slide16

 The number of nodes in the grid (Np) has a direct influence on

 A finer grid should exist in those areas of the simulation structure

 To maintain the simulation time within reasonable bounds, the fine

 The maximum number of grid nodes is 20,000 for Silvaco simulations.

TCAD, C. Lien Slide17

TCAD, C. Lien Slide18

TCAD, C. Lien Slide19

 Athena: This tool performs structure initialization and manipulation, and

TCAD, C. Lien Slide20

TCAD, C. Lien Slide21

Defining initial mesh grid

Defining initial substrate

Conformal layer deposition

Specifying the electrodes

Saving the structure file

TCAD, C. Lien Slide22

Uniform grid Non uniform grid

TCAD, C. Lien Slide23

TCAD, C. Lien Slide24

Pressing the Write button the

The STRUCT OUTFILE line is

TCAD, C. Lien Slide25

TCAD, C. Lien Slide26

TCAD, C. Lien Slide27

TCAD, C. Lien Slide28

TCAD, C. Lien Slide29

TCAD, C. Lien Slide30

TCAD, C. Lien Slide31

TCAD, C. Lien Slide32

TCAD, C. Lien Slide33

TCAD, C. Lien Slide35