High Step-Up DC-DC Converter Using Built-in Transformer Voltage Multiplier Cell and Dual Boost Concepts

This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2021.3063060, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 1
High Step-Up Dc-Dc Converter Using Built-in

Transformer Voltage Multiplier Cell and Dual Boost
Concepts
Marcelo Flavio Guepfrih, Student Member, IEEE, Gierri Waltrich, Member, IEEE,
and Telles Brunelli Lazzarin, Senior Member, IEEE
Abstract—This article proposes a new high step-up DC-DC

converter for fuel cell applications. Built-in transformers and
voltage multiplier cells are integrated into the structure to step-
up the voltage gain. The paper proposes a new topology with
common ground. Two of them are connected using the dual
boost concept. Thus, the final structure provides input current
interleaved that reduces the current ripple, output-series connec-
tion that increases the voltage gain and floating ground on the
output voltage, which can be a limitation for some applications.
Additionally, on designing the built-in transformer with a leakage
inductance value much less than the magnetizing inductance
value (less than 0.5%), the proposed topology does not need a
clamp circuit, which reduces the number of components and
increases the efficiency. Operational steps, static gain analysis,
and design guide of the new converter are described in details
herein. Furthermore, a 1 kW, 48-800 V prototype was built
to verify the theoretical analysis. Tests in laboratory reached
94.60% of maximum efficiency at 480 W and 93.00% of
efficiency at 1.0 kW (rated power). Fig. 1. Microgrid block diagram example.
Index Terms—Dc-dc converter, high step-up, dual boost con-
verter, built-in transformer, voltage multiplier cells, boost inter-
leaved. Against this background, the use of step-up converters is a
requirement in this field [8]. The conventional boost converter
I. I NTRODUCTION is the first candidate to solve this issue. However, it presents
limitations for high-voltage gains (greater than 4× when it
R ENEWABLE sources have been appearing as an alter-
native to produce electrical energy and to replace a few
fossil fuels sources [1], [2]. In this scenario, the use of sources
uses a duty cycle close to the unit), as reduced efficiency,
high voltage stresses on switches, high reverse diode recov-
as photovoltaic (PV) and wind energies have been growing ery time, and output voltage is too sensitive regarding to
up significantly [3]. Renewable sources are intermittent and a the duty cycle [9], [10]. Therefore, voltage gain techniques
solution to solve this challenge is to store the produced energy have been developing and applying to propose novels step-up
in battery banks or to supply it for an utility grid [4]. converters [11]. Among these alternatives, voltage multiplier
The popularization of renewable energies has been bringing cell techniques stand out providing voltage gain and reducing
an emergent demand for direct current microgrids and energy the voltage stresses on the switches [12], [13], [14]. These
storage systems. The last supplies stability for microgrids techniques use semiconductors with lower blocking voltage,
based on intermittent renewable energy sources. A method to which leads to converter efficiency improvement [15], [16].
generate electrical energy in microgrids is through fuel cells However, converter with voltage multiplier cells can present
(FC), which have been used more and more given its zero problems associated with high current peaks, which are caused
pollution emission, high efficiency in the energy conversion by energy exchange among cells’ capacitors [17], [18].
process, and capability to supply energy with no intermittent Techniques to provide voltage gain based on magnetic cou-
[5]. For instance, in a microgrid, the FC may be used in pling has been also widely used. Theoretically, it is possible
instants of the intermittent of other sources as photovoltaic to obtain extremely high voltage gain changing the transfor-
and wind, and during faults of the grid. It provides backup, mer turn ratio value [19], [20]. However, these converters
stability, and guarantees to the system [6]. present problems related to leakage inductance, resulting in
FC systems supply energy at low voltage values, and thus, high-voltage spikes during commutation and damping/clipping
the challenge is to connect it to high voltage loads, for circuits (snubbers) have to be used, which deteriorates the
instance in DC bus from microgrids [7], as depicted in Fig. 1 converter efficiency [21]. Thus, the isolated use of magnetic
configuration. coupling, through coupled inductors and built-in transformers
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2021.3063060, IEEE Journal
may not be very attractive [22].

An interesting alternative is to combine voltage multiplier
cells to coupled inductors or built-in transformers. The in-
tegration increases the converter gain, it divides the voltage
stress on the semiconductors and, additionally, it can use the
leakage inductance to provide soft commutation on diodes and
to avoid the current peaks caused by charge and discharge
of capacitors [23]. These concepts has been applied for low
power applications in literature [24], [25].
On the other hand, converters connected to low input voltage
(e.i., fuel cells) has a high input current, which is another
challenge to design a converter. For higher power applications
the multistage concept is usually employed [26]. Techniques
as interleaved, parallel connection of devices, and parallel
connection of converters are employed to reduce the input
Fig. 2. Proposed converter.
current and the ripple input current of dc-dc converters [27].
Conventional solutions to share the input current have their
outputs connected in parallel as well. Nevertheless, these so- It should be highlighted that some literature names the dual
lutions have to be studied herein with output-series connection boost converter either floating-output double-boost converter
to provide high voltage gain [28]. or differential connection, as in [28], [36] and [31], and
Based on voltage gain and current division techniques, this this configuration may be applied on other topologies, as
paper proposes a novel high step-up dc-dc converter using the approached in [37].
dual boost concept, which can be adequate for applications
such as fuel cell, charging batteries, a connection between two A. Resonant tank
DC bus with different voltages, lighting, and other isolated
The built-in transformer has a resonance between the series
circuits from the grid, which common ground is not required
capacitance (C1 and C2 ) and the transformer leakage induc-
[29]–[33]. The proposed topology combines advantages of
tance (Lk1 and Lk2 ), as detailed in [38]. This feature may
interleaved converters, built-in transformer, voltage multiplier
provide a sinusoidal current in the built-in transformer primary
cells, and output capacitors connected in series from the dual
side during the switching period. Therefore, the converter can
boost configuration. In addition, it does not use a clamp circuit
be configured to operate in two modes, that is either Above
for leakage inductances. The operational stages, static gain
Resonance Frequency (ARF) or Below Resonance Frequency
analysis in CCM and DCM, design equations, dynamic and
(BRF). Figure 3 shows the current waveform iLk in the leakage
efficiency analysis, and experimental results are approached
inductance (primary side of transformer) for both operational
in this paper.
modes.
II. P ROPOSED C ONVERTER AND P RINCIPLE OF
O PERATION
This section presents the principles of operation, features of
resonant tank and topological states of the proposed converter.
The proposed step-up dc-dc converter is depicted in Fig. 2. It
is composed of the following components: inductors L1 and
L2 ; power switches s1 and s2 ; built-in transformers Tr1 and
Tr2 ; blocking capacitors C1 and C2 ; voltage multiplier cells
(VMC) that employ diodes Dm1 and Dm2 and capacitors Cm1
and Cm2 ; and the output rectifier stage, formed by Co1 and
Fig. 3. Current of the leakage inductance, modes ARF and BRF.
Co2 and diodes Do1 and Do2 . The built-in transformers turn
ratio are given by N = (Ns1 /Np1 ) = (Ns2 /Np2 ).
The ARF mode uses tr < dTs and the switching period
The topology proposed herein is seen in Fig. 2 and it is
Ts is longer than the resonance period tr . As a consequence,
named as phase-1. The circuit is a step-up converter composed
the current iLk is in discontinuous conduction mode (DCM),
of input inductor, built-in transformer, multiplier cell, and
as seen in Fig. 3 (b). Conversely, BRF operational mode
output rectifier stage. Additionally, it has a common ground.
employs tr > dTs . As a result, the current iLk operates in
Two phases are interleaved using the dual boost concept
continuous conduction mode (CCM), as shown in Fig. 3 (c).
(proposed in [34] and [35]), which provides low current ripple
The resonance period between Lk1 and C1 (or Lk2 and C2 )
at the input, the output-series connection that increases the
is defined by,
voltage gain, and floating ground on output voltage. Both p
tr = π Lk1 C1 . (1)
phases (1 and 2) connected in dual boost concept are depicted
in Fig. 2. This integration is analyzed together, so that it is The current through diodes Dm1 and Dm2 (iDm ) has the
named herein as the proposed converter. same shape of the current iLk during the negative half period
(iDm only presents different signal). Therefore, using the ARF energy from the secondary side of Tr1 and Dm2 is reverse-
operation, the Zero Current Switching (ZCS) condition in the biased. This stage will finish when s2 is turned-off.
diodes Dm1 and Dm2 is achieved due to the discontinuity Stage 3 [t3 − t2 ]: s1 maintains in on-state and s2 is turned-off.
in iLk that reflects in the transformer secondary side and, Do1 is maintained reverse-biased, Dm1 is forward-biased, L1
consequently, in iDm . Thus, the choice between ARF and BRF is storing energy, and resonance between C1 and Lk1 should
modes defines if the multiplier cell diodes (Dm1 and Dm2 ) be completed close to the end of the stage. The diode Do2 is
will or it will not operate in ZCS. forward-biased and L2 transfers its energy to the resonant tank
On analyzing the ARF region, three operation mode for and to the load. This stage will finish when s1 is turned-on.
resonance can be highlighted. Considering the gate driver Stage 4 [t4 − t3 ]: in this stage both s1 and s2 are in on-state.
signals d1 and d2 180° phase-shifted due to interleaved op- Consequently, Do1 and Do2 are reverse-biased. L1 and L2 are
eration mode between s1 and s2 , these modes are depicted storing energy. Dm2 is forward-biased due to the resonance
in Fig. 4. In the first case, the resonance period tr is shorter, between C2 and Lk2 is starting. Cm2 starts to receive load
maintaining the ZCS condition. However, a short resonance from Tr2 . This stage will finish when s1 is turned-off.
period increases the rms current value, and, therefore, the con-
verter efficiency decreases. The second case is an intermediate
situation, in which tr is close to Ts /2. It maintains the ZCS
condition and it presents a good compromise between effective
current and efficiency values. Lastly, in the third case, as long
Ts /2 < tr < dTs , the ZCS condition can be lost due to non-
idealists of the circuit. Thus, the second mode is suggested for
a good design. Considering the leakage inductance fixed, the
resonance frequency is adjusted in function of C1 and C2 , as
illustrated in Fig. 4.
Fig. 4. Current through Dm1 versus C1 variation.
B. Topological states
The operation stage analysis considers that: the compo-
nents are ideal, free of parasitic elements (resistances and
capacitances), except by the transformer leakage indutances; Fig. 5. Proposed converter main waveforms.
all capacitors are adequately large and their voltages are
considered constant during one switching period; the currents
through the input inductors are in CCM. Considering these III. C ONVERTER P ERFORMANCE A NALYSIS
conditions, the converter presents four operating stages, which
are described as follows: The proposed converter behavior in relation to static gain
Stage 1 [t1 − t0 ]: the topological state starts when s1 is (in CCM and DCM), voltage and current stresses, efficiency
turned-off and s2 is in on state. The diode Do1 is forward- analysis and comparison with other similar converters are
biased, Dm1 is reverse-biased, Cm1 transfers its energy to the detailed in this section. The following considerations are taken
output load, the input inductor L1 transfers its energy to the into account during the analysis: (L1 = L2 ), (C1 = C2 ),
resonant tank and to the load. The input inductor L2 stores (Tr1 = Tr2 ), (Cm1 = Cm2 ) and (Co1 = Co2 ).
energy from the input source vg . The diode Do2 is reverse-
biased, Cm2 is loaded through the secondary side of Tr2 . A. Static analysis in CCM
C2 and Lk2 are in resonance and this resonance should be This section approaches the proposed converter in CCM.
completed close to the end of the stage. This stage will finalize The static analysis is carried out in one phase and the result
when s1 is turned-on. is extended to another due to their similarities. Hence, the
Stage 2 [t2 − t1 ]: during this stage s1 and s2 are turned-on. analysis begins in Phase 2, as follows.
Consequently, Do1 and Do2 are reverse-biased. Input inductors During steps I, II and IV the voltage in L2 is given by,
L1 and L2 are storing energy. The resonance between C1
and Lk1 starts and thus Dm1 is forward-biased. Cm1 receives IV
vL2 = vg . (2)
Considering the inductor voltage-second balance principle,

the related voltage expression during step III, is given by
III d .
vL2 = −vg (3)
(1 − d)
During stages I, II and IV,
IV IV ,
vN 2 = −vL2 (4)
vC2 , vL2 = vg ,
IV
(5)
IV IV .
vN 22 = N × vN 2 (6)
That leads, during stage III, to,
III
h i
III d ,
vN 2 , − vL2 = vg (7)
(a) Stage 1 [t1 − t0 ]. (1 − d)
III
h
III
i N d .
vN 22 , N × vN 2 = vg (8)
(1 − d)
During stages I and IV the voltage in Cm2 is given by,
.
IV
vCm2 , − vN 22 = N × vg (9)
The output voltage (vo2 ), during stage III is equal to,
h
III III
i (N + 1) .
vo2 , vC2 + vN 2 + vN 22 + vCm2 = vg (10)
(1 − d)
During the same step, considering the converter symmetry,
i.e., (vo1 = vo2 ), the output voltage (vo ) is given by,
vo = vo1 + vo2 − vg , (11)
(b) Stage 2 [t2 − t1 ].
which leads to the ideal voltage gain (M ) of the proposed
topology, expressed by,
vo (2N + d + 1) .
M (d, N ) , = (12)
vg (1 − d)
The voltage gain of the proposed converter (equation 12) is
shown in Fig. 7 for different values of transformer turn ratio
(N ). It should be highlighted that the topology can provide a
high voltage gain, and it increases in relation to N .
(c) Stage 3 [t3 − t2 ].
Fig. 7. Voltage gain (M ) considering the lossless proposed converter.
B. Static analysis in DCM

The discontinuity in the input inductor currents (iL1 ) and
(iL2 ) during the demagnetization period (∆t2 ), and in the
output diode current (iDo ) defines the discontinuous conduc-
(d) Stage 4 [t4 − t3 ]. tion mode (DCM), as depicted in Fig. 8. The DCM operation
changes the converter static gain, which depends on the load
Fig. 6. Stages of the proposed converter.
current (io ).
20
15
10
DCM
5 CCM
0 0.002 0.004 0.006 0.008 0.010
Fig. 9. Voltage gain M as a function of normalized load current io for DCM

and CCM considering the lossless converter.
Fig. 8. Proposed converter main waveforms operate in DCM. C. Voltage and current stresses
The maximum voltage on vds1 occurs in stage I and on
According to Fig. 8, the diode average current, iDo[AVG] , can vds2 occurs in stage III, but both values are equal. Considering
be denoted by the output current, io , which is related to the vds = vds1 = vds2 , the voltage stress is given by
inductor maximum current, iL1[MAX] , given by
III vg × d vg .
iL1[MAX] ∆t2 . vds , (vg + vL2 ) = vg + = (21)
io , iDo[AVG] = × (13) (1 − d) (1 − d)
2(N + 1) Ts
where ∆t2 is the period between (t2 − t1 ). According to Fig. 6, the multiplier cell diode voltage
The inductor maximum current is obtained by (vDm = vDm1 = vDm2 ) and the output-stage diode voltage
(vDo = vDo1 = vDo2 ) are given, respectively, by
vg d vo1 d.
iL1[MAX] , × = × (14) vg (N ) ,
L1 Ts L 1 fs M III
vDm , vN

22 + vCm2 = (22)
(1 − d)
where M denoted de static gain (vo1 /vg ) in DCM mode.
The inductor demagnetization occurs at ∆t2 , which is vg (N + 1) .
vDo , [vo1 = vo2 ] = (23)
defined by (1 − d)
∆t2
In relation to current stresses, the inductors current equa-

vo1 /(N + 1) − vg
, (15)
iL1(∆t2 ) = iL1[MAX] − × t tions are summarized in Table I, with (L = L1 = L2 ).
L1 0
iL1[MAX] × L1 × (N + 1) .
∆t2 = (16) TABLE I
vo1 − vg (N + 1) I NPUT INDUCTOR CURRENT.
When replacing (16), (14) into (13), io is expressed by
∆ iL iL[AVG] iL[MIN] iL[MAX] iL[RMS]
vo1 d2 .
io = × (17)
2Lfs M (M − N − 1)

vg d (M +1) ∆i ∆i
io iL[AVG] − L iL[AVG] + L ≈ iL[AVG]
Lfs 2 2 2
The current io is normalized, named as io , and it is obtained
by
2Lfs , d2 The diodes current stresses are given,
io , ⇒ io = . (18)
vo1 M (M − N − 1) iDo[AVG] = iDm[AVG] = io , (24)
The converter static gain in DCM mode (M ) is obtained s
from (18), and it is given by 1 ,
iDo[RMS] = io (25)
s (1 − d)
(N + 1) d2 (N + 1)2 . r
M (d, N, io ) = + + (19) ω dr .
2 (io ) 4 iDm[RMS] = io (26)
fs 8
The boundary (iκε ) between MCC and MCD modes occurs
where dr is√equal tr /Ts and ω is the resonance frequency,
when (12) is equal (19), given by,
given by 1/ C1 × Lk1 .
(M − 2N − 1)2 . The switches average currents are given by
iκε = (20)
M (M + 1)2 (M − N − 1)
2N + d(M + 1) ,
A graph projection of (12), (19) and (20) gives the limits is[AVG] = io (27)
2
between the conduction modes, as shown in Fig. 9. In this
figure the transformer turn ratio (N ) is equal to one. In and the rms current is defined, approximately, by
addition, the analyses for DCM and CCM was done for 4N + d(M + 1) .
d > 0.5 is[RMS] , is[AVG] + N iDm[AVG] = io (28)
2
The rms capacitors currents are written by Capacitor power losses are given by
s
d , PC = ESR i2C[RMS] , (39)
iCo[RMS] = io (29)
(1 − d) where ESR is the capacitor intrisic resistance and iC[RMS] is the
s rms capacitor current.
ω dr fs2 ,
iCm[RMS] = io + (30) Finally, the total power losses (Ploss ) and converter effi-
fs 8 (1 − d)ω 2 ciency (η) are estimated, respectively, by
s
ωN dr fs2 . Ploss = Pmos + PD + PL + PC , (40)
iC1[RMS] = io + (31)
fs 8 (1 − d)ω 2 Po
η= . (41)
The rms currents in the built-in transformers are given by Po + Ploss
s From the performed analysis, and considering (34), (35),
ωN dr fs2 , (37), (38), (39) and data from Table III, power losses graphs
iP ri[RMS] , iC1[RMS] = io + (32)
fs 8 (1 − d)ω 2 were obtained, as seen in Fig. 10 (a) and (b). These graphs
present the converter power losses distribution in absolute
s
ω dr fs2 .
iSec[RMS] , iCm[RMS] = io + (33) (Fig. 10 (a)) and percentage Fig. 10 (b)) values. The theoretical
fs 8 (1 − d)ω 2 power losses, at full load (1 kW) are close to 40 W. At lower
power levels, the losses concentrates more in the magnetic
D. Efficiency Analysis elements, while, at higher power levels, the losses are equally
The component intrinsic resistances and semiconductor for- distributed among all components.
ward drop voltages have impact in the converter efficiency.
Thus, to measure the converter efficiency, the equations for
semiconductors, magnetics and capacitors losses are presented
as following.
The power losses (Pmos ) in the switches can be divided
in two parts. One part describes the switching losses (Psw ),
while the another part describes the conduction losses (Pcon ).
The switching losses are calculated by
1
fs × VDS[off] × is[AVG] × (ton + tof f ) ,

Psw = (34)
2
where fs is the switching frequency, is[AVG] is the average
switching current, VDS[off] is the voltage across the switch (see
(21)), and ton and tof f represent, respectively, the switches
time rise and time fall. The conduction losses are calculated
by
Pcon = RDS[on] i2s[RMS] , (35)
where is[RMS] is the rms current, and RDS[on] is the MOSFET
ON-state resistance. Thus, the total power losses in the con-
verter switches are obtained by
Pmos = Psw + Pcon . (36)
Fig. 10. Efficiency analysis. (a) power losses and (b) distribution losses.
The total power losses (PD ) on the converter diodes are
obtained by E. Sensitivity Analysis of the Duty Cycle
A sensibility analysis may consider many variables of the
PD = VD ID[AVG] + RD[on] i2D[RMS] , (37)
proposed converter. In this section, it is studied the sensitivity
where ID[AVG] represents the average current, iD[RMS] is the defined by the ratio between the converter output voltage (vo )
rms current, VD is the diode voltage stress and RD[on] is the and small changes in the duty cycle (d), around the converter
diode conduction resistance. All these data are obtained from operating point [40]. Thus, this sensitivity is defined by
manufacture datasheets.
∂vo d

∆vo d
Inductors and built-in transformers losses are divided in Sdvo , × = × . (42)
∂d vo ∆d vo
copper and core losses [39], given by
The conventional boost and proposed converter have their
PL = RL i2L[RMS] + fs Lk i2P ri[MAX] + Ve Kc fsα ∆B β , (38) sensitivity defined by,
| {z } | {z }
copper loss core loss
d

 (1 − d) , → boost converter


where Ve is the core volume and Kc , α and β are constants
obtained from manufacturer datasheet. The iP ri[MAX] is equal Sdvo = (43)

 2d(N + 1) , → proposed converter
to (Io N ω)/(2fs ). 
(1 − d)(d + 2N + 1)
The equations above are shown graphically in Fig. 11. It where, Req = (r1 + r2 )r3 + (r1 + r2 + r3 )Ro .
should be noted from Fig. 11 that, for the same duty cycle Applying the Laplace transform, it is obtained,
variation, both converters provide different gains but they have
Ỹ(s) = C(sI − A−1 Γ) + Ψ d̃(s).

(55)
similar sensitivity for a wide duty cycle range.
where the matrices Γ and Ψ are defined by,
Γ = (A1 − A2 )X + (B1 − B2 )U, (56)
Ψ = (C1 − C2 )X + (E1 − E2 )U. (57)
On solve these equations, the transfers functions inductor
current to duty cycle and output voltage to duty cycle are
obtained. Applying the prototype values shown in TABLE III
on obtained transfers functions, the final results are giving by,
(a) (b)
Fig. 11. Comparison between boost converter and proposed converter. (a) ĩL1 (s) 7e5s3 + 2.47e13s2 + 1.1e20s + 1.2e22 ,
= (58)
static gain (M ). (b) sensitivity (S). ˜
d(s) s4 + b1 s3 + b2 s2 + b3 s + b4
F. Dynamic Analysis ṽo1 (s) 5.3e4s3 + 1.55e12s2 + 7.1e18s + 3.5e23 .
= (59)
The dynamic analysis approached in this section follows ˜
d(s) s4 + b1 s3 + b2 s2 + b3 s + b4
the methodology presented in [41]–[43], uses the equivalent where,
circuit shown Fig.12, and considers the converter in CCM.
b1 = 3.52e7 b2 = 1.63e14 b3 = 9.14e16 b4 = 4.33e20
The methodology for multi-loop control, that is, with the
simultaneous control of the output voltage and the input
current is shown in Fig.13. The block diagram shown in figure
is used for individual control in each phase,
Fig. 12. Circuit of the proposed converter for dynamic analysis.

• When s1 is ON, the following differential equations describe current
sensor
the behavior of the converter:
diL1 (t) voltage
L1 = vg (t) − rL iL1 (t), (44) sensor
dt
dvC1 (t) vC1 (t) vC2 (t) , Fig. 13. Methodology for double loop control.
C1 =− − (45)
dt (r1 + r2 ) (r1 + r2 ) ∗
dvC2 (t) vC1 (t) vC2 (t) , where, vref is reference voltage, v is voltage error, i∗ref is
C2 =− − (46) reference current, i is current error, mi is a modulation,
dt (r1 + r2 ) (r1 + r2 ) ˜
d(s) is the duty cycle, ĩL1 (s) is current in phase-1 and
dvC3 (t) vC3 (t) , ṽo1 (s) is output voltage in phase-1. Cv (s) is the voltage
C3 =− (47)
dt (r3 + Ro ) controller, Ci (s) is the current controller, kPWM (s) is the PWM
Ro ˜ and Gv (s) is ṽo1 (s)/ĩL1 (s).
modulation, Gi (s) is ĩL1 (s)/d(s)
vo = vC3 (t). (48)
(r3 + Ro ) Both controllers Cv (s) and Ci (s) using PI structures. Thus,
• When s1 is OFF, the expressions describe the converter: on choosing the phase margin (Pm) and the crossing frequency
diL1 (t) dvC2 (t) dvC3 (t) (ωc ), the parameters of both PI controllers are defined. In the
L1 + [r2 + Ro ]C2 − [Ro ]C3 = input-current control, a Pm = 60◦ and ωc = 2π2000 rad/s were
dt dt dt
vg (t) − vC2 (t) − rL iL1 (t), (49) assumed. In the output-voltage control, a Pm = 60◦ and ωc =
2π200 rad/s were employed. Following those specifications,
dvC1 (t) dvC2 (t)
C1 + C2 = iL1 (t), (50) the Fig. 14 shows the open-loop, controller, and compensated
dt dt open-loop transfer functions of current- and voltage loops.
dvC1 (t) dvC2 (t) dvC3 (t)
[r1 ]C1 − [r2 ]C2 − [r3 ]C3 =
dt dt dt
− vC1 (t) + vC2 (t) + vC3 (t), (51) G. Performance Comparison

Ro

dvC2 (t) dvC3 (t) −vC3 (t) , A comparison among the proposed converter and other
− C2 + C3 = (52) boost converters [38], [44], [45], [46] and [47] is presented
Ro + r3 dt dt (r3 + Ro )
r1 r2 Ro r3 Ro r3 Ro in Table II and in Fig. 15. In relation to the voltage gain (15
vo = iL1 (t) + vC1 (t) − vC2 (t)+ (53) (a)), the proposed converter presents highest voltage gain than
Req Req Req
the converters proposed in [38], [44] a similar to [46] and less
(r1 + r2 )Ro than [47]. Regarding the switches voltage stresses (as seen
vC3 (t). (54)
Req in the pink area in Fig. 15 (b)) the proposed topology has
50 60
Magnitude (dB)
Magnitude (dB)
25 30
0 0 200 Hz
2000 Hz
not compensated not compensated
-25 compensated -30 compensated
PI - control PI - control
-50 -60
180 0
90 -45
Phase(deg)
Phase(deg)
0 -90
-90 -135 Pm = 60 deg

Pm = 60 deg
-180 -180
0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100
frequency (Hz) frequency (Hz)
(a) (b)
Fig. 14. Bode diagram. (a) Control for input current iL1 . (b) Control for output voltage vo1 .
TABLE II
C OMPARISON AMONG THE PROPOSED CONVERTER AND OTHERS HIGH STEP - UP CONVERTERS .
Converter
Parameter
in [25] in [38] in [44] in [45] in [46] in [47] Proposed
Number of switches 1 1 2 2 2 2 2
Number of diodes 1 3 2 6 6 8 4
Number of capacitors 2 4 5 5 5 7 6
Number of cores 2 2 2 3 3 3 4
Number of windings 3 3 3 5 7 7 6
1 N +2 N +1 2(N + 1) 2(N + 1) + n 2(N + n + 1) 2N + d + 1
Voltage gain (M )
1 − (1 + N )d (1 − d) (1 − d) (1 − d) (1 − d) (1 − d) (1 − d)
Voltage stress on 1 1 1 1 1 1
1
switch (vDS /vo ) (N + 2) (N + 1) 2(N + 1) 2(N + 1) + n 2(N + n + 1) (2N + d + 1)
Voltage stress on N +1 N 2N + 1 2N + n + 1 2N + 1 N +1
N
diode (vDo /vo ) (N + 2) (N + 1) 2(N + 1) 2(N + 1) + n 2(N + n + 1) (2N + d + 1)
Input current continuous continuous continuous continuous continuous pulsating continuous pulsating continuous
Interleaved × × × X X X X
Frequency 30 kHz 100 kHz 100 kHz 100 kHz 20 kHz 20 kHz 50 kHz
Maximum efficiency − 96.6% 96.7% 96.1% 97.6% 97.7% 94.7%
Efficiency in full load − 95.6% 95.4% 95.4% 96.9% 96.0% 93.0%
Rated power 400 W 500 W 500 W 1 kW 1.3 kW 1 kW 1 kW
Test gain 4 10.55 10.55 9.5 12 15 16.67
vg /vo (V) 50/200 36/380 36/380 40/380 50/600 45/675 48/800
one of the lowest voltage stresses when compared to other A. Input inductor design
converters. When analyzing the output diode voltage (as seen To design L1 and L2 is considered,
in the white area in Fig. 15 (b)), the proposed converter is
the only one that presents a reduction in this voltage while vg × d .
L1 = L2 , (60)
increasing the transformer turn ratio. iL1[AVG] × fs × ∆iL1 [%]
In relation to the converter presented in [38], which was one
of the based-paper used in this study, the proposed converter The recommended value for the current ripple is 20% ≤
presents advantages, such as the greater static gain (as seen ∆iL1 [%] ≤ 30% (but it is not mandatory). There are some duty
Fig. 15 (a)), the lowest voltage stress on the switch and output cycle values that the input current ripple is canceled [48].
diode (as depicted in Fig. 15 (b)), and smaller number of
components per phase (as shown in TABLE II). B. Built-in transformer design
The built-in transformer design follows the recommenda-
IV. D ESIGN G UIDELINES
tions proposed in [49]. The rms currentpis obtained from (32),
This section approaches design for the proposed converter. while the rms voltage is defined by vg d/(1 − d).
1.0
Ref. [38] Ref. [44] Ref. [45]
Ref. [46] Ref. [47] Proposed 0.8
Normalized Voltage
50 0.6
40
0.4
* * * * * * (b)
30
20 (a)
0.2
10 * *
0 0
* * *6 *7
0.5 0.6 0.7 0.8 0.9 1.0 1 2 3 4 5 8
Fig. 15. Comparison among the proposed converter and others boost converters. (a) Voltage gain (M ). (b) Voltage (VDo /vo ) and voltage (VDS /vo ).
C. Capacitor Design
Using the voltage ripple criteria (∆vc[%] ), the three capaci-
tors of a phase are calculated by,
d2 ,
C1 ≈ (61)
Lk1 π 2 fs2
m
1 40 m
Po (1 − d)2

1 ,
Cm1 = (62)
fs ∆vc[%] (2N + d + 1)vg2 N
mm
Po (1 − d)2

d ,
Co1 = (63)
105
fs ∆vc[%] (2N + d + 1)vg2 N + 1
being recommend values around 1% ≤ ∆vc[%] ≤ 5%. 160 mm
Fig. 17. Proposed converter prototype.
TABLE III
P ROPOSED CONVERTER SPECIFICATION
Parameter / Component Specification

Input Voltage (vg ) 48 V
Output Voltage (vo ) 800 V
Output Power (Po ) 1000 W
Switching Frequency (fs ) 50 kHz

Inductor 1 (L1 ) (185 µH)@ 20 turns (90×AWG32) @(110 mΩ)

Inductor 2 (L2 ) (184 µH)@ 20 turns (90×AWG32) @(127 mΩ)
Fig. 16. Graphic method for the design of C1 and C2 . Transformer 1 (Tr1 ) magnetizing (423 µH) @ leakage (595 nH)

primary → 10 turns (45×AWG32) @(444 mΩ)

Equation (61) estimates a value for the capacitors C1 and secundary → 20 turns (30×AWG32) @(540 mΩ)
C2 . However, that value can be adjusted in relation to the Transformer 2 (Tr2 ) magnetizing (440 µH) @ leakage (495 nH)

primary → 10 turns (45×AWG32) @(440 mΩ)
resonance period determined in eq. (1), which defines the
secundary → 20 turns (30×AWG32) @(550 mΩ)
operation in ARF or BRF modes, and the rms current in the L1 and L2 Core → E42/21/20 EPCOS-N87
diode iDm described in eq. (26). C1 value regarding these Tr1 and Tr2 Core → E42/21/15 EPCOS-N87
criteria are depicted in Fig. 16, considering the specification Switches (s1 ) and (s2 ) FCH76N60NF → (600 V)@(72 A)@(RDS(on)= 38 mΩ)
shown in Table III. It should be noted that the capacitor value Diodes (Dm1 ), (Dm2 ), IDH10G65C5 → (650 V)@(10 A)@(VF =1.7 V)
(Do1 ) and (Do2 )
can be adjusted to reach the desired resonance period and the
rms current in iDm . In Fig. 16, the blue region shows the best
values for C1 (and C2 ) using these both criteria.
load output voltage vo (vo1 + vo2 ) are depicted in Fig. 18 (a).
V. E XPERIMENTAL V ERIFICATION It should be highlighted a reduced ripple in the input current
A 1 kW, 48 to 800 V prototype was built to verify the in relation the inductor currents, a self balance between vo1
proposed converter operation. The prototype specification is and vo2 and between iL1 and iL2 , and a high-voltage gain in
detailed in Table III and a photograph is shown in Fig. 17. vo (48 to 800 V).
All experimental results shown in Figs. 18, 19, 21, and 22 The currents and voltages on the input inductors L1 and
were carried out at rated power. L2 are detailed in Fig. 18 (b) and a 180◦ degree phase-shift
The input inductor currents iL1 and iL2 , total input current between both phases waveforms is clearly seen.
iL1 + iL2 , output voltages in each phases vo1 and vo2 , and The voltage and current stresses on switches s1 and s2 are
(a) (b) (c)
(d) (e) (f)
(g) (h) (i)

Fig. 18. Experimental waveforms measurements (voltage and current) of the proposed converter. (a) inductors L1 and L2 . (b) vo1 and iL1 for phase-1, vo2
and iL2 for phase-2. (c) waveforms of the switches s1 and s2 . (d) waveforms of the diodes Dm1 and Dm2 . (e) waveforms of the diodes Do1 and Do2 . (f)
vgs1 , is1 , iDm1 and iDo1 . (g) iL1 , is1 , iLk1 and iDm1 . (h) iL1 , is1 , iLk1 and iDo1 . (i) vgs1 , vds1 , is1 and iDm1 .
shown in Fig. 18 (c). It should be noted that it was used The dynamic test is shown in Fig. 19. A step of 1% is
switches with a 600 V blocking voltage, even with an 800 V applying in the duty cycle to verify the proposed dynamic
output voltage. Small differences between peak-voltage values model. The simulation results are depicted in Fig. 19(a), while
are attributed to the measurement probes. experimental results are shown in Fig. 19(b). Both waveforms
(simulated and experimental) are close, which corroborates the
The voltage and current stresses on diodes Dm1 and Dm2
proposed model.
are depicted in Fig. 18 (d). Converter non-idealities (stray
Tests were carried out in order to evaluate the controllers
inductances and parasitic capacitances) contribute to an small
performance and they are shown in Fig. 20. The first test,
amplitude differences in both currents. Additionally, ZCS
seen in Fig. 20 (a), applies positive-load and negative-load
switching characteristic is verified when the diodes currents
steps during the operation. When a load is added to the
reach zero value before the next period. The current and
output (positive-load step), the control action increases in
voltage stresses on the output diodes Do1 and Do2 are shown
amplitude, which rises the current reference and, thus, the
in Fig. 18 (e). The ZCS feature is highlighted in the waveform.
inductor current. As a consequence, the output is regulated in
Figure 18 (f) details the s1 gate-source voltage (vgs ), drain- its reference value. When a load is disconnected to the output
source current in the switch s1 , diode current in Dm1 , and (negative-load step), the voltage control action, the reference,
diode current in Do1 . It may be observed that the current and inductor currents reduce to maintain the output voltage
Dm1 is part of current is1 , as expected by theoretical analyzes. regulated. In both cases, the control loops (current and voltage)
Figures 18 (g), (h) and (i) presents different waveforms of guarantee the converter operation within the limits imposed by
the current in L1 , s1 , Lk1 , Dm1 , and Do1 . These figures the references. The transient responses show a fast dynamic
detail the main currents in the phase-1, and all of them are in response in the current loop and a slow dynamic response to
accordance with theoretical waveforms presented in Fig. 5. It the loop voltage, as expected.
should be noted a great similarity between the theoretical and
experimental curves.
control signal
5A/div
reference
10V/div 424 V
reference
(a)
0.004/div
(a) 0.67
4A/div
7V/div reference
424 V
(b)
20V/div
2A/div reference
(b) 424 V
10V/div
reference
Fig. 19. Response of the step in duty cycle. (a) Simulation. (b) Experimental.
(c)
The second test verifies unbalanced load on the output (an
Fig. 20. Response of the step in duty cycle [5.0ms/div]. (a) Load step.
extra load is connected parallel to the Co2 ). The test starts with (b) Control system under unbalanced load. (c) Input voltage step.
the control system disabled and, after a period, it is enabled.
It should be noted in Fig. 20(b) that the duty cycles are equal
with no control, while the inductor current and output voltages converter losses distribution is presented in Fig. 22 and it may
from each modules (vo1 and vo2 ) are not equal. Then, when the be noted that the highest losses are the switches.
control system is activated, the control signals find different
duty-cycles to regulate the output voltages according to the 96
reference. 95
Finally, the last test considers variations in the input voltage 94
value (vg ). Voltage steps are added in vg , which generate
different values for the input current. When the input voltage 93
rises, the inductor current reduces, and the output voltage 92
(vo1 ) maintains in its reference value. Similar behavior is seen 91
in vo2 . The dynamic response from the current and voltage 200 400 600 800 1000
controllers were adequate to input voltage perturbations.
Efficiency curves for three different values of C1 and C2
are presented in Fig. 21. The prototype reached 94.7% of Fig. 21. Proposed converter experimental efficiency.
maximum efficiency at 480 W using C1 = C2 = 25uF . It
should be highlighted that increasing the capacitors value, the
converter efficiency increases as well. As was approached in VI. C ONCLUSION
subsection II-A, when these both capacitance increase, the res- This paper proposes a high step-up dc-dc converter. The new
onant period increases. As a result, the resonant current peak topology is configured in an interleaved structure (dual boost
reduces, reducing the conduction losses. However, there is a concept), with built-in transformers, voltage multiplier cells,
limit to increase these capacitance maintaining ZCS operation and stacked output. The interleaved feature provides reduced
mode, as studied in subsection II-A and subsection IV-C. The current ripple at the input, while the built-in transformer and
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High Step-Up DC-DC Converter Using Built-in Transformer Voltage Multiplier Cell and Dual Boost Concepts

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This article has been accepted for publication in a future issue of this journal, but has not been

High Step-Up Dc-Dc Converter Using Built-in

Abstract—This article proposes a new high step-up DC-DC

may not be very attractive [22].

Fig. 4. Current through Dm1 versus C1 variation.

Considering the inductor voltage-second balance principle,

(c) Stage 3 [t3 − t2 ].

Fig. 7. Voltage gain (M ) considering the lossless proposed converter.

B. Static analysis in DCM

0 0.002 0.004 0.006 0.008 0.010

Fig. 9. Voltage gain M as a function of normalized load current io for DCM

Fig. 12. Circuit of the proposed converter for dynamic analysis.

-90 -135 Pm = 60 deg

Fig. 17. Proposed converter prototype.

Parameter / Component Specification

(a) (b) (c)

(d) (e) (f)

(g) (h) (i)

1.06% [9] N. Zhang, D. Sutanto, K. M. Muttaqi, B. Zhang, and D. Qiu, “High-

networks,” IEEE Transactions on Industrial Electronics, vol. 65, no. 7,

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