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Reduced Switching-Frequency-Modulation Algorithm for High-Power

Multilevel Inverters

Article  in  IEEE Transactions on Industrial Electronics · November 2007

DOI: 10.1109/TIE.2007.905968 · Source: IEEE Xplore

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 A Reduced Switching Frequency Modulation Algorithm for High Power Multilevel Inverters

J. Rodrı́guez, S. Kouro, J. Rebolledo and J. Pontt

Universidad Técnica Federico Santa Marı́a
Department of Electronics Engineering
Av. España 1680, Valparaı́so, CHILE
Email: samir.kouro@ieee.org

Multilevel modulation
Abstract— Multilevel inverters have emerged as the state of
the art power conversion systems for high power medium volt- Fundamental Switching High Switching
age applications. Many topologies and modulation methods are Frequency Frequency PWM

commercially available. This paper presents a new adaptive duty Space Vector Selective Harmonic Space Vector Phase Shifted Phase Disposition
cycle modulation algorithm, that reduces the switching frequency Control Elimination PWM PWM PWM
and consequently the switching loses. This can be important
for high power applications, where high frequency modulation a1 a2 a3

methods like PWM are not suitable. Results are shown for a nine
level asymmetric cascaded inverter. Output voltage waveforms Symmetric Opposition Alternate Op-
obtained for references with variable frequencies and amplitudes Disposition Disposition position Disposition

show a similar switching pattern, with a reduced and near

constant number of commutations per cycle, regardless the
reference frequency and amplitude. The proposed modulation
is compared to a Multiple Carrier PWM method, achieving Fig. 1. Principal modulation methods for multilevel inverters.
the same fundamental reference tracking performance with a
reduced number of commutations.
time calculation based on the reference voltage slope is
I. I NTRODUCTION derived, and used to achieve a reduction in the number of
Multilevel inverters are considered today the most suitable commutations.
power converters for high voltage capability and high power The multilevel modulation algorithm proposed in this
quality demanding applications [1]–[4]. Voltage operation paper is applicable to any multilevel inverter topology, with
above classic semiconductor limits, lower common mode an arbitrary number of levels, either for single-phase or
voltages, near sinusoidal outputs together with small dv/dt’s, three-phase applications. In this work, it is tested on a nine
are some of the characteristics that have made this power level, three phase, asymmetric H-bridge cascaded inverter.
converters popular for industry and research, specially for Results are compared, under same conditions, to Multicarrier
medium-voltage applications. PD-PWM .
There are several topologies available, being the Neutral
Point Clamped [5], Flying Capacitor [6] and Cascaded H-
II. T HE I NVERTER
bridge inverter [7] the most studied and used. In recent years
many variations and combinations of these topologies have A generalized power circuit of an asymmetric H-bridge
been reported, one of them is the cascaded H-bridge fed cascaded inverter is shown in Fig. 2. The inverter is composed
by non equal DC sources, known as asymmetric multilevel by the series connection of m monophasic H-bridges fed by
inverter [8], [9]. The main characteristic of this topology is non equal DC sources (vk , with k = 1, . . . , m). The use
the reduction, or even elimination of redundant output levels of asymmetric input voltages can reduce, or when properly
to maximize the output power quality of the inverter using less chosen, eliminate redundant output levels, maximizing the
semiconductors. number of different levels generated by the inverter. Therefore
Many modulation algorithms have been adapted or created this topology can achieve the same output voltage quality
for multilevel inverters [1]–[3]. Most of them are based on with less number of semiconductors, space and costs than the
multiple carrier Pulse Width Modulation (PWM) techniques: symmetric fed topology.
Phase Disposition (PD), Phase Opposition Disposition (POD), When cascading three level inverters like H-bridges (output
Alternative Phase Opposition Disposition (APOD) and Phase levels: −vdc , 0 and +vdc ), the optimal asymmetry is obtained
Shifted (PS) carrier PWM have been studied [10]. Space by using voltage sources scaled proportional to the power of
Vector Modulation (SVM) is also extended for the multilevel three. Applying this criteria to the voltage sources illustrated
case [11]. Selective Harmonic Elimination [12] and Space in Fig. 2, optimal design leads to
⎡ ⎤ ⎡ ⎤
Vector Control [13] are used for lower switching frequency v1 30
applications. These modulation methods are summarized in ⎢ v2 ⎥ ⎢ 31 ⎥
⎢ ⎥ ⎢ ⎥
Fig. 1. ⎢ v3 ⎥ ⎢ 32 ⎥
⎢ ⎥=⎢ ⎥ · vdc . (1)
In this paper, a new modulation method is presented based ⎢ .. ⎥ ⎢ .. ⎥
⎣ . ⎦ ⎣ . ⎦
on time domain duty cycle calculation between the two nearest
output voltage levels to the reference. An adaptive modulation vm 3(m−1)

0-7803-9033-4/05/$20.00 ©2005 IEEE. 867

 a b c v o*
5vdc vo

4v

Voltage Levels
dc

v1 va1 vb 1 vc 1 3vdc

2v
dc
tcom
vdc
v2 va2 vb 2 vc 2
Tm 2Tm 3Tm 4T m
Time
(a)
vo*
5vdc vo
vm vam vbm vcm 4vdc

Voltage Levels
3vdc

2vdc tcom
n
Fig. 2. Asymmetric cascaded H-bridge multilevel inverter. vdc

Tm 2T m 3T m 4T m
Then the individual output voltages per H-bridge are Time
(b)
va1 ∈ {−vdc , 0, +vdc }, vo*
va2 ∈ {−3vdc , 0, +3vdc }, 5vdc vo
.. 4vdc
Voltage Levels

. (2)
vam ∈ {−3(m−1) vdc , 0, +3(m−1) vdc }, 3vdc

for phase a, which is analog for phases b and c of the inverter. 2vdc
The total phase voltages generated by the inverter can be tcom
vdc
expressed as

m 
m 
m
Tm 2Tm 3Tm 4
4Tm
van = vaj ; vbn = vbj ; vcn = vcj . (3) Time
j=1 j=1 j=1 (c)

Replacing in (3) the different combinations of individual Fig. 3. Duty Cycle Modulation: (a) Left-justified timer schedule when
outputs generated by each H-bridge given in (2), a total of dvo∗ /dt > 0; (b) Left-justified timer schedule when dvo∗ /dt < 0; (c) Right-
justified timer schedule when dvo∗ /dt < 0.
3m different levels per phase can be generated to the load.

III. M ODULATION STRATEGY This can be expressed mathematically by

A. Basic principle vo∗ (2Tm ) = v̄o (∆T3 )

 3Tm
The proposed modulation algorithm is based on a com- 1
= vo (t)dt (4)
bination of left-justified timer scheduling and right-justified Tm 2Tm
timer scheduling duty cycle modulation [14], together with  2Tm +tcom  3Tm

1
an adaptive commutation time calculation derived from the = 2vdc dt + 3vdc dt .
Tm 2Tm 2Tm +tcom
voltage reference slope. The aim of the proposed method is
to change the modulation time frame to reduce the switching Then, the commutation time, tcom is computed by solving (4).
frequency. This task can be simplified seeing the modulation of vo∗ (2Tm )
The left-justified timer scheduling operating principle is as a duty cycle between the two nearest output voltage levels.
shown in Fig. 3(a). Consider, for example, the third modulation Then tcom can be easily computed by
period ∆T3 =[2Tm , 3Tm ] in Fig. 3(a) (shadowed area). To
achieve fundamental frequency tracking, the mean output  ∗  ∗

voltage during this period, v̄o (∆T3 ), has to be equal to the vo (2Tm ) vo (2T )
tcom = 1− − f loor · Tm . (5)
sampled reference at the beginning of the interval, vo∗ (2Tm ). vdc vdc

868
Once tcom is calculated by (5), the nearest lower voltage level 1
v *
to the reference, 0.5
o

Voltage [pu]
vo
 ∗
vo (2Tm ) 0
f loor · vdc , (6)
vdc −0.5

is generated from t = 2Tm up to t = 2Tm + tcom , then the −1

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
nearest upper voltage level, Time [s]
 ∗ (a)
vo (2Tm )
ceil · vdc , (7) 1
vdc v *
o
0.5

Voltage[pu]
is generated to complete the duty cycle from t = 2Tm + tcom v
o

to t = 3Tm . 0

The qualitative example explained before and illustrated −0.5

in Fig. 3(a) looks adequate for positive voltage reference −1

slopes. However the negative slope case, shown in Fig. 3(b), 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2
Time[s]
reveals that the commutation sequence (first the lower level
(b)
and then the higher level) still achieves fundamental reference
tracking, but introduces higher harmonic distortion due to Fig. 5. A 9 level asymmetric H-bridge inverter with left&right-justified timer
higher dv/dt’s since a two level difference appears in the schedule modulation: (a) Output voltage for a 50[Hz] reference; (b) Output
voltage for a 10[Hz] reference.
switching pattern. It clearly follows that a right-justified timer
schedule would be more appropriate for the negative slope
case as shown in Fig. 3(c). In this case tcom is computed by Figure 4(a) and (b) show results for a 81 level inverter
(4 asymmetric H-bridges per phase) with left-justified timer

schedule and the combined left&right-justified timer schedule
vo∗ (2Tm ) vo∗ (2T )
tcom = − f loor · Tm . (8) respectively. It is clear that the voltage reference slope sign
vdc vd c
detection reduces dv/dt’s by alternating both methods ade-
Once tcom is determined by (8) first the nearest upper level is quately. This algorithms ensures mean voltage tracking with
generated and is switched to the nearest lower level at tcom . zero error in each modulation interval. However, since the
The slope sign detection and timer schedule justification is modulation period is fixed (Tm = constant), the selected
selected according to the following criteria: value for implementation has to be sufficiently small to allow
good performance for the highest voltage reference frequen-
if vo∗ (t) > vo∗ (t − Tm ),
cies. When using this small Tm for a low frequency refer-
=⇒ use left-justified timer schedule ence, unnecessary additional commutations will be performed
else, (9) with this modulation algorithm (this occurs with all PWM
=⇒ use right-justified timer schedule methods).This effect is shown in Fig. 5(a) and (b), where
the same algorithm (same Tm ) is applied to a 50[Hz] and
10[Hz] voltage references respectively. It can be seen that the
considered modulation period of 1[ms] produces a minimum
1 necessary commutations for the fast reference, while to many
commutations are performed to follow the 10[Hz] reference.
Voltage [pu]

0.5
0
For High power applications those extra switching losses can
Vo be avoided introducing a variable modulation period, which
−0.5 V * should be determined according to the reference frequency.
o
−1
0 0.02 0.04 0.06 0.08 0.1 0.12 B. Adapting the modulation period
Time[s]
It is possible to reduce the number of commutations by
(a) using appropriately an estimation of the voltage reference
1
slope. Assuming for a certain instant t = t(k) that the slope
Voltage [pu]

0.5 mk stays fixed over one modulation period Tmk , and that in
0 addition the difference between two adjacent voltage levels
Vo
is always vdc , a modulation period that produces only one
−0.5 Vo*
commutation can be calculated by
−1 vdc
0 0.02 0.04 0.06 0.08 0.1 0.12 Tmk = , (10)
Time[s] mk
(b) This holds only if no big changes occur in the reference slope,
Fig. 4. Results for a 81 level asymmetric inverter with Duty Cycle
which is common in high power applications.
Modulation: (a) Left-justified timer schedule; (b) left&right-justified timer The estimated slope is calculated using a least squares
schedule with voltage reference slope sign detection. algorithm and some past samples of the voltage reference. For

869
n samples and a fixed sampling period Ts = t(i) − t(i − 1), 2) Use the last n samples to compute the reference slope
the slope is given by mk according to (11), and compare to mmin .
3) Calculate the modulation period Tmk using (10).

k 
k 
k
4) Determine the nearest voltage levels to the reference as
n t(i) · v ∗ (i) − t(i) · v ∗ (i)
i=k−n i=k−n i=k−n
given in (6) and (7).
mk =  2 . (11) 5) Compute commutation time tcom :

k 
k
n· 2
t (i) − t(i) a) using (5), if mk > 0 (left timer scheduling).
i=k−n i=k−n
b) using (8), if mk < 0 (right timer scheduling).
6) Tmk , tcom and the nearest voltage levels are sent to
Figure 6 illustrates this operating principle. For example, at
a FPGA to schedule the commutation and deliver the
t = t2 the slope m2 is computed according to (11), then the
gating signals necessary to generate the desired voltage
modulation period Tm2 is calculated using (10), finally the
levels at the corresponding times.
left timer schedule modulation is performed since m2 > 0.
7) Save the last n voltage reference samples before the
Note that the adaptive modulation time will adjust itself to the
modulation period Tmk is finished.
reference signal.
8) Begin algorithm again.
C. Modulation period saturation
There is however a drawback at this point with this strategy, IV. R ESULTS
from (10) it follows that for mk ’s close to zero, too large Figure 7(a) and (b) show output voltage results for a 9 level
modulation periods are obtained. Therefore Tmk has to be asymmetric H-bridge inverter controlled with the proposed
saturated using a certain criteria; when the estimated slope slope sign detection and adaptive modulation time calculation
of the reference is lower than a specified limit mmin , the last for a 10[Hz] and 50[Hz] reference respectively. The algorithm
modulation time will be used. When the estimated slope is was tested using a least squares estimation with n = 5
higher than mmin the calculated modulation time will be used. samples and a sample period Ts = 10[µs]. It can be seen
This can be summarized as follows: that both waveforms are very similar in shape, due to the
if mk < mmin , adaptation of the algorithm to both reference frequencies. The
results confirm that the algorithm works properly, achieving
=⇒ use Tm(k−1)
fundamental frequency control and similar waveforms, same
else, (12) number of commutations per cycle, independently of the
=⇒ use Tmk voltage reference frequency.
Note that this modulations techniques introduces a zero-
order-hold effect, because of its discrete time nature [14].
The design of mmin will depend on the highest frequency Figure 8 shows the algorithm timer. Each saw tooth
available in the reference bandwidth. represents the execution of the algorithm, showing clearly
how the modulation periods change according to the slope of
D. Algorithm summary the reference. Note that the modulation period is saturated
The following is a simplified overview of the necessary
steps to perform the proposed modulation algorithm:
1
1) Continuously sample the voltage reference at DSP clock vo*
time Ts . 0.5 v
Voltage[pu]

−0.5
4vdc
−1
0 0.02 0.04 0.06 0.08 0.1
m3 Time [s]

3vdc (a)

Tm3 1
vo*
2
m

0.5
Voltage [pu]

v
o

2vdc 0

Tm2 v o*
1

−0.5
m

vo −1
vdc 0 0.02 0.04 0.06 0.08 0.1
Tm1 Time [s]

t1 t2 t3 t4 (b)
Time Fig. 7. Results for a 9 level asymmetric H-bridge inverter with the adaptive
modulation period algorithm: (a) Output voltage for a 10[Hz] reference; (b)
Fig. 6. Adapting modulation time operating principle. Output voltage for a 50[Hz] reference.

870
 0.01 1
Modulation timer [s]

0.008
0.5

Voltage [pu]
0.006
0
v *
0.004 o
−0.5 v
0.002 o
−1
0
0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
Time [s] Time [s]

(a) (a)
1
0.002
Modulation timer [s]

0.5

Voltage [pu]
0
0.001 v *
o
−0.5 vo
−1
0 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time [s]
Time [s]
(b)
(b)
Fig. 9. Response to step change in amplitude and frequency: (a) Proposed
Fig. 8. Adaptive modulation periods: (a) For a 10[Hz] reference; (b) For a
algorithm; (b) Multiple carrier Phase Disposition PWM.
50[Hz] reference.

0.06
THDv = 12.2
when mmin is reached, and that two to three sample periods
Voltage [pu]
0.04
have he same time length until the slope restriction is
deactivated. 0.02

0
V. C OMPARISON 0 200 400 600 800 1000 1200
Frequency [Hz]
1400 1600 1800 2000

Figure 9(a) and (b) present a comparison between the (a)

proposed method and Multiple Carrier Phase Disposition 0.06
THDv = 15.7
PWM operating in a 9 level Asymmetric Inverter. Both
Voltage [pu]

0.04
methods are tested under same conditions, showing the
dynamic behavior when a simultaneous step is applied in 0.02
amplitude and frequency at t = 0.1[s]. Both methods achieve
fundamental frequency control, however the carrier frequency 0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
for the PD-PWM was designed to follow correctly the Frequency [Hz]
high frequency component of the reference, and therefore it (b)
produces a large number of commutations until t = 0.1[s]. Fig. 10. Steady state output voltage spectrum: (a) Proposed Algorithm; (b)
The proposed method adapts the modulation period, obtaining Multiple carrier Phase Disposition PWM.
almost a constant number of commutations per cycle. The
steady state spectrum for both methods for a 10[Hz] reference
are plotted in Fig. 10(a) and (b). As expected, the harmonic Compared to high switching frequency modulations meth-
content for PD-PWM is concentrated around multiples of ods (like carrier based PWM), less commutations are obtained
the carrier frequency 1[kHz), while the proposed algorithm while achieving same reference tracking. This makes the
produces a dispersed low frequency harmonic content. This algorithm suitable for high power applications.
is a drawback considering the filtering nature of most loads. Compared to low frequency modulation methods, the
However this work is focused for high power applications proposed algorithm ensures fundamental reference tracking,
where reducing commutation losses is required. If this issue and also can be applied to inverters with reduced number
becomes relevant the use of an output filter is recommended. of levels and achieves high quality outputs even for low
modulation indexes (not achieved with Space Vector Control).
In addition it is easy to implement and not limited to pure
VI. C ONCLUSION
sinusoidal references (necessary for Selective Harmonic
In this paper a new duty cycle modulation technique, with Elimination).
adaptive modulation periods has been presented. Reduced
commutations and similar output voltage quality, indepen-
dently of the reference frequency, are the main features ACKNOWLEDGMENT
achieved. The authors gratefully acknowledge financial support pro-
The algorithm is by nature developed in discrete time, vided by the Chilean National Fund of Scientific and Tech-
and therefore its DSP implementation is straightforward. The nological Development (Fondecyt), under grant No. 1040183,
algorithm can be easily extended for any multilevel inverter and by the General Direction of Research (DGIP) of the
topology, either for one or three-phase applications. Universidad Técnica Federico Santa Marı́a.

871
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