Assembly Language for Intel-Based

Computers, 4th Edition

Kip R. Irvine

Chapter 2: IA-32 Processor

Architecture

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 Chapter Overview

• General Concepts
• IA-32 Processor Architecture
• IA-32 Memory Management
• Components of an IA-32 Microcomputer
• Input-Output System

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 2

 General Concepts

• Basic microcomputer design

• Instruction execution cycle
• Reading from memory
• How programs run

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 3

 Basic Microcomputer Design
• clock synchronizes CPU operations
• control unit (CU) coordinates sequence of execution
steps
• ALU performs arithmetic and bitwise processing

data bus

registers

I/O I/O
Central Processor Unit Memory Storage
Device Device
(CPU) Unit
#1 #2

ALU CU clock

control bus

address bus

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 Clock
• synchronizes all CPU and BUS operations
• machine (clock) cycle measures time of a single
operation
• clock is used to trigger events

one cycle

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 5

 Instruction Execution Cycle

PC program
• Fetch I-1 I-2 I-3 I-4
fetch
• Decode memory
op1
read
op2
• Fetch registers registers
operands I-1
instruction
register
• Execute

decode
• Store output
write

write
flags ALU

execute
(output)

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 Multi-Stage Pipeline
• Pipelining makes it possible for processor to execute
instructions in parallel
• Instruction execution divided into discrete stages
Stages
Example of a non- S1 S2 S3 S4 S5 S6
pipelined 1 I-1
2 I-1
processor. Many 3 I-1
wasted cycles. 4 I-1
5 I-1
Cycles

6 I-1
7 I-2
8 I-2
9 I-2
10 I-2
11 I-2
12 I-2

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 7

 Pipelined Execution

• More efficient use of cycles, greater throughput of instructions:

Stages
S1 S2 S3 S4 S5 S6
1 I-1 For k states and n
2 I-2 I-1 instructions, the
Cycles

3 I-2 I-1
number of required
4 I-2 I-1
5 I-2 I-1 cycles is:
6 I-2 I-1
k + (n – 1)
7 I-2

Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 8

 Wasted Cycles (pipelined)
• When one of the stages requires two or more clock
cycles, clock cycles are again wasted.
Stages
exe
S1 S2 S3 S4 S5 S6
1 I-1
2 I-2 I-1 For k states and n
3 I-3 I-2 I-1
instructions, the
Cycles

4 I-3 I-2 I-1

5 I-3 I-1 number of required
6 I-2 I-1 cycles is:
7 I-2 I-1
8 I-3 I-2 k + (2n – 1)
9 I-3 I-2
10 I-3
11 I-3

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