5 4 3 2 1

Celullar ANT

BPI, APC
FEM
EMI x32
EMI
TX RX
Memory
MCP
NFI RF IQ
D NFI D

BSI ctrl MT6166 RX

balun

micro SD MSDC 4-bit

MSDC1
26M_BB
+ hot-plug 26M
26M_AUD
DCXO ctrl

MT6572
26M_CN
ABB 26M_CN

TCXO
Connectivity ANT
SPI CONN IQ
CMMB
EINT
CONN ctrl
MT6627

C C

RTC 32K
32K_BB
Camera Camera IF CAM
Module (MIPI / Parallel)

2nd Camera Camera IF MT6323 Headset

(HPL, HPR, AU_VIN1)
Module

I2C
i2C_0 Class D/AB

LCD LCD IF LCD Audio

module (MIPI / Parallel) AUD I/F
Speech Receiver

CTP I2C
i2C_1 AU_VIN0
controller EINT

B B
I2C
Motion
EINT
Sensor
POWER
I2C

ALS + PXS
EINT
Power SIM2
SPI SIM2
I2C
Management
Magnetic
SIM1
sensor EINT SIM1

VIB
I2C
Gyro BC1.1
sensor EINT Charger

Charger
Battery
Keypad

BJT
JTAG
A A
Debug micro USB
USB 2.0
port USB
UART

Title
MT6572 Block diagram
Size Document Number Rev
D V1.0

Date: Friday, December 28, 2012 Sheet 1 of 15

5 4 3 2 1
 5 4 3 2 1

GND
100nF
0201
U101-H

C108

[2,3,4,5,6,7,9,15] VIO18_PMU T25 F1

DVDD18_MIPIRX AVDD28_DAC VTCXO_PMU [4,7]
U25 DVSS18_MIPIRX
AVDD18_AP E5

R25 DVDD18_MIPITX DVDD18_PLLGP U9 [2,3,4,5,6,7,9,15]

VIO18_PMU
P25 DVSS18_MIPITX
D D

AVDD18_MD D3 VIO18_PMU [2,3,4,5,6,7,9,15]

H23 AVDD18_USB AVSS18_MD A1
[2,3,4,5,6,7,9,15] VIO18_PMU
G24 AVDD33_USB AVSS18_MD A4
[4] VUSB_PMU
G23 AVSS33_USB AVSS18_MD C3 C112 C128
AVSS18_MD E2
0201 0201
100nF 100nF

C104 C113 F6 BG
C107 C101 REFP GND GND
C109
0201 0201 0201 0402
100nF 1uF G6 REFN
100nF 100nF
0402
1uF
MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
MT6572TA

GND
GND GND GND GND GND

dedicate VSS ball, must return to cap then to main GND:

1. REFN(G6) => C109
2. DVSS18_MIPIRX(U25) => C107
4. C101,C104,C107,C108,C109,C112,C113,C128 close to BB U101-B
1.8V IO for DDR1
W9 1.2V IO for DDR2
VCCIO_EMI VIO_EMI [5]
W12
VCC VCCIO_EMI C405 C406 If double-sided SMT, put C405 & C406 below BB.
VCCIO_EMI W14
AC21 GND
Memory
VCCIO_EMI W16 If single-sided SMT, put C405 & C406 around memory.
AD11 GND VCCIO_EMI W19 0201 0201
AF13 100nF 100nF
GND
AB11 GND GND
GND
C AC8 GND C
AB5 GND
AB14 DVDD
GND if use emmc,DVDD18_MC0 should add a 100nF cap
W26 Peripheral AA1
GND DVDD18_MC0 VIO18_PMU [2,3,4,5,6,7,9,15]
T15 GND DVDD18_CAM K20
W23 GND DVDD18_VIO_1 L3
T14 GND DVDD18_VIO_2 J19
AF26 GND DVDD18_VIO_3 H13
G3 AB24 R119 0R
GND DVDD18_LCD 0402
K21 GND
L11 C126
GND 100nF
L12 GND 0201
L14 GND DVDD3_MC1 K24 VMC_PMU [4] 0402
L15 1uF C138
GND
L16 GND DVDD3_LCD W24
GND
M5 GND
M11 GND DVDD28_BPI C10 VIO28_PMU [4,9,15] C121
M12 GND R119,C121
M13 GND C117 0402 Based on your system level
M14 GND 1uF
M15 GND C117 Close to BB IC, recommand < 150mil design , if better FM performance
M16 VCC P6 0402
GND VCCK_CPU GND
N10 CPU T7
1uF is needed on your system ,
GND VCCK_CPU GND
N8 GND VCCK_CPU P7 please refer to FM desense
N9 GND VCCK_CPU P8
N11 P9 performance enhance proposal
GND VCCK_CPU
N12 GND VCCK_CPU R6
N13 GND VCCK_CPU R7
N14 GND VCCK_CPU R8
N15 GND VCCK_CPU R9
N16 GND VCCK_CPU T6
P10 GND VCCK_CPU U6
N22 GND VCCK_CPU T9
P11 GND VCCK_CPU T8
P12 GND VCCK_CPU U7
P13 GND
P14
P15
GND
GND
120mil
B VPROC_PMU [4] B
P16 GND
R10 GND
R11 VCC J9
GND Core VCCK
R12 GND VCCK J15
R13 GND VCCK M9
R14 GND VCCK K6
R15 GND VCCK K7
R16 GND VCCK K8
T10 GND VCCK K9
T11 GND VCCK K11
T12 GND VCCK K14
T13 GND VCCK K15
C136

C137

AF1 VSS VCCK M10

VCCK K16 C114 C115 C118 C116 C135 C120 C134 C119 C111 C106 C102 C103
U10 VSS VCCK K17
U11 U17
2.2uF 0402

0402 0402 0402 0402

2.2uF 0402

VSS VCCK 0201 0201 0201 0201 0603 0603 0603 0603
V13 VSS VCCK M17 100nF 100nF 100nF 100nF 1uF 1uF 1uF 1uF 4.7uF 10uF 10uF 10uF
W11 VSS VCCK L7
Y21 VSS VCCK L8 GND GND GND GND
VCCK L9
VCCK L17
VCCK M6 R101 0R
M7 0201 GND_VPROC_FB [4]
VCCK
GND VCCK M8 feedback-4mil - defferential - GND shielding
R102 0R
J17 0201 VPROC_FB [4]
VCCK
VCCK J16
VCCK R17
T16
Vproc remote sense :
VCCK
VCCK L6 differential 4mil with good shielding, from the BB to PMIC
VCCK K12
VCCK T17
VCCK J10
VCCK J11
VCCK U12
VCCK U13
VCCK U14
VCCK U15
A VCCK U16 A
VCCK J8
VCCK J14

A26 DUMMY

MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
MT6572TA

Title
BB- Power
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Wednesday, January 02, 2013 Sheet 2 of 15

5 4 3 2 1
 5 4 3 2 1

SPI&SIM PART

PMIC_SPI_CSN,AUD_DAT_MOSI

00,use pin map for LPDDR1

01,use pin map for LPDDR2
1x,use pin map for PCDDR3
RF PART CAM&LCM PART
U101-G
U101-A
BPI_BUS[0:6] are 2.8V GPIO,power with DVDD28_BPI(VIO28_PMU) U101-D
[7] RX_I_P D2 DL_I_P BPI_BUS0 B12 BPI_0 [7] [15] SDA_2 L25 CMPDN2 MIPI_2nd_CAM
C2 DL_I_N BPI_BUS1 B11 for GSENSOR [15] SCL_2 K25
D [7] RX_I_N BPI_1 [7] CMRST2 D
B1 C12 [4] AUD_MISO J1 AUD_DAT_MISO H22 Parallel 8-bit
[7] RX_Q_P DL_Q_P BPI_BUS2 BPI_2 [7] [10] CMPDN CMPDN
C1 A11 K5 AUD_CLK_MOSI J22
[7] RX_Q_N DL_Q_N BPI_BUS3 BPI_3 [7] [4] AUD_CLK CMRST
K1 [10] CMRST
[4] AUD_MOSI AUD_DAT_MOSI
D11
BPI_BUS4=0,boot from emmc/nand(default) Y22
BPI_BUS4 BPI_4[7] CMMCLK CMMCLK [10]
[7] TX_I_P A2 UL_I_P BPI_BUS5 C11 BPI_5 [7]
BPI_BUS4=1,boot from SD/SPI-NAND [4] PMIC_SPI_MOSI L2 PMIC_SPI_MOSI R24
L5 RDN0 MIPI_CAM
[7] TX_I_N B2 UL_I_N BPI_BUS6 A13 [4] PMIC_SPI_MISO PMIC_SPI_MISO R23 Y23
RDP0 CMPCLK CMPCLK[10]
B4 [4] PMIC_SPI_SCK L4 PMIC_SPI_SCK R22
[7] TX_Q_P UL_Q_P RDN1
K2
[7] TX_Q_N
B3 UL_Q_N BPI_BUS7 A10 W_PA_B1_EN [7] [4] PMIC_SPI_CS PMIC_SPI_CSN MIPI 100-ohm differential R21 RDP1 RCN_A V25 CMVSYNC[10]
BPI_BUS8 B10 R26 W25
GPIO_SPK_EN[6] RCN RCP_A CMHSYNC[10]
D10 [4,5] WATCHDOG G2 WATCHDOG T26 V24
BPI_BUS9 RCP RDN1_A CMDAT7[10]
E9 [4,7] SRCLKENA H4 SRCLKENA V23
BPI_BUS10 W_PA_B8_EN [7] RDP1_A CMDAT6[10]
E8 [4] EINT_PMIC J2 EINTX P19 U22
BPI_BUS11 [9] MIPI_TDN0 TDN0 RDN0_A CMDAT5[10]
B9 P20 MIPI_LCD U21
BPI_BUS12 EINT_HP[6] [9] MIPI_TDP0 TDP0 RDP0_A CMDAT4[10]
[7] VM0 A8 VM0 BPI_BUS13 B8 N25
TP_ID [9] TDN1
A7 E7 [3,4] SIM1_SCLK H5 SIM1_SCLK N26 Y26
[7] VM1 VM1 BPI_BUS14 TDP1 CMDAT3 CMDAT3[10]
D7 [4] SIM1_SIO M3 SIM1_SIO P23 Y25
BPI_BUS15 TDN2 CMDAT2 CMDAT2[10]
P24 TDP2 CMDAT1 AA25 CMDAT1[10]
[7] TXBPI D5 TXBPI BSI_DATA2 D6 BSI-A_DAT2 [7] [9] MIPI_TCN N20 AB25 CMDAT0[10]
J5 TCN CMDAT0
BSI_DATA1 C7 BSI-A_DAT1 [7] [4] SIM2_SCLK SIM2_SCLK N19
[9] MIPI_TCP TCP
F2 F9 M1 SIM2_SIO
[7] VAPC1 APC BSI_DATA0 BSI-A_DAT0 [7] [4] SIM2_SIO
BSI_EN F11 BSI-A_EN [7]
F3 G11

GND
VBIAS BSI_CLK BSI-A_CK [7]
R202 1.5K P26
0402 VRT
MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
MT6572TA
R202 close to BB

MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
MT6572TA
MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
MT6572TA

C C

U101-E D12 PWM_A NP when power on,should add PD RES when use

[7] CLK1_BB E1 CLK26M PWM_A D12

SYSTEM PWM E12
PWM_B EINT_CTP [9]
[4] CLK32K_BB H2 CLK32K_IN

M2 SYSRSTB LPD17 N1
[4] RESETB LCD
LPD16 N2 LCD_BK_EN_PMIC[9]
GND G4 Parallel N3
C201 TESTMODE LPD15
LPD14 P2
GND AC24 FSOURCE LPD13 N4
0201 LPD12 R2
NC(330PF) N5
LPD11
GND [4] J26 R1
CHD_DP CHD_DP LPD10
J25 BC 1.1 P5
[4] CHD_DM CHD_DM LPD9
LPD8 T1
LPD7 R5
[11] USB_DM G26 USB_DM LPD6 T2
USB 2.0
90-ohm differential [11] USB_DP
G25 USB_DP LPD5 T5
R203 5.1K H25 U2
R203 close to BB 0402 USB_VRT LPD4
GND

LPD3 T3
LPD2 U5
i2C
for CAM,Power by CAM_IO
[10] SCL_0
C25
C26
SCL_0 LPD1 T4
V2
reserve for JTAG debug
[10] SDA_0 SDA_0 LPD0
[9] B24 SCL_1 VIO18_PMU [2,4,5,6,7,9,15]
SCL_1
for CTP [9] SDA_1 B23 SDA_1
B B

LPCE0B AD25 R209 NC(20K)

F24 AB26 [3,4] SIM1_SCLK 0402
SPI_MISO LPTE LPTE [9]
F25 SPI_MOSI
SPI
LRSTB AC26 LRSTB [9]
MT6572 support JTAG from below :
F23 SPI_SCK LPRDB AA22
[15] EINT_GY E23 SPI_CS LPA0 AB23 1. KP (recommand),JTAG:R209=20K,normal:R209=NC
LPWRB AC25 GPIO_CTP_RSTB[9]
2. MC1
[12] MC1CMD K23 MC1_CMD T-flash KP KROW0 B25 KCOL0=0,force USB DL mode in bootrom
TEST203
3. CAM
L21 MC1_CK KROW1 A24
[12] MC1CK KCOL0=1,NA(default)
[12] MC1DAT0 K22
M22
MC1_DAT0 KROW2 B26
C24
JTMS for JTAG pin out from MC1/CAM, refer
[12] MC1DAT1 MC1_DAT1 KCOL0 KCOL0 [11]
M25 D24 TEST204
[12] MC1DAT2
L26
MC1_DAT2 KCOL1
A25
KCOL1 [14] to HW design notice
MC1_DAT3 KCOL2
[12] MC1DAT3
KCOL2 [14]
JTCK
B7 E25 R201 1K TEST201
[9] LCD_ID AUX_IN0 ADC UART UTXD1 0201
B6 D25 R208 1K
AUX_IN1 URXD1 0201
C5 E26 R210 1K
AUX_IN2_XP UTXD2 0201
B5 F26 R211 1K
AUX_IN3_YP URXD2 0201 TEST202
C4 AUX_IN4_XM
A5 AUX_IN5_YM TEST206
GND

TEST207

MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
MT6572TA
TEST205
FCHR_ENB [4]

A A

SH4

1
SH2
SH3
MARK
1 1

MK201 MK202 MK203 MK204

1 1 1 1

Title
SMT MARK SMT MARK SMT MARK SMT MARK
GND GND GND
BB - peripheral
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Wednesday, January 02, 2013 Sheet 3 of 15

5 4 3 2 1
 5 4 3 2 1

1. charge part Close to Battery Connector.

(Rsense (R328) <10mm)
Charger 2. Main path should be 40mil.
(VBUS -> U303's E, -> U303's C -> R328 -> VBAT)
3. Star connection from R328 to BAT Connector

VBUS [11]

D D

R329 330K/1%
0402 VCDT [4] VCDT rating:
VCDT 1.268V
rating: 1.268V
U301
GND

C329 MT6323/VFBGA145/P0.4/B0.25/5.8X5.8
R324 39K/1%
C329 cap rating depends on 0402
Phone OVP spec. 0603 0R
1uF/50V [4,6,7,9] VBAT
R336 SPK_P K1 AU_SPKP [6]
40mils 0603
SPK
2.2uF

L1
C313

SPK_N AU_SPKN [6]

C362 P1 VBAT_SPK
GND if you use digital MIC, 100nF
L2 GND_SPK AU_HSP H1 AU_HSP [6]
0402
GND

0402
please change cap (C312) REC AU_HSN G1 AU_HSN [6]
R331 3.3K
0402 CHR_LDO [4]
to 1.0uF AU_HPL H4 AU_HPL [6]
[6] MICBIAS0 F2 AU_MICBIAS0 EARPHONEAU_HPR J4 AU_HPR [6]
6

G2 AU_MICBIAS1
C C E [6] MICBIAS1
C312
Before you select BJT U303, please take C315
40mils U303
power dissipation into consideration. [6] AU_VIN0_P E4 E9
WPT2F30 0402 0201 AU_VIN0_P AUDIO DRIVER ISINK0
Refer to MT6323 design notice 1uF 100nF
main mic
[6] AU_VIN0_N
F4 AU_VIN0_N ISINK1 C9
C C B
GND
ISINK2 E10
GND
1

U305 G3 C10
1

[6] AU_VIN1_P AU_VIN1_P ISINK3

PNM723T703E0-2 earphone mic [6] AU_VIN1_N
G4 AU_VIN1_N
3 2
VDRV [4]
[4] VA_PMU D2 AU_VIN2_P
D1 AU_VIN2_N
40mils
4mil GND
C314 J2 AVDD28_ABB
TP301 TP302 TP303 D3

1PS79SB30,115
AVDD28_AUXADC
ISENSE [4] 0402 H2 GND_ABB
R328 Differential 4mil to PMU 1uF
R328 Rsense 0805 VBAT [4,6,7,9]
0.2R/1%

D301
GND

[6] ACCDET
E2 ACCDET
4mil BUCK OUTPUT
VPROC C14
E1 D14 L301 0.68uH
[7] CLK4_AUDIO CLK26M VPROC VPROC_PMU [2]
40mils LPS2520H1MM2
16.9K/1%

VPROC E14

BAT CONN AUXADC_REF [4] C357 NC(1nF)

0201
VPROC_FB B12 VPROC_FB [2]
CHARGER
GND_VPROC_FB C12 GND_VPROC_FB [2]
0402

[4,6,7,9] VBAT P13 BATSNS

P12 A14 L301,L303 Please use inductor recommand by MTK
differential to Rsense [4] ISENSE ISENSE VPA
R334

K3 BATON VPA B14

[4] BAT_ON Refer to MT6323 design notice
A12 VCDT
C [4] VCDT C
J301 40mils 40mils M13 VDRV VPA_FB D12 D301,D302,Ifsm>500mA,Vf<500mV when If=100mA
[4] VDRV
1 VBAT [4,6,7,9]
4 2 1K
R317 BAT_ON [4] [4] CHR_LDO N13
3 0402 CHRLDO
27K/1%

C316 H14 L303 0.68uH

C317 VSYS VSYS_PMU [4]
FV301 R334,R335 must to be close to
6
5

FV302 LPS2520H1MM2
D305 C316 Close to PMIC CONTROL SIGNAL
GND

C360 C344 C345 PMIC AUXADC_REF pin 0402 0402 D302

PAN30-03466-S10701 1uF 1uF [14] PWRKEY M2 PWRKEY
if battery NTC is 10kohm, R334=16.9K, R335=27K
0402

0603 0603 0402 [3,5] WATCHDOG

A1 SYSRSTB
22uF 22uF 100nF if battery NTC is 47kohm, R334=61.9K, R335=100K GND K4 1PS79SB30,115
GND RESETB
GND [3] RESETB ALDO OUTPUT
R335

ZENER-MM3Z5V1-5 ESD9X5.0ST5G ESD9X5.0ST5G Refer to MT6323 HW design notice GND A9 FSOURCE VA M3

VA_PMU [4]
[3] EINT_PMIC A7 INT
N12 EXT_PMIC_EN VCN28 N3 VCN_2V8_PMU [8]
VTCXO L4 VTCXO_PMU [2,7]
GND N2 PMU_TESTMODE
GND GND P3
GND VCAMA VCAMA_PMU [10]
[3] AUD_MOSI
E7 AUD_MOSI VCN33 M6 VCN_3V3_PMU [8]
D305 E8 AUD_CLK AVDD33_RTC C3 VRTC
[3] AUD_CLK
VF : 4.85V~5.36V [3] AUD_MISO B6 AUD_MISO

1K
500mW
[3,7] SRCLKENA A2 SRCLKEN C355 C356
Add Zenar Diode Place on the path M1 DLDO OUTPUT

0402
[3] FCHR_ENB FCHR_ENB
from VBAT to IC (Battery connector VM J13 VM_PMU [5] 0402
0402
D9 SPI_CLK VRF18 H11 1uF 100nF
or test point or IO connector) [3] PMIC_SPI_SCK VRF18_PMU [7] R312
B7 SPI_CSN VIO18 L12 VIO18_PMU [2,3,4,5,6,7,9,15]
HW trapping PIN [3] PMIC_SPI_CS
GND
Refer to MT6323 design [3] PMIC_SPI_MOSI
D8 SPI_MOSI VIO28 M4 VIO28_PMU [2,9,15] GND
VBAT [4,6,7,9] R303=20K,VM=1.8V B8 J12
GND

notice for Zener selection [3] PMIC_SPI_MISO SPI_MISO VCN18 VCN_1V8_PMU [8]
R303 20K K14 ==> for longer RTC time sustain after battery remove,
R303=NC,VM=1.2V 0402 VCAMD VCAMD_PMU [10]
VCAM_IO L13 VCAMD_IO_PMU [10]
F13 VBAT_VPROC
VBAT INPUT please refer to RTC design notice
80mil 40mil F14 VBAT_VPROC
G13 VBAT_VPROC VEMC_3V3 P7 VEMC_3V3_PMU C325
R120 NC 4mil (VPA no use)
A13 VBAT_VPA VMC L6 VMC_PMU [2]
0201
FV303 VMCH P4 VMCH_PMU [12] 0603
C361 15mil H13 N6 C354
C359 C310 VBAT_VSYS VUSB VUSB_PMU [2] NC(22uF)
P8 P9
20mil VBAT_LDOS3 VSIM1 VSIM1_PMU [13]
P6 VBAT_LDOS3 VSIM2 N9 VSIM2_PMU [13] 0201
0603
NC(22uF)22uF
0603 0402
100nF 20mil P5 VBAT_LDOS2
analog LDO VGP1 L8
CTP_2.8V_PMU [9] 100nF GND
20mil P2 VBAT_LDOS1 GND
ESD9X5.0ST5G

[4] VSYS_PMU
20mil J14
M14
AVDD22_BUCK
AVDD22_BUCK
VIBR
VGP2
VGP3
M7
N8
L14
VIBR_PMU [4]
VGSENSOR_PMU [15] Vibra
VCAM_AF N7 CTP_1.8V_PMU [9]
GND GND
A8 DVDD18_DIG VIBR_PMU [4]

[2,3,4,5,6,7,9,15] VIO18_PMU A5 DVDD18_IO

B AUXADC B
[4] AUXADC_REF C2 AUXADC_VREF18
B1 AUXADC_AUXIN_GPS VREF P14
B2 AVSS28_AUXADC
C323 C320

1
0201 0201 dedicate VSS ball, must return to cap then to main GND:

P
100nF BC 1.1 C311
100nF
1. GND_VREF(N14) => C320 VIB301
A10 N14

N
[3] CHD_DM CHG_DM GND_VREF
GND A11 0402
[3] CHD_DP CHG_DP

2
GND 1uF
RTC 32K : X301+C324+C319=> mount, R333=> NC
D5 32K-less: X301+C324=> remove, C319+R333=> 0R VXODIG domain select
SIM LVS RTC RTC_32K1V8 CLK32K_BB [3]
RTC_32K2V8 C4
[3] SIM1_SCLK B5 SIM1_AP_SCLK XIN A3 32K_IN Logic DCXO_
M11 A4 32K_OUT MODE XMODE VXODIG
[3] SIM1_SIO SIMLS1_AP_SIO XOUT 2
32K_EN GND
E6 1
SIM1_AP_SRST
C301 C303 C304 C305 C302 C306 C309 C307 C308 X301 Q13MC1461000200// Q13MC1462000200
[3] SIM2_SCLK C5 SIM2_AP_SCLK GND_ISINK B10
3

0603 0603 0402 0402 0402 0603 0603 0402 0402 K11 SIMLS2_AP_SIO GND_VSYS G11 C324
[3] SIM2_SIO C319
10uF 10uF 1uF 1uF 1uF 10uF 10uF 1uF 1uF D6 SIM2_AP_SRST GND_VPA E13
E11 GND DCXO + 32K XO default 0(GND) 1(VIO18) 1(VIO18)
GND_VPROC 0201 0201
M9 SIMLS1_SCLK GND_VPROC F11 18pF
[13] SCLK 18pF
N11 SIMLS1_SIO GND_VPROC F10
[13] SIO
M10 DCXO + 32K-Less 1(VTXCO28) 1(VTXCO28) 1(VTXCO28)
Refer to MT6323 design notice GND GND
[13] SRST SIMLS1_SRST
GND_LDO K6 GND
K9 K8
for Buck GND layout rule [13] SCLK2
L11
SIMLS2_SCLK GND_LDO Close to chip
[13] SIO2 SIMLS2_SIO
K10 SIMLS2_SRST GND_LDO F5
[13] SRST2
GND_LDO F6
GND_LDO F7 R333 NC
F8 0201 DCXO_32K [7]
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO

GND_LDO F9
GND_LDO G5
GND_LDO G6
J10
J9
J8
J7
J6
H10
H9
H8
H7
H6
H5
G9
G8
G7

GND

MT6323A

A A

Title
PMIC
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 4 of 15

5 4 3 2 1
 5 4 3 2 1

D D

R401 0R
Memory MCP
1.8V [4] VM_PMU 0402 VIO_EMI [2,5]

VIO_EMI [2,5]

MT6572 MEMORY PART U401

C9 G8
4.7uF

VDDQ CLK EDCLK [5]

C401

0603

Please make sure the ball map is D10

E9
VDDQ
VDDQ
CLK#
CKE0
H8
E3
EDCLK_B [5]
ECKE [5]
F10 J2
GND

VDDQ CS0# ECS0_B [5]

match to the MCP type you selected G9
J10
VDDQ RAS# G2
H2
ERAS_B [5]
VDDQ CAS# ECAS_B [5]
Put C402 & C403 between BB & memory. K9 K1 EWR_B [5]
VDDQ WE#
0201 0201 0201 0201
100nF 100nF 100nF100nF

L9 J3 EBA0 [5]
C403 C402

VDDQ BA0
M10 K2 BA[1:0] = EA[15:14] (LPDDR1)
VDDQ BA1 EBA1 [5]
N9 J8
GND GND

U101-F VDDQ DM0 EDQM0 [5]

DM1 G6 EDQM1 [5]
H10 VDDD DM2 F8 EDQM2 [5]
AF6 H1 E7
C408 C407

[5] ED31 ED31__DDR1_ VDDD DM3 EDQM3 [5]

[5] ED30 AE6 ED30__DDR1_ ECS0_B__DDR1_ AF22 ECS0_B [5] M1 J7
VDDD DQS0 EDQS0 [5]
[5] ED29 AF8 ED29__DDR1_ ECS1_B__DDR1_ AF19 ECS1_B [5] B8 G5
VDDD DQS1 EDQS1 [5]
C AE7 ED28__DDR1_ D1 H7
[5] ED28 VDDD DQS2 EDQS2 [5] C
AE8 ED27__DDR1_ EWR_B__DDR1_ AF21 EWR_B [5] P8 E5
[5] ED27 VDDD DQS3 EDQS3 [5]
AC9 AD21 ERAS_B [5]
C129

[5] ED26 ED26__DDR1_ ERAS_B__DDR1_

0201 0603 0402
100nF 4.7uF 1uF

[5] ED25 AC7 ED25__DDR1_ ECAS_B__DDR1_ AB20 ECAS_B [5] C1 L4 ED0 [5]
AB9 AD24 VSSD DQ0
[5] ED24 ED24__DDR1_ ECKE__DDR1_ ECKE [5] J1 L5 ED1 [5]
GND

VSSD DQ1
C110

[5] ED23 AF5 ED23__DDR1_ B9 L6 ED2 [5]

AE5 AB13 VSSD DQ2
[5] ED22 ED22__DDR1_ EDQM0__DDR1_ EDQM0 [5] H9 L7 ED3 [5]
AD5 AD12 VSSD DQ3
EDQM1 [5]
GND

[5] ED21 ED21__DDR1_ EDQM1__DDR1_ P9 K8 ED4 [5]

C409

AC5 AD8 VSSD DQ4

[5] ED20 ED20__DDR1_ EDQM2__DDR1_ EDQM2 [5] M2 L8 ED5 [5]
AE4 AE12 VSSD DQ5
[5] ED19 ED19__DDR1_ EDQM3__DDR1_ EDQM3 [5] K7 ED6 [5]
AF3 DQ6
[5] ED18 ED18__DDR1_ N10 VSSQ DQ7 K5 ED7 [5]
[5] ED17 AF2 ED17__DDR1_ EDQS0__DDR1_ AA14 EDQS0 [5] GND M9 K6 ED8 [5]
AB6 Y13 VSSQ DQ8
[5] ED16 ED16__DDR1_ EDQS1__DDR1_ EDQS1 [5] J9 G7 ED9 [5]
AE11 Y8 VSSQ DQ9
[5] ED15 ED15__DDR1_ EDQS2__DDR1_ EDQS2 [5] G10 J6 ED10 [5]
AD15 AA9 VSSQ DQ10
[5] ED14 ED14__DDR1_ EDQS3__DDR1_ EDQS3 [5] F9 J5 ED11 [5]
AE10 VSSQ DQ11
[5] ED13 ED13__DDR1_ E10 VSSQ DQ12 H6 ED12 [5]
GND

[5] ED12 AE9 ED12__DDR1_ EDQS0_B Y14 L10 H5 ED13 [5]

AF12 AA13 VSSQ DQ13
[5] ED11 ED11__DDR1_ EDQS1_B K10 VSSQ DQ14 J4 ED14 [5]
[5] ED10 AF11 ED10__DDR1_ EDQS2_B AA8 D9 G3 ED15 [5]
AF9 Y9 VSSQ DQ15
[5] ED9 ED9__DDR1_ EDQS3_B C10 G4 ED16 [5]
AC13 VSSQ DQ16
[5] ED8 ED8__DDR1_ DQ17 F4 ED17 [5]
[5] ED7 AE16 ED7__DDR1_ EDCLK0_B Y18 EDCLK_B [5] K4 E4
[5] EA0 A0 DQ18 ED18 [5]
AE13 ED6__DDR1_ EDCLK0 AA18 EDCLK [5] L1 F5 ED19 [5]
[5] ED6 [5] EA1 A1 DQ19
AE15 ED5__DDR1_ L2 H3
[5] ED5 [5] EA2 A2 DQ20 ED20 [5]
[5] ED4 AE14 ED4__DDR1_ EDCLK1_B AA19 L3 H4
[5] EA3 A3 DQ21 ED21 [5]
[5] ED3 AF15 ED3__DDR1_ EDCLK1 Y19 C2 E6 ED22 [5]
[5] EA4 A4 DQ22
AF16 ED2__DDR1_ D2 F7
[5] ED2 [5] EA5 A5 DQ23 ED23 [5]
[5] ED1 AC15 ED1__DDR1_ E1 F6 ED24 [5]
[5] EA6 A6 DQ24
[5] ED0 AB16 ED0__DDR1_ ND0__DDR1_ AA2 NLD0 [5] D3 D5 ED25 [5]
Y2 [5] EA7 A7 DQ25
ND1__DDR1_ NLD1 [5] E2 E8 ED26 [5]
AB17 W1 [5] EA8 A8 DQ26
VREF1 ND2__DDR1_ NLD2 [5] D4 D6 ED27 [5]
AC11 W3 [5] EA9 A9 DQ27
VREF0 ND3__DDR1_ NLD3 [5] K3 D8 ED28 [5]
A10 DQ28
GND

AB1 [5] EA10

ND4__DDR1_ NLD4 [5] F2 D7 ED29 [5]
AD2 [5] EA11 A11 DQ29
ND5__DDR1_ NLD5 [5] F1 C8 ED30 [5]
AB18 W4 [5] EA12 A12 DQ30
EA18__DDR1_ ND6__DDR1_ NLD6 [5] C7 ED31 [5]
1.8V VIO18_PMU [2,3,4,5,6,7,9,15] DQ31
GND

AE18 EA17__DDR1_ ND7__DDR1_ AE1 NLD7 [5] R1

AE17 W2 DNU
EA16__DDR1_ ND8__DDR1_ NLD8 [5] R2 P2 NLD8
AE21 Y3 DNU NLD8
BA[1:0] = [5] EBA1 EA15__DDR1_ ND9__DDR1_ NLD9 [5] R9 P3 NLD9
B AB19 AC2 DNU NLD9 B
EA[15:14] [5] EBA0 EA14__DDR1_ ND10__DDR1_ NLD10 [5] R10 N4 NLD10
AE22 AC1 DNU NLD10
(LPDDR1) [5] EA13 EA13__DDR1_ ND11__DDR1_ NLD11 [5] B5 P4 NLD11
AC23 Y4 VCCN NLD11
[5] EA12 EA12__DDR1_ ND12__DDR1_ NLD12 [5] N5 P5 NLD12
AD22 V5 VCCN NLD12
[5] EA11 EA11__DDR1_ ND13__DDR1_ NLD13 [5] C5 N7 NLD13
AD18 AE2 C404 VSSN NLD13
GND

[5] EA10 EA10__DDR1_ ND14__DDR1_ NLD14 [5] P6 M7 NLD14

AE25 V1 VSSN NLD14
[5] EA9 EA9__DDR1_ ND15__DDR1_ NLD15 [5] B1 N8 NLD15
AE23 NC NLD15
EA8__DDR1_ 0402 B2 A2
[5] EA8 [5] ECKE NC CKE1 DNU
AF25 1uF
[5] EA7 EA7__DDR1_ B10 NC NC P1
AE24 VIO18_PMU [2,3,4,5,6,7,9,15]
[5] EA6 EA6__DDR1_ [5] ECS1_B F3 NC CS1# NC G1
[5] EA5 AF24 EA5__DDR1_ NCEB__DDR1_ W5 NCEB [5] M3 EA13
A13 NC EA13 [5]
AE26 EA4__DDR1_ NWRB__DDR1_ Y5 NWRB [5] GND NLD0 N1
[5] EA4 NLD0
AC18 AB2
47K

[5] EA3 EA3__DDR1_ NREB__DDR1_ NREB [5] NLD1 N2 B4 NCLE [5]

AE19 AC3 NLD1 CLE
[5] EA2 EA2__DDR1_ NCLE__DDR1_ NCLE [5] NLD2 N3 C4 NALE [5]
AE20 AD3 NLD2 ALE
EA1__DDR1_ NALE__DDR1_ NALE [5] NLD3 M5 B6
0201

[5] EA1 NLD3 /CE NCEB [5]

[5] EA0 AF18 EA0__DDR1_ NRNB__DDR1_ AE3 NRNB [5] NLD4 P7 B3
NLD4 /RE NREB [5]
NLD5 M6 B7 NWRB [5]
R402

NLD5 /WE
NLD6 N6 NLD6 /WP C3 WATCHDOG [3,4]
AC22 ERESET NWPB__DDR1_ AB3 NLD7 M8 C6
NLD7 R/#B NRNB [5]
GND

P10 NC LOCK NC M4
MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
MT6572TA A10 A9
DNU DNU
MTK
H9DA4VH2GJAMCR-4EM

1.8V power
H9DA4VH2GJAMCR-4EM(hynix 4k page size),PIN M3 is A13
MT29C4G48MAAHBAAKS-5 WT(Micron 4k page size),PIN B2 is CKE1
MT29C4G48MAAHBAAKS-5 WT(Micron 4k page size),PIN F3 is CS1#
MT29C4G48MAAHBAAKS-5 WT(Micron 4k page size),PIN M3 is A13
MT29C4G48MAAHBAAKS-5 WT(Micron 4k page size),PIN P10 is LOCK,internal PD,block LOCK disable
A A

Title
Memory
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Wednesday, January 02, 2013 Sheet 5 of 15

5 4 3 2 1
 5 4 3 2 1

Reserve

Speaker
MICBIAS1 [4]
Earphone
class D audio PA nokia,L-R-MIC-GND
AW8155,B2为AGND，connect to B1 internel，Rin=28.5K,Cin=10nF,Fc=558.7Hz
default iphone,L-R-GND-MIC
MODE1,class D,8V/V,0.65w C569 C570
MODE2,class D,12V/V,0.85w

0201
MODE3,class D,12V/V,0.85w Close to BB close to connector R524 0402 0201
1uF 100nF
1K
MODE4,class AB,12V/V,C542,C543 should be <5nF
D GND D

0201
100nF
C563
R501 0R
[4,7,9] VBAT 0603 [4] AU_VIN1_N

100pF
2.2uF

C545
R525 C565

0201
1.5K
0402

0402
C566
0402

0603
C546

100nF

ear mic
0201
4.7uF

100nF
C564
[4] AU_VIN1_P HP_MIC [6]
GND

33pF

33pF
A2

U501
R523 1K
VDD

[4] ACCDET 0201

A3 B501 NC(BLM18PG181SN1D)

0402

0402
SPK+ [6]

C567

C568
OUT+
C540 0402 10nF A1
[4,6] AU_HPL IN+
C3 B502 NC(BLM18PG181SN1D)
OUT- SPK- [6]
C541 0402 10nF C1
IN- GND tie together and single via to GND plane
0402
0402

GND
GND of C565(4.7uF) and headset iphone
C2 B2 should tie together and single
AGND
PGND

[3] GPIO_SPK_EN CTRL VREF

via to GND plane
C543
C542

1nF
1nF
10K

AUDIOPA_YDA145
B3

B1
0201

C544
GND
R502

0402
GND 1uF
GND GND SPKL SPKR GND MIC

CTRL,VIH=1.3V-VDD,VIL=0-0.35V AW8145,B2=VREF,C544=1uF R534,R535,C505,C506

VIO18_PMU [2,3,4,5,7,9,15]
BB VOH?? AW8155,B2=AGND,connect to B1 internel，C544 can be 0R，NC，cap EINT_HP use 2.8V GPIO so PU to 2.8V
Reserve bead+C footprint for FM
performance tuning
C C
Close to BB close to connector
R530
0201 J501
470K
0402
Fc=120.6Hz B511 BLM15HD182SN
0R R506
4
0603 0603

[6] HP_MIC 0402

0R R505 GND
R535 0R C504 10uF 100R B510 BLM15HD182SN
[4] AU_HPR 0402 R533 5
0402
MP3R
R534 0R C503 10uF R532 100R B509 BLM15HD182SN
[4,6] AU_HPL 6
0402 0402
MP3L
GND B511 509 510 modify value 0426 R503 1.5K 2
0402
R531 47K B512 BLM15HD102SN1D 3
[3] EINT_HP 0201

internal audio PA output R507

0402
0R 1
MIC
R508 0R AJ006-34323A01
0402
470R

470R

BLM18PG181SN1D [8] FM_ANT 0402 C505 C506

B503
33pF

33pF

[4] AU_SPKP
class D/class AB SPK+ [6] 0R R527
B504 BLM18PG181SN1D C505 506 modify 390PF 0426 FV512
L501

[4] AU_SPKN SPK- [6] FV509 FV510 FV511

0402 0402
0402

0402

0201

0201

390PF 390PF
0402

0402

FV508
C501

C502

GND GND
R528

R529
C547

C548
1nF

1nF

ESD9X5.0ST5G
ESD9X5.0ST5G
0402

ESD9X5.0ST5G

ESD9X5.0ST5G
GND GND GND GND
[8] FM_RX_N_6572 0402 LESD9L5.0T5G，low cap
100nH

0R R526

GND
GND GND GND
Single via to GND plane
main mic GND GND

B B

Close to CPU Close to MIC

spk [4] MICBIAS0

C555
R519
0201

1K
0402
1uF

[6] SPK+
R504
0402
0R
PAD501

SPEAKER PAD
GND
rec
100pF

R520
0201

1.5K

B507 BLM15HD102SN1D REC501

0201
0402

100nF
C551

[4] AU_HSN
C552

PAD502
B505 BLM15HD102SN1D
R518 0R [4] AU_VIN0_P
[6] SPK- 0402 SPEAKER PAD C560
1
100pF
FV502
FV501

2
C554 MIC PAD
33pF

0201
33pF

2 MIC 100pF
0603
0402

B508 BLM15HD102SN1D
0201

C557

1 MIC501
100nF

[4] AU_HSP
C553

4.7uF
0402

B506 BLM15HD102SN1D
0402

C550
C549

[4] AU_VIN0_N
LESD9D5.0CT5G

LESD9D5.0CT5G

C561 C562 FV506 FV507

R521 FV503 FV504
0201

33pF

33pF

if you use digital MIC, 1.5K 0201 0201

GND
GND please change cap 33pF 33pF

(C552,C553) to 1.0uF
0402

0402

ESD9X5.0ST5G ESD9X5.0ST5G
C558

C559

ESD9X5.0ST5G

ESD9X5.0ST5G

A A
FV501、FV502 use bi-direction TVS GND
GND
R522 GND
0201

1K
GND

together then single via to main GND

GND

Title
Audio
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 6 of 15

5 4 3 2 1
 5 4 3 2 1

BPI0~4 and 10~11 are 2G+3G mode both

BPI5~9 and 12~14 are 3G mode only
(suggest BPI5~9 = 1.8V)
RF9810 control logic table
Enable VctC VctB VctA Antenna matching, depends on antenna design
LB_GMSK_TX H L H L
TRXB8 [7] GND
[4,6,7,9]
HB_GMSK_TX H L H H W2100_TRX [7]
VBAT
LB_EDGE_TX H L L L
GND C632
U605 GND C633
HB_EDGE_TX H L L H [3,7] VM1 C631 0201
SKY13373-460LF 100nF
3
2
1

0402
RX1 L H L L 0402 0402 0201 0402

ANTENNA PAD
13
J3

J1
GND

GND NC NC 82pF 2.2uF

NC [3,7] VM0 GND GND GND
0201

RX2 L L H L
22pF

J601 C620 C619

C618

ANT602
4 12
D BPI_4 [3] V1 GND R603 33pf C609 R601 0R
5 11 0402 D
RX3 L L H H BPI_5 [3] V2 RFC 0201 1 2 0R 0402 L605

10
6 10
modify by sunning 0326

4
3

1
VTCXO28-1 [7] VDD GND 4 3 L620
RX4 L L L H C610
C624 modify by sunning 0326
0201 NC W_PA_OUT_B1 [7]

VCC1
VCC2
NC

6 5

VMODE_0
VMODE_1
GND
GND

ANTENNA PAD
modify by sunning 0326
J2

C628

0201
18pF
ANT603
0201 R630 NC
C623 C625 C626 GND 0201 C629
7
8
9

2 9 C630
0201

NC NC NC GND 0201 RF_IN RF_OUT NC

GND
0201
modify by luming 0329 GND
NC
0201 0201 0201
GND GND GND W_PA_B1_IN [7] 0201
GND
R614

R638 0ohm

ANT604
8 U604 6 GND

ANTENNA PAD
GND 0201 CPL_IN CPL_OUT GND

0201
R692 NC R631
0201 NC
NC R638 modify 0424
modify by sunning 0326 5 VEN 27R R666 27R R668 [7]
ANT(GSM) [7]

GND
GND
0201 0201 PDET

NC
GND

0201

R667
B8_CPL_OUT[7]

R602

7
11
[3] W_PA_B1_EN

0201
GND
GND

33R
GND

[4,6,7,9]
VBAT

C604
[3,7] VM1 C605 0201 C603
100nF
R684 1K 0201 0402
82pF 2.2uF
VBAT 0201 BPI_3[3] [3,7] VM0 GND GND GND

R683 1K
C614

10
0201 BPI_0[3] modify by sunning 0326

4
3

1
22pF
+ C653 C651 C650
0201
modify by sunning 0326

VCC1
VCC2
C649

VMODE_0
VMODE_1
22uF 100nF 22pF C601 BPI0~4 and 10~11 are 2G+3G mode both BPI0~4 and 10~11 are 2G+3G mode both

C608
TANTCAP3216H1MM8 GND

0201
56pF
0603 0201 0201 22pF BPI5~9 and 12~14 are 3G mode only OR L601 1NH
GND
BPI5~9 and 12~14 are 3G mode only R607 W_PA_OUT_B8 [7]
GND GND GND 0201 2 9 0201
GND (suggest BPI5~9 = 1.8V) (suggest BPI5~9 = 1.8V) 0201 RF_IN RF_OUT
R682 1K
R670 10K 0201 BPI_1[3] 3GH1_B8_TX [7] C611
8 U603 6 C615

0201
VAPC1[3] 0201 R606 CPL_IN CPL_OUT NC
C612 NC NC
R679 1K NC 0201
22pF 0201 BPI_2[3] 0201
220pF 5 GND GND
0201 VEN

GND
GND
0201 GND 51R R632
C613 0201
0201

R671
22pF GND
24K

7
11
C670
0201 modify by sunning 0326 [3] W_PA_B8_EN
11

10

12

GND B8_CPL_OUT [7]

7

GND U601 GND

GND
GND
TX_EN
VRAMP

GPCTRL0

GPCTRL1

GPCTRL2
VBATT

C
2.2nH
0201

C606 22pF ANT 15 0201 L638

R672 18R R604 22pF 2 W2100_TRX [7]
C678
22pF

GGE_PA_HB_IN(TD)[7] 0402 0201 RFIN_HB

0201

L641
0201 C671 0ohm R678 C652
0201 C672 0201 ANT(GSM)[7]
300R
300R
C
RF9810 0201 0201 0201
C

NC NC NC
GND

0201
RX1 19
GND C679 C680
GND GND
R605 22pF 4 GND
0201 RFIN_LB GND

6
SAYFH897MHC0F0A

9
7
5
4
2
18 2G_LB(TD)[7]
RX2 NC
GND10
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

ANT

GND
GND
GND
GND
GND
G
0201

RX4

RX3

C607 56pF 9 1 [7] W_PA_OUT_B8

GND G RX
R673 18R 7 3
GGE_PA_LB_IN(TD)[7] 0402 G
VANCHIP
VC7810 5 TX
8
1
3
5
6
13
14
20
21
22
23

16

17

G 4 RX
0201 C675

ANT
0201 C673 G
2
300R
EDGE TXM U609

TX
RX
RX
300R

NC
U606

C617
2G_HB(TD) [7]

0201 9.1nH
3
1
8
TRXB8 [7]
GND W_PA_OUT_B1
[7] GND

L607

L608
GND

L653 0201 NC

GGE_PA_HB_IN(TD) [7]

GGE_PA_LB_IN(TD) [7]

1NH 0201

0201
modify by sunning 0326
L602 33NH

W_PA_B1_IN [7]

3GH1_B8_TX [7]
C616 C645 0201
39nH

GND
NC

GND

27NH
GND
12nH 0201 L621
LB_RX_P[7]
0201 C655 0201
NC NC
0201
0201

L604

L606
0201
modify by sunning 0326 NC
L633

L634
C685

10
0201
33pF

L616
L615

U602
0201

modify by sunning 0326

0201
2.2nH 0201 L618
GND

2G_LB(TD) [7]
1 9 12nH 0201 L622
LBIN LB OUT LB_RX_N [7]
0201

C666
1.8NH
0201

C665 1.8NH
2 8 GND
NC NC GND LBOUT
6.2nH NC 0201 L603
0201 0201
GND 0201 L623
3 7 0201
C686

GND GND HBOUT

0201
33pF

NC

NC

0201 2nH 470nF

0201

0201

3nH 0201 L617 4 6 HB_RX_P[7]

2G_HB(TD) [7] HBIN HB OUT
GND

C669
C667 C602 VRXLF_VRF18
7.5nH
NC

C668 VRXLF_VRF18[7]
1.5pF RFBLN2012090BM5T25
5

NC
0201
L624

L627

0201 GND PDET[7]

GND 6.2nH
0201 L626

HB_RX_N[7]

B modify by sunning 0326 B

D11
A10

A11

B11

B10
C10
D3
E3

C3

C2

A2

A3

B3

B4

A5

B5

A6

B6

B8

A8

A9

C7

C8

C9
J2

J7

J8
U600
VTXHF
GND
GND
GND
GND
GND

GND
GND

GND
GND
GND
GND
GND
DET
2GLB_TX
3GB1_RXN

3GB5_RXN

3GB2_RXN

3GB8_RXN

2GHB_TX

3GH1_TX

3GH2_TX

3GL5_TX
3GB1_RXP

3GB5_RXP

3GB2_RXP

3GB8_RXP

F3 GND GND D9
G3 GND GND E9
B H3 F9 B
GND GND
J3 GND GND G9
C4 FDD RX TXO H9
GND GND
Two Application Circuit Conditions, D4 GND GND J9

1.TSX Circuit : X600=TSX, R653=R656=NC, R654=100K+-1%, R655=R657=0ohm A1 B40_RXP DETGND D10

R608 OR
0402
VTCXO_PMU
0R R633
VTCXO28-1[7]
2.XTAL Circuit :X600=Mobile XTAL, R653=R656=0ohm, R654=R655=R657=NC B1 B40_RXN TMEAS C11
0201
R634 0R GND
VRF18_PMU 0201 VRXLF_VRF18[7] LB_RX_P C1 E10 VTCXO28-1
LB_RX_P[7] LB_RXP V28 VTCXO28-1[7]
TDD RX
modify by sunning 0326 LB_RX_N D1 G10 TX_BBIP
LB_RX_N[7] LB_RXN 3GTX_IP TX_BBIP[7]
VIO18_PMU 0402 VIO18 [7] C674
0R R635
HB_RX_P[7] HB_RX_P E1 G11 TX_BBIN 470nF
HB_RXP 3GTX_IN TX_BBIN[7]
TX(I/Q) 0201
HB_RX_N[7] HB_RX_N F1 HB_RXN 3GTX_QP F10 TX_BBQP GND
TX_BBQP[7]
VRXLF_VRF18[7]
GND VRXLF_VRF18 F2 VRXHF
MT6166 3GTX_QN F11 TX_BBQN TX_BBQN[7]
470nF
C660
0201

470nF
XTAL2 G2 L11

C676
RFVCO_MON TXVCO_MON

0201
VRXLF_VRF18[7]
IC,MT6166A,TD-SCDMA/HSDPA and GSM/GPRS/EDGE dual-mode Transceiver
4 3 XTAL1 J1 J11 VRXLF_VRF18 GND R610 close to 3G PA
GND GND HOT XTAL1 VTXLF
X600
H2 H10 TXBPI TXBPI[3]
XTAL2 XO TXBPI
22110264
1 2 VTCXO28-1 K1 J10 RCAL
HOT GND GND VTCXO28 Test pin RCAL

R600
X1E000021043400 DCXO_32K_EN G1 32K_EN TST2 K11

0201
SRCLKENA L1 L10
EN_BB TST1
Connect TSX/XTAL GND BSI
VTCXO28-1[7]
to GND_AUXADC first SRCLKENA K2 G8 BSI-A_DAT2

2K,1%
CLK_SEL BSI_DATA2 BSI-A_DAT2[3]
26M output
than connect to main GND C677
L2 H8 BSI-A_DAT1 GND
470nF XO3 BSI_DATA1 BSI-A_DAT1[3]
0201
0R R620
Route AUXADC_REF/AUXADC_TSX as differential trace with well GND shielding GND
E4
F4
GND GND B7
J6
RX_Q_P[3] 0201 RX_QP[7] GND GND
AVDD_VIO18

G4 RX(I/Q) D8
and route AUXADC_GND with 24mil trace width under
BSI_DATA0

GND GND
H4 E8
BSI_CLK
OUT32K

VXODIG

GND GND
XMODE

BSI_EN

0R R621
RX_QN
RX_QP
VRXLF

RX_IN

SRCLKENA[3,4,7]
RX_IP

RX_QN[7]
RX_Q_N[3] 0201
AUXADC_TSX/AUXADC_REF trace to provide return current path.
GND
GND
GND
GND
GND
GND

GND
GND

GND
GND
GND
GND
XO4

XO2

XO1

SRCLKENA[3,4,7]
0R R622 MTK
MT6166
RX_I_N[3] RX_IN[7]
J4
C5
D5
E5
F5
D7

K4

K3

L4

K5

L5

K6

K7

L7

L8

K8

K9

G6

H6

F8

E7
J5

C6
D6
E6
F6

0201
K10

NC R652
0R R623 VTCXO28-1[7] 0201
RX_I_P[3] 0201 RX_IP[7]
CLK4_AUDIO
R651 0R DCXO_ 32K_EN CLK4_AUDIO[4] BSI-A_DAT0
RX_QN
RX_QP

BSI-A_DAT0[3]
RX_IN
RX_IP

0201 SYSCLK_WCN
SYSCLK_WCN[8]
0R CLK1_BB
VRXLF_VRF18

R624 TX_BBQP[7] CLK1_BB[3] BSI-A_CK BSI-A_CK[3]

TX_Q_P[3] 0201 DCXO_32K
R650 NC DCXO_32K[4]
DCXO_ BSI-A_EN BSI-A_EN [3]
A 0R R625 Logic A
XMODE VXODIG VTCXO28-1[7] 0201
VIO18_VGPIO

TX_Q_N[3] 0201 TX_BBQN[7] MODE 32K_EN 0R

R649
VIO18_VGPIO[7] 0201 [7] [7] [7] [7]
RX_QP
RX_IN

RX_QN
RX_IP

0R R626 TX_BBIN[7] XMODE

TX_I_N [3] 0201
L630 0402 6.2nH
VIO18[7]
C682
TX_I_P[3]
0R
0201
R627 TX_BBIP[7] DCXO + 32K XO default 0(GND) 1(VIO18) 1(VIO18)
R648 NC 2.2uF
VRXLF_VRF18[7]
A VTCXO28-1[7] 0201 0402 A
GND
DCXO + 32K-Less 1(VTXCO28) 1(VTXCO28) 1(VTXCO28) R647 0R
VIO18_VGPIO[7] 0201 Reserved LC filter C684
VXODIG 470nF
0201
GND

Title
RF
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Wednesday, January 02, 2013 Sheet 7 of 15

5 4 3 2 1
 4 3 2 1
5 4 3 2 1

U101-C

B16 GPS_RXIN GND_WBG A14

A16 GPS_RXIP GND_WBG D18
GND_WBG B22
GND_WBG C16
B14 GPS_RXQN GND_WBG C17
B15 GPS_RXQP GND_WBG C18
GND_WBG C19
GND_WBG C20
[8] WB_TXIN A19 WB_TXIN GND_WBG C15
[8] WB_TXIP B19 WB_TXIP GND_WBG D16
D D17 D
GND_WBG
[8] WB_TXQN B18 WB_TXQN GND_WBG D19
[8] WB_TXQP A18 WB_TXQP GND_WBG D20
GND_WBG C21 GND
[8] WB_RXIN A21 WB_RXIN
[8] WB_RXIP A22 WB_RXIP
CONN_WB_CTRL0 E20 WB_CTRL0 [8]
[8] WB_RXQN B20 WB_RXQN CONN_WB_CTRL1 F20
WB_CTRL1 [8]
B21 D22
[8] WB_RXQP WB_RXQP CONN_WB_CTRL2 WB_CTRL2 [8]
CONN_WB_CTRL3 E22 WB_CTRL3 [8]
1 CONN_WB_CTRL4 C22 WB_CTRL4 [8]
CONN_WB_CTRL5 C23 WB_CTRL5 [8]

[8] AVDD18_WBG F18 AVDD18_WBG CONN_RSTB C14 WB_RSTB [8]

SH1
CONN_SEN E15 [8]
WB_SEN
CONN_SDATA E14 WB_SDATA [8]
G12
GND CONN_SCLK WB_SCLK [8]

CONN_F2W_DAT E13 FM_DATA [8]

CONN_F2W_CLK F12 FM_CLK [8]

CONN_XO_IN F14 CONN_XO_IN

MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
MT6572TA

[8] WB_CTRL3

[8] WB_CTRL2
WIFI/BT/GPS Single ANT Ref. [8] WB_CTRL4

C [8] WB_CTRL1 C
[8] WB_CTRL5 Close to MT6572
ANT701 ANT702
ANTENNA PAD GND [8] WB_CTRL0
ANTENNA PAD
AVDD18_WB [8]

5 6 [8] WB_RXIP B703

R706 0R 3 4 [8] AVDD18_WBG
0402 VCN_1V8_PMU
L702

2 1
L701

0R
J701 [8] WB_RXIN C701
C742
0201
NC

NC R703 GND 100nF

0402 0201
NC
0402
0402

30

29

28

27

26

25

24

23

22

21

C716 U701 GND

WB_CTRL5

WB_CTRL4

WB_CTRL3

WB_CTRL2

WB_CTRL1

WB_CTRL0

WB_RX_IP

WB_RX_IN
W_LNA_EXT

AVDD18_WBT

C740
0402
NC

NC
0402
NC L704 0402 6.2nH 50 Ohm 31 20 [8] WB_RXQP
GND WB_GPS_RF_IN WB_RX_QP
Based on your system level design , if WBG_ANT
B704
better WiFi TX performance is needed on 50 Ohm [8] AVDD18_WB VCN_1V8_PMU
32 19 [8] WB_RXQN 0R
your system, please refer to WiFi GPS_DPX_RFOUT WB_RX_QN
B705
performance enhance proposal [8] AVDD18_GPS VCN_1V8_PMU
0R
33 18 [8] WB_TXIP Star Conn
[8] AVDD33_WB AVDD33_WBT WB_TX_IP
C705 for WB/GPS/WBG 1V8
0201 C707
0201 0201 C708
4.7nF 100nF C706
34 17 [8] WB_TXIN 0402
NC WB_TX_IN 100pF
50 Ohm 1uF C706 modify 1UF 0426
GND

FM FM_RX_N_6572[6] 35 NC WB_TX_QP 16 [8] WB_TXQP GND

L711
MT6627N
0402
FM_ANT[6]
82nH
L712

AVDD28_FM [8] 36 AVDD28_FM WB_TX_QN 15 [8] WB_TXQN

B B
37 FM_LANT_N GPS_RX_IP 14
0402

FM_RX_N_6572

FM_LANT_P
38 13
NC

FM_LANT_P GPS_RX_IN

50 Ohm 39 12
GPS_RFIN GPS_RX_QP refer to FM desense performance
add ext GPS LNA by sunning 20130116 enhance proposal
[8] AVDD18_GPS 40 AVDD18_GPS GPS_RX_QN 11

B701
AVDD28_FSOURCE

41 DVSS AVDD28_FM [8] VCN_2V8_PMU [4,8]

MGB1005G601FBP,600Ω@100MHZ
F2W_DATA

F2W_CLK

C702
FM_DBG
HRST_B

SDATA

XO_IN

0402
CEXT
SCLK

SEN

1uF
MT6627 SMD QFN40
C702 modify 1UF 0426
1

10

Close to MT6627 GND

B702
[8] AVDD33_WB VCN_3V3_PMU
[8] WB_RSTB 0R

0R R701 0201 0402 C703 C709

0201 SYSCLK_WCN[7]
C704 2.2uF 0402
1NF 100pF 2.2uF C710
[8] FM_DATA 0201
0402
0201 C711
C712 modify 1NF 0426
C712 GND 220nF
100pF NC R702
0201
A [8] FM_CLK A
GND

[8] WB_SCLK
[4,8] VCN_2V8_PMU
4 VCC OUT 3

[8] WB_SDATA 1 2
NC GND
C720
X701
[8] WB_SEN 0402 X1G003851001500 Title
1uF TCXO,26MHz,±0.5PPM,-30/+85℃,10KΩ/10pF,2.5*2.0*0.8 For MT6620
Wireless Connectivity
Size Document Number Rev

GND
D MT6572 REF PHONE V1.0

Date: Wednesday, January 02, 2013 Sheet 8 of 15

4 3 2

5 4 3 2 1
 5 4 3 2 1

LCM LCD Backlight

DJN,driver IC=OTM8018B,ID ADC=0.99V,ID domain=2.8V
DJN,8 LED,Vf=23.6-26V,If=20mA
TRUST,driver IC=OTM8018B,ID ADC=1.8V,ID domain=1.8V TRUST,8 LED,Vf=23.2-27.2V,If=20mA
Tianma,driver IC=ILI9806C,ID ADC=?V,ID domain=?V

D D

Z802
6

1 3
[3] MIPI_TCN LCDC_MIPI_CLK- [9] J801 FCONH1MMPDMM3PIN25F_MIPILCD
DCR=0.265R,Isat=0.6A
L801
2 4 1 D801 1PS79SB30,115
[3] MIPI_TCP LCDC_MIPI_CLK+ [9] GND
2
[9] LCDC_MIPI_D0- D0- SWPA3012S100MTA01
3
NC
4
[9] LCDC_MIPI_D0+ D0+
5
LED+ [9] SYQ201ABC up to 30V
5

GND
ASBM1A2NP3KR,0R 6
D1-
7
NC C807

1
8 U801
D1+ LANSEL
9

LX
GND 0603
10 LANSEL=GND,one lane R820 0R 6
[9] LCDC_MIPI_CLK- CLK- [4,6,7] VBAT 0603 VIN 1uF/50V
11 5
NC LANSEL=IOVCC,two lane VOUT GND
12
[9] LCDC_MIPI_CLK+ CLK+

GND
13 4 3
GND IM2???? EN FB LED- [9]
14 C808 C809
IM2 NC 200mV
15

10R
2
BLU_PWM SYQ201ABC
Z803 16 0603
6

GND 0402
17 10uF 100nF VENH>1.5V
[3] LRSTB RST

0402
18 VENL<0.4V Ir=200mV/10R=20mA
1 [3] LPTE TE GND
3 19
GND LANSEL

R811
[3] MIPI_TDN0 LCDC_MIPI_D0- [9] 20
[2,3,4,5,6,7,9,15] VIO18_PMU IOVCC 1.8V
21
2 4 [2,4,15] VIO28_PMU VCI 2.8V LCM will make VDD28 power noise
[3] MIPI_TDP0 LCDC_MIPI_D0+ [9] 22 R808 0R
GND PWM>200ns when poweron [3] LCD_BK_EN_PMIC 0201 GND
23 1.8V,20K--1MHz
[9] LED+ LED+
24
[9] LED- LED-
GND

GND

25
ADC0 [3] LCD_ID ID
5

R810

0201
ASBM1A2NP3KR,0R
33pF

26

27

C806 100K
C801 C802 C803 C804
0402

C 0402 0402 0402 0402 0402 C

C805

1uF 100nF 1uF 100nF NC GND

GND GND GND GND

FV806

ESD9X5.0ST5G

GND

yeji,driver IC=MSG2133A
B
Touch LENS CON DJN,driver IC=FT6206
TRUST,driver IC=FT6206
B

VIO18_PMU [2,3,4,5,6,7,9,15]
TEST801

TEST802

TEST803

TEST804

TEST805

TEST806

TEST807
100K
4.7K

4.7K

NC
0201

0201
0201

0201

J802
R816

R817
R818

R819

1
GND
2
2.8V [4] CTP_2.8V_PMU VDD 2.8V
for ESD CTP power should can be off 3
1.8V [4] CTP_1.8V_PMU IOVDD 1.8V
4
[3] SDA_1 SDA
5
[3] SCL_1 SCL
6
[3] EINT_CTP INT
7
[3] GPIO_CTP_RSTB RESET
8
[3] TP_ID ID
9 11
NC
10 12
GND
C810 C811 C812 C813
FCONH1MM1PMM5PIN10F
0402 0201 0402 0201
1uF 100nF 1uF 100nF FV802 FV804
FV801 FV803 FV805

GND GND
A A
ESD9X5.0ST5G

ESD9X5.0ST5G

ESD9X5.0ST5G
ESD9X5.0ST5G

ESD9X5.0ST5G

GND GND GND GND GND

Title
LCD, Touch
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 9 of 15

5 4 3 2 1
 5 4 3 2 1

D CAMERA 2M,driver IC=HI253,MCLK=18-48MHz,PCLK=72MHz

D

TEST901

TEST902

TEST903

TEST904

TEST906

TEST907

TEST908

TEST909
TEST905

TEST910

TEST911

TEST912

TEST913

TEST915
TEST914

TEST916

TEST917

TEST918

TEST919
VCAMD_IO_PMU [4,10] GND

NC
100K

0201
0201

R903
J901

R902
DOVDD=1.8V 1
AVDD=2.8V [3] CMPDN
2
PWDN
[3] CMHSYNC HREF
2M cam,DVDD=NC or 1.8V 3
[3] CMVSYNC VSYNC
4
[3] CMRST RESET
3M cam,DVDD=1.2V [4] VCAMD_PMU
5
DVDD
6
1.8V
[4,10] VCAMD_IO_PMU
R907 0R 7
DOVDD
only 150mA from VCAMD 1.8V [4] VCAMA_PMU 0402
8
AVDD
AGND
2.8V 9
PCLK
please check your CAM module DVDD current C903 C904 C907 C908 C905 C906 [3] CMPCLK
10
DGND
11
[10] CAM_MCLK_C XCLK
external LDO is required for DVDD current > 150mA
2.2uF 0402

0402 0201 0201 0402 0201 12

DGND
1uF 100nF 100nF 1uF 100nF 13
[3,10] SDA_0 SIO_D
14
[3,10] SCL_0 SIO_C
15
C [3] CMDAT7 Y9 C
16
[3] CMDAT6 Y8
GND GND 17
GND [3] CMDAT5 Y7
18
[3] CMDAT4 Y6
19
[3] CMDAT3 Y5
20
[3] CMDAT2 Y4
21
[3] CMDAT1 Y3
22
[3] CMDAT0 Y2
23
NC
24
0R

NC
C910
0402

AW520CAMERA
0201
NC
R904

GND

GND

VCAMD_IO_PMU [4,10]
4.7K

4.7K
0201

0201

R901 0R
[3] CAM_MCLK_C [10]
R910

R911

B CMMCLK 0402 B

for CAM,Power by CAM_IO

C901 C902
[3,10] SCL_0
[3,10] SDA_0
0201 0201
NC NC
GND GND

A A

Title
Camera
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 10 of 15

5 4 3 2 1
 5 4 3 2 1

D D

5PIN Micro USB CONN

TP1001 TP1002 TP1003 TP1004
GND

ESD5Z7.0T1*

C1013 C1014

0402 0603
100nF 1uF/50V
FV1003
C J1004
SW set project 6.5V
C
40mil_50mil
1
[4] VBUS VBUS
2
[3] USB_DM DM

[3] USB_DP 3
DP 6
GND
7
R1004 1K 4 GND
[3] KCOL0 0201 ID 8
GND
9
5 GND
GND
FV1001 FV1002
FV1004

cap<3pF
LESD9L5.0T5G,low cap

GND
LESD9L5.0T5G

ESD9X5.0ST5G

B B
GND

A A

Title
USB
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 11 of 15

5 4 3 2 1
 5 4 3 2 1

D D

TF CARD

VMCH_PMU [4]
47K

47K

47K

47K
47K

C1101 C1102
0201

0201

0201

0201
0201

2.2uF 0402
0201
R1102

R1103

R1104

R1105

100nF
R1101

C C

GND
J1101

1
[3] MC1DAT2 DATA2
2
[3] MC1DAT3 CD/DATA3
3
[3] MC1CMD CMD
4
VDD
6个个个个个个 [3] MC1CK
5
6
CLK GND
9
10
VSS2 GND
7 11
[3] MC1DAT0 DATA0 GND
8 12
[3] MC1DAT1 DATA1 GND

CAH11-08163-SFOO
C1103 C1104 C1105 C1106 C1107 C1108

0201 0201 0201 0201 0201 0201

NC NC NC NC NC NC

B GND GND GND GND

GND GND B

A A

Title
Memory CARD
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Thursday, December 27, 2012 Sheet 12 of 15

5 4 3 2 1
 5 4 3 2 1

SIM CARD cap<45pF

D
SIM1 D

R1201 NC
0201

GND
8

J1201
6 1
[4] VSIM1_PMU VCC GND
5 2
[4] SRST RST VPP
4 3
[4] SCLK CLK I/O SIO [4]
KWS6156N10R
9

10

C1203 C1204
C1207 C1208
C C1201 C1202 C1205 C1206 C
0201 0201 0201 0201
0402 0201 22pF NC 0201 0201 22pF NC
1uF 100nF 22pF NC
GND
GND GND
GND GND

SIM2 B

R1202 NC
0201

GND
8

J1202
6 1
[4] VSIM2_PMU VCC GND
5 2
[4] SRST2 RST VPP
4 3
[4] SCLK2 CLK I/O SIO2 [4]
KWS6156N10R
9

10

C1209 C1210 C1211 C1212 C1213 C1214 C1215 C1216

0402 0201 0201 0201 0201 0201 0201 0201

A 1uF 100nF 22pF NC 22pF NC 22pF NC A

GND GND GND GND GND Title

SIM
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Thursday, December 27, 2012 Sheet 13 of 15

5 4 3 2 1
 5 4 3 2 1

TP1
Power Key
D D
DO NOT put pull-up
resistor on PWRKEY
J1301 J1303
R1303 1K
0201 KCOL1 [3]

2 1 R1301 1K 2 1
GND S1 0201 PWRKEY [4] GND S1
4 4
GND GND FV1303
5 3 5 3
GND S2 GND S2
FV1301

GND TC-1122F TC-1122F

ESD9X5.0ST5G
ESD9X5.0ST5G
GND

GND J1302
GND

C C
2 1 R1302 1K KCOL2 [3]
GND S1 0201
4
GND
5 3
GND S2

FV1302

TC-1122F

Volume Up

ESD9X5.0ST5G
Volume Down
GND
GND

B B

A A

Title
KP
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Thursday, December 27, 2012 Sheet 14 of 15

5 4 3 2 1
 5 4 3 2 1

G-Sensor
reserved
power supply=1mA,VIH>0.8*VDD=2.24V,VIL<0.2*VDD=0.56V
D motion Sensor D

LED 3-5mA,Vf=1.1-1.3
1.8V VIO18_PMU [2,3,4,5,6,7,9,15] VGSENSOR_PMU [4,15]
NC
0R

R0201
R0201

1.8V
1.8V,power can be off
1.8V
R1405
R1406

2.7K

2.7K
R0201

R0201

VIO18_PMU VIO28_PMU

C C
R1402

R1401

[3,15] SCL_2

12

11
U1402
1 6 GND 1 SCL 10

NC
INT GND NC TEST
2 9 GND
U1401 [3,15] SDA_2 SDA GND
2 5 R1404 0R 3 8 GND
DVDD NC
INTN

NC SDA R0201 SDA_2 [3,15] 1.8V 4 VPP 7

NC AVDD
3 4 R1403 0R C1404
2.8V [4,15] VGSENSOR_PMU VDD SCL R0201 SCL_2 [3,15] 1.8V BMA222E
5

0201 C1403
MXC6225XU 100nF GND
GND GND 0201
100nF
GND
C1402 C1401

B B
0201 0402
100nF 1uF
EINT_GY

GND

Default
[3]

1.8V version
MMC6225XC(2.8V version)&BB I2C cannot be 2.8V
IC VDD:2.5-5.5V
IC VDD:2.5-5.5V
VGSENSOR_PMU=2.8V
VGSENSOR_PMU=2.5V
VIO18_PMU=1.8V
R1401,R1402=10k R1401,R1402=2.7k
R1403,R1404=3.3k R1403,R1404=0R
R1405=0R,R1406=NC R1405=NC,R1406=0R

A A

Title
MEMS Sensors
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Thursday, December 27, 2012 Sheet 15 of 15

5 4 3 2 1