5 4 3 2 1

Celullar ANT
Project : MT6572
REF_SCH TOP LEVEL BPI, APC FEM
EMI x32
EMI
TX RX

Memory
D NFI RF IQ D
MCP
NFI
BSI ctrl
RX
MT6166 balun

MSDC 4-bit MSDC1

26M_BB
micro SD 26M
26M_AUD DCXO ctrl
+ hot-plug

26M_CN
26M_CN
ABB

TCXO
Connectivity ANT
SPI CONN IQ
CMMB MT6572
EINT
CONN ctrl
MT6627
C C

32K_BB RTC 32K

Camera IF
Camera CAM
Module (MIPI / Parallel)

Camera IF MT6323 Headset

2nd Camera (HPL, HPR, AU_VIN1)
Module
I2C
i2C_0 Class D/AB

LCD IF
LCD LCD AUD I/F Audio Receiver
module (MIPI / Parallel) Speech

I2C
i2C_1 AU_VIN0
CTP EINT
B controller B

I2C

Motion EINT
POWER
Sensor
I2C
ALS + PXS
EINT
SIM2
SPI SIM2
I2C Power
Management SIM1
Magnetic EINT SIM1
sensor
VIB
I2C
BC1.1
Gyro EINT Charger
sensor

Charger
Battery
Keypad

BJT
A JTAG A

USB 2.0 micro USB

Debug USB
UART
port

Title
MT6572 Block diagram
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 1 of 19

5 4 3 2 1
 5 4 3 2 1

cap Close to BB IC

2
C108
U101-H

1
cap Close to BB IC
VIO18_PMU VIO18_PMU T25 DVDD18_MIPIRX AVDD28_DAC F1 VTCXO_PMU VTCXO_PMU
U25 DVSS18_MIPIRX
AVDD18_AP E5

R25 DVDD18_MIPITX DVDD18_PLLGP U9 VIO18_PMU VIO18_PMU

P25 DVSS18_MIPITX
D D

AVDD18_MD D3 VIO18_PMU
VIO18_PMU VIO18_PMU H23 A1

1
AVDD18_USB AVSS18_MD
VUSB_PMU VUSB_PMU G24 AVDD33_USB AVSS18_MD A4
G23 C3 C128

1
1
AVSS33_USB AVSS18_MD C / 100 / nF / 0402

2
AVSS18_MD E2
C113

1
C112

2
2
C / 1000 / nF / 0402

2
C104 BG

1
1
C107 C101 REFP F6 REFP

1
C109

2
2
C / 1000 / nF / 0402 G6 REFN

2
MT6572/TFBGA428/P0.4/B0.25/10.6X10.6

VIO_EMI

U101-B

dedicate VSS ball, must return to cap then to main GND: W9

1.8V IO for DDR1
VCC VCCIO_EMI
W12 1.2V IO for DDR2

1
1
1. REFN(G6) => C109 Memory VCCIO_EMI
VCCIO_EMI W14
2. DVSS18_MIPIRX(U25) => C107 AC21 W16 C405 C406
GND VCCIO_EMI

2
2
AD11 GND VCCIO_EMI W19
3. DVSS18_MIPITX(P25) => C101 AF13 If double-sided SMT, put C405 & C406 below BB.
GND
AB11 GND
C AC8 If single-sided SMT, put C405 & C406 around memory. C
GND DVDD
AB5 GND
AB14 Peripheral
GND
W26 GND DVDD18_MC0 AA1 VIO18_PMU VIO18_PMU
T15 GND DVDD18_CAM K20 VIO18_PMU
W23 GND DVDD18_VIO_1 L3 VIO18_PMU
T14 GND DVDD18_VIO_2 J19 VIO18_PMU
AF26 GND DVDD18_VIO_3 H13 VIO18_PMU
G3 GND DVDD18_LCD AB24 DVDD18_LCD R119 1 2
K21 GND
L11 R / 0 / ohm / 0402
GND
L12
1

GND
L14 GND DVDD3_MC1 K24 VMC_PMU VMC_PMU C126
L15 GND C / 1000 / nF / 0402
2

L16 GND DVDD3_LCD W24 DVDD18_LCD

M5
1

GND
M11 GND DVDD28_BPI C10 VIO28_PMU VIO28_PMU C121

1
M12 GND
2

M13 GND C117

M14 C / 1000 / nF / 0402

2
GND VCC
M15 GND
M16 CPU P6
GND VCCK_CPU
N10 GND VCCK_CPU T7
N8 GND VCCK_CPU P7
N9 GND VCCK_CPU P8 Close to BB IC, recommand < 150mil
N11 GND VCCK_CPU P9
N12 GND VCCK_CPU R6
N13 GND VCCK_CPU R7
N14 GND VCCK_CPU R8
N15 GND VCCK_CPU R9
N16 GND VCCK_CPU T6 Based on your system level
P10 GND VCCK_CPU U6 design , if better FM performance
N22 GND VCCK_CPU T9
P11 GND VCCK_CPU T8 is needed on your system ,
P12 GND VCCK_CPU U7
P13 please refer to FM desense
GND
P14 GND performance enhance proposal
P15 GND
B 120mil VPROC_FB B
P16 GND VCC VPROC_FB [3]
R10 GND
R11 Core J9
GND VCCK
R12 GND VCCK J15
R13 GND VCCK M9
R14 GND VCCK K6
R15 GND VCCK K7
R16 GND VCCK K8
T10 K9
C / 1000 / nF / 0402
C / 1000 / nF / 0402
C / 1000 / nF / 0402
C / 1000 / nF / 0402

GND VCCK
C / 4700 / nF / 0603

T11 GND VCCK K11

T12 GND VCCK K14
T13 GND VCCK K15
AF1 M10
C111

VSS VCCK
1 C114
1 C115
1 C118
1 C116
1 C135
1 C120
1 C134
1 C119
1 C136
1 C137
1
1 C106
1 C102
1 C103

VCCK K16
U10 VSS VCCK K17
U11 U17
2
2
2
2
2
2
2
2
2
2
2
2
2
2

VSS VCCK
V13 VSS VCCK M17
W11 VSS VCCK L7 Vproc remote sense :
Y21 VSS VCCK L8
L9 differential 4mil with good shielding, from the BB to PMIC
VCCK
VCCK L17 GND_VPROC_FB [3]
VCCK M6
M7 4mil - defferential - GND shielding
VCCK VPROC_FB [3]
VCCK M8
VCCK J17
VCCK J16
VCCK R17
VCCK T16
VCCK L6
VCCK K12
VCCK T17
VCCK J10
VCCK J11
VCCK U12
VCCK U13
VCCK U14
VCCK U15
A VCCK U16 A
VCCK J8
VCCK J14

A26 DUMMY

MT6572/TFBGA428/P0.4/B0.25/10.6X10.6
Title
BB- Power
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Wednesday, January 02, 2013 Sheet 2 of 19

5 4 3 2 1
 5 4 3 2 1

U101-A

[6] RX_I_P D2 DL_I_P BPI_BUS0 B12 BPI_0 [6]

[6] RX_I_N C2 DL_I_N BPI_BUS1 B11 BPI_1 [6]
[6] RX_Q_P B1 C12 BPI_2 [6] U101-D
DL_Q_P BPI_BUS2
[6] RX_Q_N C1 DL_Q_N BPI_BUS3 A11 BPI_3 [6]
[3] AUD_MISO J1 AUD_DAT_MISO
BPI_BUS4 D11
[3] AUD_CLK K5 AUD_CLK_MOSI
[6] TX_I_P A2 UL_I_P BPI_BUS5 C11 EINT_HP [5]
[3] AUD_MOSI K1 AUD_DAT_MOSI reserve for JTAG debug
[6] TX_I_N B2 UL_I_N BPI_BUS6 A13
[6] TX_Q_P B4 UL_Q_P
D [3] PMIC_SPI_MOSI L2 PMIC_SPI_MOSI D
[6] TX_Q_N B3 UL_Q_N BPI_BUS7 A10
[3] PMIC_SPI_MISO L5 PMIC_SPI_MISO
BPI_BUS8 B10
[3] PMIC_SPI_SCK L4 PMIC_SPI_SCK
BPI_BUS9 D10
[3,4] PMIC_SPI_CS K2 PMIC_SPI_CSN
BPI_BUS10 E9 VIO18_PMU
BPI_BUS11 E8
[3] WATCHDOG G2 WATCHDOG
BPI_BUS12 B9 EINT_MAG [80] [3] SIM1_SCLK
[3,6] SRCLKENA H4 SRCLKENA
A8 VM0 BPI_BUS13 B8 EINT_ALPXS [21]
[3] EINT_PMIC J2 EINTX
A7 VM1 BPI_BUS14 E7 EINT_ACC [21]
BPI_BUS15 D7
[3] SIM1_SCLK H5 SIM1_SCLK
[6] TXBPI D5 TXBPI BSI_DATA2 D6 BSI-A_DAT2 [6] Normal : NC
[3] SIM1_SIO M3 SIM1_SIO
BSI_DATA1 C7 BSI-A_DAT1 [6]
[6] VAPC1 F2 F9 BSI-A_DAT0 [6]
JTAG : 20K
APC BSI_DATA0
BSI_EN F11 BSI-A_EN [6]
[3] SIM2_SCLK J5 SIM2_SCLK
F3 VBIAS BSI_CLK G11 BSI-A_CK [6]
[3] SIM2_SIO M1 SIM2_SIO

Reserve R footprint
for JTAG debugging

MT6572/TFBGA428/P0.4/B0.25/10.6X10.6 MT6572/TFBGA428/P0.4/B0.25/10.6X10.6

U101-E

C C
[6] CLK1_BB E1 CLK26M PWM_A D12 GPIO_FLASH_EN [80]
SYSTEM PWM E12
PWM_B EINT_CTP [12]
[3] CLK32K_BB H2 CLK32K_IN
LCD
[3] RESETB M2 SYSRSTB LPD17 N1
Parallel N2
LPD16
G4 TESTMODE LPD15 N3
LPD14 P2
AC24 FSOURCE LPD13 N4 EINT_CMMB [80]
LPD12 R2
Based on your system level design , if better LPD11 N5
[3] CHD_DP J26 CHD_DP LPD10 R1 MC1_INS [18]
desense performance is needed on your [3] CHD_DM J25 BC 1.1 P5
CHD_DM LPD9
LPD8 T1
system , please refer to desense R5
LPD7
performance enhance proposal [14] USB_DM 90-ohm differential G26 USB_DM LPD6 T2
U101-G G25 USB 2.0 T5
[14] USB_DP USB_DP LPD5
USB_VRT H25 USB_VRT LPD4 U2
MIPI_2nd_CAM 1 2 T3
[13] GPIO_CMPDN2 L25 R203 LPD3
CMPDN2 Parallel 8-bit U5
[13] GPIO_CMRST2 K25 i2C LPD2
CMRST2 [13] SCL_0 C25 T4
[13] GPIO_CMPDN H22 SCL_0 LPD1
CMPDN [13] SDA_0 C26 V2
[13] GPIO_CMRST J22 close to BB SDA_0 LPD0
CMRST [12,21] SCL_1 B24 SCL_1
[12,21] SDA_1 B23 SDA_1
CMMCLK Y22 CMMCLK [13]
[13] MIPI_RDN0 R24 RDN0
R23 MIPI_CAM Y23
[13] MIPI_RDP0 RDP0 CMPCLK CMPCLK [13] AD25
R22 LPCE0B EINT_GY [80]
[13] MIPI_RDN1 RDN1 [80] SPI_MISO F24 AB26 LPTE [12]
100-ohm differential[13] MIPI_RDP1 R21 V25 CMVSYNC [13] SPI_MISO SPI LPTE
RDP1 RCN_A [80] SPI_MOSI F25 AC26 GPIO_LRSTB [12]
[13] MIPI_RCN R26 W25 CMHSYNC [13] SPI_MOSI LRSTB
RCN RCP_A [80] SPI_SCK F23 AA22 GPIO_FLASH_SEL [80]
[13] MIPI_RCP T26 V24 CMDAT7 [13] SPI_SCK LPRDB
RCP RDN1_A [80] SPI_CSB E23 AB23 GPIO_TV_RST [80]
V23 CMDAT6 [13] SPI_CS LPA0
RDP1_A AC25 GPIO_CTP_RSTB [12]
[12] MIPI_TDN0 P19 U22 CMDAT5 [13] LPWRB
TDN0 MIPI_LCD RDN0_A MT6572 support JTAG from below :
[12] MIPI_TDP0 P20 TDP0 RDP0_A U21 CMDAT4 [13]
100-ohm differential [12] MIPI_TDN1 N25 TDN1 [18] MC1CMD K23 KROW0 B25 KROW0 [20] 1. KP (recommand)
[12] MIPI_TDP1 N26 TDP1 CMDAT3 Y26 CMDAT3 [13] MC1_CMD T-flash KP
[18] MC1CK L21 MC1_CK KROW1 A24 KROW1 [20]
P23 TDN2 CMDAT2 Y25 CMDAT2 [13] [18] MC1DAT0 K22 MC1_DAT0 KROW2 B26 2. MC1 JTMS 1 TP205
P24 TDP2 CMDAT1 AA25 CMDAT1 [13]
B [18] MC1DAT1 M22 MC1_DAT1 KCOL0 C24 KCOL0 [20] B
[12] MIPI_TCN N20 TCN CMDAT0 AB25 CMDAT0 [13] [18] MC1DAT2 M25 MC1_DAT2 KCOL1 D24 3. CAM
[12] MIPI_TCP N19 TCP [18] MC1DAT3 L26 MC1_DAT3 KCOL2 A25 JTCK 1 TP206
for JTAG pin out from MC1/CAM, refer
B7 AUX_IN0 UTXD1 E25 to HW design 1
UTXD1 notice TP201
MIPI_VRT P26 VRT ADC UART
1 2 B6 AUX_IN1 URXD1 D25 URXD1 1 TP202
R202 C5 E26
AUX_IN2_XP UTXD2
B5 AUX_IN3_YP URXD2 F26
C4 AUX_IN4_XM
close to BB A5 AUX_IN5_YM
MT6572/TFBGA428/P0.4/B0.25/10.6X10.6

MT6572/TFBGA428/P0.4/B0.25/10.6X10.6

VCAMD_IO_PMU
1
1

R204 R205
2.2K 2.2K
2
2

[13] SCL_0 Power by CAM_IO

[13] SDA_0

A A
VIO18_PMU
1
1

R206 R207
2.2K 2.2K
2
2

[12,21] SCL_1
[12,21] SDA_1 Power by CTP, MEMS sensor
Title
BB - peripheral
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Wednesday, January 02, 2013 Sheet 3 of 19

5 4 3 2 1
 5 4 3 2 1

Before you select BJT , please take power dissipation into consideration.
Refer to MT6323 design notice

Charger
VBUS

D D
1. Close to Battery Connector.
(Rsense (R328) <10mm) R329
2. Main path should be 40mil. VCDT
1 2
(VBUS -> U303's E, -> U303's C -> R328 -> VBAT) U301
VCDT rating: 1.268V
R324
3. Star connection from R328 to BAT Connector 39K MT6323/VFBGA145/P0.4/B0.25/5.8X5.8

1
cap rating depends on C329 1 2

2
Phone OVP spec. SPK_P K1 AU_SPKP [5]
SPK_N L1 AU_SPKN [5]
40mils BATSNS BATSNS
P1

1
C313 VBAT_SPK

R331 L2 GND_SPK AU_HSP H1 AU_HSP [5]

2
AU_HSN G1 AU_HSN [5]
CHR_LDO
1 2 H4
AU_HPL AU_HPL [5]
MICBIAS0 F2 J4 AU_HPR [5]

6
5
4
AU_MICBIAS0 AU_HPR
MICBIAS1 G2

1
C C E U303 C312 AU_MICBIAS1
STT818B
40mils

2
[5] AU_VIN0_P E4 AU_VIN0_P AUDIO ISINK0 E9 ISINK0 [12]
[5] AU_VIN0_N F4 DRIVER C9 ISINK1 [12]
C B AU_VIN0_N ISINK1
C E10 ISINK2 [12]

1
ISINK2

1
2
3
[5] AU_VIN1_P G3 AU_VIN1_P ISINK3 C10 ISINK3 [12]
U305 [5] AU_VIN1_N G4 AU_VIN1_N
3 2 SSM3K35MFV VDRV
VA_PMU VA_PMU D2 AU_VIN2_P
40mils D1

1
C314 AU_VIN2_N
C / 1000 / nF / 0402 J2
40mils 4mil AVDD28_ABB Please use inductor recommand by MTK

2
D3

1
AVDD28_AUXADC
ISENSE H2 GND_ABB Refer to MT6323 design notice
R328
Rsense Differential BATSNS [6]
R0805

2
[5] ACCDET E2 ACCDET
4mil BUCK OUTPUT L301
VPROC C14
40mils
[6] CLK4_AUDIO E1 CLK26M VPROC D14 VPROC_SW VPROC_PMU
E14 L/IND/SMD/2520
1 2 VPROC_PMU [1]
VPROC
AUXADC_REF AUXADC_REF [6]

B12 VPROC_FB [1]

2
CHARGER VPROC_FB
ISENSE/BSTSNS 4mil GND_VPROC_FB C12 GND_VPROC_FB [1]
R334 [6] BATSNS BATSNS P13
BATTERY differential to Rsense BATSNS
ISENSE ISENSE P12 ISENSE VPA A14
BAT_ON BAT_ON K3 BATON VPA B14

1
VCDT VCDT A12 VCDT
C
CONNECTOR
CON301 40mils 40mils C
VDRV VDRV M13 VDRV VPA_FB D12
VBAT+ 1 BATSNS
BATSNS[6]
6 NC NTC 2 BAT_ON CHR_LDO CHR_LDO N13 CHRLDO
1R317 2 L303

1
GND- 3 VSYS H14 VSYS_SW VSYS_PMU
C316 L/IND/SMD/2520
1 2

2
C / 1000 / nF / 0402 R316
CONTROL SIGNAL

2
7 NC NC 4 R335
[20] PWRKEY M2 PWRKEY
5 R334,R335 must to be close to [2] WATCHDOG 1 2 A1
NC SYSRSTB
[2] RESETB K4

1
PMIC AUXADC_REF pin RESETB ALDO OUTPUT
A9 FSOURCE VA M3 VA_PMU
[2] EINT_PMIC A7 INT
BAT/SMD/KBC23S3D4XR/KEIRAKU Close to PMIC N12 N3 VCN_2V8_PMU
EXT_PMIC_EN VCN28
VTCXO L4 VTCXO_PMU VEMC_3V3_PMU
N2 PMU_TESTMODE
VCAMA P3 VCAMA_PMU
[2] AUD_MOSI E7 AUD_MOSI VCN33 M6 VCN_3V3_PMU
[2] AUD_CLK E8 C3 VRTC
1

AUD_CLK AVDD33_RTC
[2] AUD_MISO B6 AUD_MISO C355 C / 1000 / nF / 0402 C354
C / 100 / nF / 0402
2

[2,6] SRCLKENA A2 SRCLKEN DLDO OUTPUT 1 2

i
t
t
r
s
TP301 1 FCHR_ENB FCHR_ENB M1 FCHR_ENB
VM J13 VM_PMU

fi
at
et
yr
s
07
oo
K0
,K
R,
3R
33
53
=5
9=
03
K9
0
K
Based on your system level design , if [2] PMIC_SPI_SCK D9 SPI_CLK VRF18 H11 VRF18_PMU
[2,4] PMIC_SPI_CS B7 L12 VIO18_PMU

fR
bbf e
ae
r
et
yo
NNT M
TT6
CC3
ii2
3
14H
kkW
hhd
mme s
,,i
RRg
33n
33n
44o
==t i
31c
99e
SPI_CSN VIO18
better ESD performance is needed on [2] PMIC_SPI_MOSI D8 SPI_MOSI VIO28 M4 VIO28_PMU
[2] PMIC_SPI_MISO B8 SPI_MISO VCN18 J12 VCN_1V8_PMU
your system, please refer to ESD BATSNS
VCAMD K14 VCAMD_PMU
performance enhance proposal VCAM_IO L13 VCAMD_IO_PMU
F13 VBAT INPUT
VBAT_VPROC
80mil 40mil BATSNS G14 VBAT_VPROC
G13 VBAT_VPROC VEMC_3V3 P7 VEMC_3V3_PMU
4mil (VPA no use) BATSNS A13 VBAT_VPA VMC L6 VMC_PMU
VMCH P4 VMCH_PMU
15mil BATSNS H13 VBAT_VSYS VUSB N6 VUSB_PMU
P8 VBAT_LDOS3 VSIM1 P9 VSIM1_PMU
20mil BATSNS P6 N9 VSIM2_PMU

1
Add Zenar Diode VBAT_LDOS3 VSIM2
20mil BATSNS P5 VBAT_LDOS2 VGP1 L8 VGP1_PMU
path C310 20mil BATSNS P2

K
Place on the500mW VBAT_LDOS1

2
VIBR M7 VIBR_PMU
from VBAT to IC D302 VSYS_PMU 20mil J14 N8
AVDD22_BUCK VGP2
(Battery connector M14 AVDD22_BUCK VGP3 L14 VGP3_PMU
SOD323/SMD/MM3Z2V4T1

A
VCAM_AF N7 VCAM_AF_PMU
or test point or IO
DVDD18_DIG_PMIC A8 DVDD18_DIG
connector) VF : 4.85V~5.36V
VIO18_PMU VIO18_PMU A5 DVDD18_IO

B Between IC and IO port [6] AUXADC_REF AUXADC_REF C2 AUXADC B

AUXADC_VREF18
[6] AUXADC_TSX AUXADC_TSX B1 AUXADC_AUXIN_GPS VREF P14 VREF
[6] GND_AUXADC GND_AUXADC B2 AVSS28_AUXADC
1

C320

1
dedicate VSS ball, must return to cap then to main GND:
C322
1. GND_VREF(N14) => C320
2

C / 100 / nF / 0402 BC 1.1

2
[2] CHD_DM A10 CHG_DM GND_VREF N14
Based on your system level design , if [2] CHD_DP A11 CHG_DP
C322 must to be close
better EOS performance is needed on your
Refer to MT6323 design to PMIC AUXADC_TSX pin D5 CLK32K_BB [2]

2
system, please refer to EOS performance SIM LVS RTC RTC_32K1V8
RTC_32K2V8 C4
RTC 32K : X301+C324+C319=> mount, R333=> NC

C / 1000 / nF / 0402
C / 1000 / nF / 0402
enhance proposal SH301 [2] SIM1_SCLK B5 SIM1_AP_SCLK XIN A3 32K_IN
notice for Zener selection X301

1
[2] SIM1_SIO M11 SIMLS1_AP_SIO XOUT A4 32K_OUT 32K-less: X301+C324=> remove, C319+R333=> 0R RTC
E6 SIM1_AP_SRST 4 1
SSP-T7-F
3
2

[2] SIM2_SCLK C5 SIM2_AP_SCLK GND_ISINK B10

[2] SIM2_SIO L11 G11

1 C301
1 C303
1 C304
1 C306
1 C309
1 C307
1 C308
1
1

SIMLS2_AP_SIO GND_VSYS SSP-T7

D6 SIM2_AP_SRST GND_VPA E13
E11 C324
Connect TSX/XTAL GND GND_VPROC C319

2
2
2
2
2
2
2
2
2

[19] SCLK M9 SIMLS1_SCLK GND_VPROC F11

to AUXADC_GND first [19] SIO N11 F10
SIMLS1_SIO GND_VPROC
than connect to main GND [19] SRST M10 SIMLS1_SRST
GND_LDO K6
[19] SCLK2 K9 SIMLS2_SCLK GND_LDO K8
[19] SIO2 K11 SIMLS2_SIO
[19] SRST2 K10 SIMLS2_SRST GND_LDO F5 Close to chip
GND_LDO F6 R333
GND_LDO F7 2 1 DCXO_32K [6]
GND_LDO F8
refer to system analog LDO GND_LDO F9
GND_LDO G5
performance improve proposal G6
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO

GND_LDO VIBR_PMU
J9
J8
J7
J6
H9
H8
H7
H6
H5
G9
G8
G7

J10
H10

Refer to MT6323 design notice

Vibra
for Buck GND layout rule
2

GND_SIGNAL
+

VRTC C311
C / 1000 / nF / 0402
VIB301
2
-

Vibrator
1

A R312 A
1

Refer to GPS co-clock layout rule

1

C325
2

Title
==> for longer RTC time sustain after battery remove, PMIC
please refer to RTC design notice Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 4 of 19

5 4 3 2 1

NC-4MIL_
 5 4 3 2 1

R615
VBAT BPI_3 [2]
C604 1 2

1
R606

1
1
1

1
BPI_0 [2]

C614
1 2

C625
1

C615

C637
2
2
2

2
C611
2
R602

C / 100 / nF / 0402
R612 BPI_1 [2]
[2] WG_GGE_PA_VRAMP 1 2

1
1 2 R608
Antenna matching, depends on antenna design
BPI_2 [2]

1
C612
1 2

1
1
R613 C608

C613

2
2

2
7
11
8
9
10
12
U601

C618
C606
R603 R / 0 / ohm / 0402 15 C623

VBATT
TX_EN
ANT CON600

VRAMP
GGE_PA_HB_IN 2

1
RFIN_HB

GPCTRL0
GPCTRL1
GPCTRL2
1 2 1 2 R614 R / 0 / ohm / 0402 C609 L605

1
R607 TXM_ANT1 TXM_ANT2 2 1 ASM_ANT2 ANT602
R605 1 2 1 2
D 3 4 D

2
RF9810

2
1
R / 0 / ohm / 0402
C624

2
5
6
RX1 19

C610
2
ANT603
4 RFIN_LB
RF9810 control logic table 18 2G_LB
C607 R609 RX2
Enable VctC VctB VctA R / 0 / ohm / 0402

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
RX4
RX3
ANT604
GGE_PA_LB_IN

1
LB_GMSK_TX H L H L 1 2 1 2

1
3
5
6
13
14
20
21
22
23
16
17

1
HB_GMSK_TX H L H H R610 R611

LB_EDGE_TX H L L L

2
EDGE TXM
2G_HB

2
HB_EDGE_TX H L L H
RX1 L H L L
RX2 L L H L
RX3 L L H H
RX4 L L L H

C C
VBAT
VBAT [3]

BPI0~4 and 10~11 are 2G+3G mode both
BPI5~9 and 12~14 are 3G mode only
[2] BPI_0
(suggest BPI5~9 = 1.8V) BPI_0 [2]
[2] BPI_1 BPI_1 [2]
[2] BPI_2 BPI_2 [2]

[2] BPI_3 BPI_3 [2]

L600

LB_RX_P
1 2

1
1
L615 L616
L618 Z600

10
C600 L619
[2] WG_GGE_PA_VRAMP WG_GGE_PA_VRAMP [2]
GGE_PA_LB_IN

2
2
GGE_PA_HB_IN

2G_LB
1 2 1 2 1 LB_RX_N

1
GND
LBIN LB OUT 9 1 2

1
C665 2 8
C666 GND LBOUT

2
2
L622 3 7 L623
[3] DCXO_32K DCXO_32K [3] C667 GND HBOUT VRF18-1
2G_HB 4 HB_RX_P

1
1 2 1 2 HBIN HB OUT 6 1 2 2 1

1
GND
VTCXO_PMU R633 1 2 VTCXO28-1 C668 VRF18-1 C669
C670

1
1

2
5
R / 0 / ohm / 0402

2
VRF18_PMU R634 1 2 VRF18-1 L625
R / 0 / ohm / 0402 L624

VIO18_PMU 1 2 VIO18 L626

GGE_PA_HB_IN
GGE_PA_LB_IN

2
2
[2] BSI-A_EN BSI-A_EN [2] HB_RX_N
[2] BSI-A_CK BSI-A_CK [2] 1 2
[2] BSI-A_DAT0 BSI-A_DAT0 [2]
[2] BSI-A_DAT1 BSI-A_DAT1 [2]
E3
D3
C3
J2
C2
A2
A3
B3
B4
A5
B5
A6
B6
B8
A8
A9
A10
A11
B11
D11
B10
C10
C7
J7
C8
J8
C9

[2] BSI-A_DAT2 BSI-A_DAT2 [2] U600

B B
[2] TXBPI TXBPI [2]
DET

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

[2,3]
SRCLKENA F3 D9
VTXHF

GND GND
[2,3] SRCLKENA SRCLKENA [2,3] G3 E9
3GL5_TX
2GLB_TX

3GH1_TX
3GH2_TX

GND GND
2GHB_TX

3GB1_RXP
3GB5_RXP
3GB2_RXP
3GB8_RXP

3GB1_RXN
3GB5_RXN
3GB2_RXN
3GB8_RXN

H3 GND GND F9
[2] CLK1_BB CLK1_BB [2] J3 GND GND G9
[10] SYSCLK_WCN SYSCLK_WCN [10] FDD RX TXO
C4 GND GND H9
CLK3_CMMB CLK3_CMMB D4 J9
[3] CLK4_AUDIO CLK4_AUDIO [3] GND GND
A1 B40_RXP DETGND D10
SH605 1 2 RX_BBQP
[2] RX_Q_P
[2] RX_Q_N
SH606 1 2 RX_BBQN B1 B40_RXN TMEAS C11 TMEAS
SH607 1 2 RX_BBIN
[2] RX_I_N
1

SH608 1 2 RX_BBIP
Two Application Circuit Conditions, LB_RX_P LB_RX_P C1 E10 VTCXO28-1 VTCXO28-1
[2] RX_I_P LB_RXP V28
TDD RX R639
2

1.TSX Circuit : X600=TSX, R653=R656=NC, R654=100K+-1%, R655=R657=0ohm LB_RX_N LB_RX_N D1 LB_RXN 3GTX_IP G10 TX_BBIP TX_BBIP
SH609 1 2 connect to main GND C674
[2] TX_Q_P TX_BBQP
1
2

[2] TX_Q_N
SH610 1 2 TX_BBQN 2.XTAL Circuit :X600=Mobile XTAL, R653=R656=0ohm, R654=R655=R657=NC HB_RX_P HB_RX_P E1 HB_RXP 3GTX_IN G11 TX_BBIN TX_BBIN
[2] TX_I_N SH611 1 2 TX_BBIN [3] AUXADC_REF Route AUXADC_REF with 4mil trace width TX(I/Q)
[2] TX_I_P SH612 1 2 TX_BBIP HB_RX_N HB_RX_N F1 F10 TX_BBQP TX_BBQP

1
R656
HB_RXN 3GTX_QP

1
VRF18-1 R645
R654 VRF18-1 F2 F11 TX_BBQN NCP15WF104F03RC
C685 0R VRXHF 3GTX_QN TX_BBQN
1 C675
2
C / 1000 / nF / 0402 NC

2
XTAL2 G2 RFVCO_MON
MT6166 TXVCO_MON L11 R610 close to 3G PA

2
R657 NC MT6166/VFBGA104/P0.4/B0.25/4.6X4.6 VRF18-1
[3] AUXADC_TSX Route AUXADC_TSX with 4mil trace width 4 GND HOT 3 XTAL1 J1 XTAL1 VTXLF J11 VRF18-1 2 1
2 1 X600
C676
H2 XTAL2 TXBPI H10 TXBPI TXBPI [2]
XO
1 HOT GND 2 VTCXO28-1 K1 VTCXO28 RCAL J10 RCAL
Test pin
1

R655 NC
[3] GND_AUXADC Route AUXADC_GND with 24mil trace width DCXO_32K_EN G1 32K_EN TST2 K11 R600
2 1

1
under AUXADC_REF/AUXADC_TSX trace SRCLKENA L1 L10
R653 EN_BB TST1
0R VTCXO28-1 BSI
2

SRCLKENA K2 CLK_SEL BSI_DATA2 G8 BSI-A_DAT2 BSI-A_DAT2 [2]

Close to each other C677
26M output

2
2

and nearby X600 CLK3_CMMB L2 XO3 BSI_DATA1 H8 BSI-A_DAT1 BSI-A_DAT1 [2]

Connect TSX/XTAL GND
to GND_AUXADC first E4 GND GND B7
F4 GND GND J6
than connect to main GND connect to main GND G4 RX(I/Q) D8
GND GND
H4 GND GND E8
[2,3] SRCLKENA
GND
GND
GND
GND
GND
GND
XO4
XO2
XO1
OUT32K
XMODE
AVDD_VIO18
VXODIG
VRXLF
RX_IP
RX_IN
RX_QP
RX_QN
BSI_EN
BSI_CLK
BSI_DATA0
GND
GND
GND
GND
GND
GND

[2,3] SRCLKENA
Route AUXADC_REF/AUXADC_TSX as differential trace with well GND shielding
CLK3_CMMB
J4
J5

L4
L5
L7
L8

F5
F8
F6

E5
K4
K3
K5
K6
K7
K8
K9
E7
E6

C5
D5
D7
H6
C6
D6

G6

K10

and route AUXADC_GND with 24mil trace width under R647

AUXADC_TSX/AUXADC_REF trace to provide return current path. VTCXO28-1 3

[3] CLK4_AUDIO CLK4_AUDIO BSI-A_DAT0 BSI-A_DAT0 [2]
2 DCXO_32K_EN
[10] SYSCLK_WCN SYSCLK_WCN
1
RX_BBIP
RX_BBIN
RX_BBQP
RX_BBQN

[2] CLK1_BB CLK1_BB BSI-A_CK BSI-A_CK [2]

[3] DCXO_32K DCXO_32K
BSI-A_EN BSI-A_EN [2]
Logic
XMODE VXODIG R649 XMODE
VRF18-1

MODE
DCXO_
VIO18 1 L630
32K_EN 2 XMODE
RX_BBIP

VIO18_VGPIO

A
RX_BBIN

VIO18 A
RX_BBQP

1
RX_BBQN

VTCXO28-1 3 R /10 / ohm / 0402 2 C682

VRF18-1
DCXO + 32K XO 0(GND) 1(VIO18) 1(VIO18) C / 1000 / nF / 0402
2

2 1
R648 C684
DCXO + 32K-Less 1(VTXCO28) 1(VTXCO28) 1(VTXCO28)
VXODIG
VIO18 1 Reserved LC filter
2 VXODIG
VTCXO28-1 3

Title
RF-2G
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Wednesday, January 02, 2013 Sheet 5 of 19

5 4 3 2 1

NC-4MIL_
 5 4 3 2 1

U101-C

GPS_RX_IN B16 GPS_RXIN GND_WBG A14

GPS_RX_IP A16 GPS_RXIP GND_WBG D18
GND_WBG B22
GND_WBG C16
GPS_RX_QN B14 GPS_RXQN GND_WBG C17
GPS_RX_QP B15 GPS_RXQP GND_WBG C18
GND_WBG C19
GND_WBG C20
WB_TXIN A19 WB_TXIN GND_WBG C15
WB_TXIP B19 WB_TXIP GND_WBG D16
GND_WBG D17
WB_TXQN B18 WB_TXQN GND_WBG D19
WB_TXQP A18 WB_TXQP GND_WBG D20
D GND_WBG C21 D
WB_RXIN A21 WB_RXIN
WB_RXIP A22 WB_RXIP
CONN_WB_CTRL0 E20 WB_CTRL0
WB_RXQN B20 WB_RXQN CONN_WB_CTRL1 F20 WB_CTRL1
U1006 WB_RXQP B21 D22 WB_CTRL2
WB_RXQP CONN_WB_CTRL2
3 OUT VCC 4 VCN_2V8_PMU CONN_WB_CTRL3 E22 WB_CTRL3
R1013 C22 WB_CTRL4

2
CONN_WB_CTRL4
2 GND NC 1 CONN_WB_CTRL5 C23 WB_CTRL5
1 C1022

1
CONN_XO_IN 2 C / 1000 / nF / 0402 AVDD18_WBG F18 C14 WB_RSTB
AVDD18_WBG CONN_RSTB
3 CONN_SEN E15 WB_SEN
CONN_SDATA E14 WB_SDATA
CONN_SCLK G12 WB_SCLK
SYSCLK_WCN [6]
CONN_F2W_DAT E13 FM_DATA
CONN_F2W_CLK F12 FM_CLK

CONN_XO_IN F14 CONN_XO_IN

MT6572/TFBGA428/P0.4/B0.25/10.6X10.6

WB_CTRL3

WB_CTRL2
ANT1004 ANT1003 WB_CTRL4
C WIFI/BT/GPS Single ANT Ref. C
WB_CTRL1

FEED
FEED
WB_CTRL5 Close to MT6572

1
1
CON1001
WB_CTRL0

50 Ohm
R1006 WB_RXIP SH1001
50 Ohm 1 2 50 Ohm AVDD18_WBG 1 2 VCN_1V8_PMU
1 2

1
1
C1042 R / 0 / ohm / 0402 4 3 WB_RXIN
L1004
1

C1001

2
6
5
NC
2

30
29 AVDD18_WB
28
27
26
25
24
23
22
21

U1000

2
WB_RX_IP
WB_RX_IN

WBG_ANT 50 Ohm 31 20 WB_RXQP

WB_CTRL5
WB_CTRL4
WB_CTRL3
WB_CTRL2
WB_CTRL1
WB_GPS_RF_IN WB_CTRL0 WB_RX_QP

W_LNA_EXT
AVDD18_WBT
SH1002
AVDD18_WB 1 2 VCN_1V8_PMU
50 Ohm 32 GPS_DPX_RFOUT WB_RX_QN 19 WB_RXQN
SH1003
AVDD18_GPS 1 2 VCN_1V8_PMU
Based on your system level design , if
better WiFi TX performance is needed on AVDD33_WB 33 AVDD33_WBT WB_TX_IP 18 WB_TXIP
1

your system, please refer to WiFi C1007 Star Conn

performance enhance proposal for WB/GPS/WBG 1V8
2
1

34 NC WB_TX_IN 17 WB_TXIN
50 Ohm C1008
2

35 16 WB_TXQP
1
1

NC WB_TX_QP
C1005 C1006
C / 1000 / nF / 0402
2
2

VCN_2V8_PMU 36 AVDD28_FM MT6627-NS/MQFN40/SMD/P0.4/5X5 WB_TX_QN 15 WB_TXQN

B B

37 FM_LANT_N GPS_RX_IP 14 GPS_RX_IP

[5] FM_RX_N_6572 FM_RX_N_6572
FM L1011
[5] FM_ANT 2 1 FM_LANT_P
38 13 GPS_RX_IN

1
FM_LANT_P GPS_RX_IN
L1012

GPS_RF 50 Ohm 39 GPS_RFIN GPS_RX_QP 12 GPS_RX_QP

2
AVDD18_GPS 40 11 GPS_RX_QN
refer to FM desense performance
AVDD18_GPS GPS_RX_QN
enhance proposal
VCN_2V8_PMU VCN_2V8_PMU
41
1

DVSS
C1002
2

AVDD28_FSOURCE
HRST_B
FM_DBG
F2W_DATA
F2W_CLK
SCLK
SDATA
SEN
CEXT
XO_IN

MT6627 SMD QFN40

1
2
3
4
5
6
7
8
9
10

Close to MT6627

SH1004
AVDD33_WB 1 2 VCN_3V3_PMU
WB_RSTB
1
1

CONN_XO_IN C1003
C1004
2
2

C / 1000 / nF / 0402
1
1

1
1

C1009
Based on your system level design , if C1010
FM_DATA
2
2

2
2

A
better GPS performance is needed on C1012 C1011
FM_CLK A
your system, please refer to GPS
performance enhance proposal
WB_SCLK

WB_SDATA
Title
WB_SEN Wireless Connectivity
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Wednesday, January 02, 2013 Sheet 6 of 19

5 4 3 2 1

NC-4MIL_
TCXO/SMD/2.5X2.0/IT2205BE
 5 4 3 2 1

[2,3] PMIC_SPI_CS

2
R403
20K

1
U101-F
HW trapping PIN
DRAM DRAM
AF6 Data Ctrl 20K: VM=1.8V
D ED31 ED31
AE6 AF22 D
ED30 ED30 ECS0_B ECS0_B
ED29 AF8 ED29 ECS1_B AF19 ECS1_B
ED28 AE7 ED28 NC : VM=1.2V
ED27 AE8 ED27 EWR_B AF21 EWR_B
ED26 AC9 ED26 ERAS_B AD21 ERAS_B
ED25 AC7 ED25 ECAS_B AB20 ECAS_B
ED24 AB9 ED24 ECKE AD24 ECKE R / 0 / ohm / 0402 R401
AF5 VM_PMU VIO_EMI
ED23 ED23 2 1
ED22 AE5 ED22 EDQM0 AB13 EDQM0 Memory MCP
ED21 AD5 ED21 EDQM1 AD12 EDQM1
ED20 AC5 ED20 EDQM2 AD8 EDQM2
ED19 AE4 ED19 EDQM3 AE12 EDQM3
ED18 AF3 ED18
ED17 AF2 ED17 EDQS0 AA14 EDQS0
ED16 AB6 ED16 EDQS1 Y13 EDQS1
ED15 AE11 ED15 EDQS2 Y8 EDQS2
ED14 AD15 ED14 EDQS3 AA9 EDQS3
ED13 AE10 ED13
ED12 AE9 ED12 EDQS0_B Y14
AF12 AA13 VIO_EMI
ED11 ED11 EDQS1_B
ED10 AF11 ED10 EDQS2_B AA8
AF9 Y9 U401
ED9 ED9 EDQS3_B
ED8 AC13 ED8 C9 VDDQ CLK G8 EDCLK
ED7 AE16 ED7 EDCLK0_B Y18 EDCLK_B D10 VDDQ CLK# H8 EDCLK_B
AE13 AA18 EDCLK C401 C / 4700 / nF / 0603 E9 E3
ED6 ED6 EDCLK0 VDDQ CKE0 ECKE
AE15 2 1 F10 J2
ED5 ED5 VDDQ CS0# ECS0_B
ED4 AE14 ED4 EDCLK1_B AA19 G9 VDDQ RAS# G2 ERAS_B
ED3 AF15 ED3 EDCLK1 Y19 Put C402 & C403 between BB & memory. J10 VDDQ CAS# H2 ECAS_B
ED2 AF16 ED2 K9 VDDQ WE# K1 EWR_B
ED1 AC15 ED1 L9 VDDQ BA0 J3 EBA0
ED0 AB16 ED0 ND0 AA2 NLD0 C402 M10 VDDQ BA1 K2 EBA1
NAND I/F Y2 N9 J8
ND1 NLD1 2 1 VDDQ DM0 EDQM0 BA[1:0] = EA[15:14] (LPDDR1)
AB17 VREF1 ND2 W1 NLD2 C403 DM1 G6 EDQM1
AC11 VREF0 ND3 W3 NLD3 2 1 H10 VDDD DM2 F8 EDQM2
ND4 AB1 NLD4 H1 VDDD DM3 E7 EDQM3
DRAM
ND5 AD2 NLD5 M1 VDDD DQS0 J7 EDQS0
AB18 Address W4 B8 G5
EA18 ND6 NLD6 VDDD DQS1 EDQS1
C AE18 EA17 ND7 AE1 NLD7 D1 VDDD DQS2 H7 EDQS2 C
AE17 EA16 ND8 W2 NLD8 P8 VDDD DQS3 E5 EDQS3
EBA1 AE21 EA15 ND9 Y3 NLD9
EBA0 AB19 EA14 ND10 AC2 NLD10 C129 C / 1000 / nF / 0402 C1 VSSD DQ0 L4 ED0
EA13 AE22 EA13 ND11 AC1 NLD11 2 1 J1 VSSD DQ1 L5 ED1
EA12 AC23 EA12 ND12 Y4 NLD12 B9 VSSD DQ2 L6 ED2
EA11 AD22 V5 C110 C / 4700 / nF / 0603 H9 L7 ED3
EA11 ND13 NLD13 VSSD DQ3
EA10 AD18 AE2 2 1 P9 K8 ED4
EA10 ND14 NLD14 VSSD DQ4
EA9 AE25 EA9 ND15 V1 NLD15 M2 VSSD DQ5 L8 ED5
BA[1:0] = EA8 AE23 EA8 DQ6 K7 ED6
EA[15:14] EA7 AF25 EA7 N10 VSSQ DQ7 K5 ED7
EA6 AE24 EA6 M9 VSSQ DQ8 K6 ED8
(LPDDR1) EA5 AF24 W5 J9 G7
EA5 NCEB NCEB VSSQ DQ9 ED9
EA4 AE26 EA4 NWRB Y5 NWRB G10 VSSQ DQ10 J6 ED10
EA3 AC18 EA3 NREB AB2 NREB F9 VSSQ DQ11 J5 ED11
EA2 AE19 EA2 NCLE AC3 NCLE E10 VSSQ DQ12 H6 ED12
EA1 AE20 EA1 NALE AD3 NALE L10 VSSQ DQ13 H5 ED13
EA0 AF18 EA0 NRNB AE3 NRNB K10 VSSQ DQ14 J4 ED14
GPIO47 AB3 D9 VSSQ DQ15 G3 ED15
C10 VSSQ DQ16 G4 ED16
AC22 ERESET DQ17 F4 ED17
EA0 K4 A0 DQ18 E4 ED18
EA1 L1 A1 DQ19 F5 ED19
EA2 L2 A2 DQ20 H3 ED20
EA3 L3 A3 DQ21 H4 ED21
MT6572/TFBGA428/P0.4/B0.25/10.6X10.6 EA4 C2 A4 DQ22 E6 ED22
EA5 D2 A5 DQ23 F7 ED23
EA6 E1 A6 DQ24 F6 ED24
EA7 D3 A7 DQ25 D5 ED25
EA8 E2 A8 DQ26 E8 ED26
EA9 D4 A9 DQ27 D6 ED27
EA10 K3 A10 DQ28 D8 ED28
EA11 F2 A11 DQ29 D7 ED29
EA12 F1 A12 DQ30 C8 ED30
DQ31 C7 ED31
Please make sure the ball map is R1 DNU
R2 DNU NLD8 P2 NLD8
VIO18_PMU
R9 DNU NLD9 P3 NLD9
B B
match to the MCP type you selected R10 DNU NLD10 N4 NLD10
B5 VCCN NLD11 P4 NLD11
N5 P5 NLD12

1
VCCN NLD12
C404 C5 VSSN NLD13 N7 NLD13
C / 1000 / nF / 0402 P6 VSSN NLD14 M7 NLD14

2
B1 NC NLD15 N8 NLD15
ECKE B2 NC CKE1 DNU A2
B10 NC NC P1
ECS1_B F3 NC G1
NC CS1# VIO18_PMU
M3 EA13 EA13
NLD0 N1 A13 NC
NLD0
NLD1 N2 B4 NCLE
1

NLD1 CLE
NLD2 N3 NLD2 ALE C4 NALE
NLD3 M5 B6 R402
NLD3 /CE NCEB 47K
NLD4 P7 NLD4 /RE B3 NREB
NLD5 M6 NLD5 /WE B7 NWRB
2

NLD6 N6 NLD6 /WP C3 WATCHDOG

NLD7 M8 NLD7 R/#B C6 NRNB

P10 NC NC M4
A10 DNU DNU A9

A A

Title
Memory
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Wednesday, January 02, 2013 Sheet 7 of 19

5 4 3 2 1
 5 4 3 2 1

1
Speaker close to IC
close to C501

2
connector
[3] AU_SPKP same power domain
SPK501 Earphone Audio

2
2 close to IC
C502 close to connector
1 R505
VIO28_PMU 1 2

1
R506
[3] AU_SPKN

1
C503 [2] EINT_HP
2 1

2
D D

Reserve bead+C footprint for FM

2
2
performance tuning C530 C529
NC

1
1
C519 NC
Based on your system level design , if better BEAD503
HP_MIC BEAD501
desense performance is needed on your R507 6
2
system , please refer to desense HP_MP3L BEAD502 4
[3] AU_HPL
performance enhance proposal 1 2 1 2
R508
EAR_DET 5
Receiver 1 2 HP_MP3R BEAD505 3
[3] AU_HPR
BEAD504 1 2

1
1
close to IC close to connector CON501
C520 C521

2
1
C506
C522

1
1

2
[3] AU_HSP VR501
VR0402
VR0402

1
REC501
C505
2

2
2

RECEIVER

1
1
FM_ANT [10]
[3] AU_HSN

2
C504

1
2 R509
2 R510
L502

Based on your system level design , if better ESD

performance is needed on your system, please 1
C SH503
refer to ESD performance enhance proposal C
1 2 FM_RX_N_6572 [10]

Single via to GND plane

MICBIAS1

Handset Microphone 1 Earphone MICPHONE

MICBIAS0

1
R511 GND of C(4.7uF) and headset
Close to BB Close to MIC

1
R514 should tie together and single

2
C523 C531 via to GND plane
[3] AU_VIN1_N 2 1 AU_VIN1_N1 1 2 GND_SIGNAL

2
1
Close to C526 C / 4700 / nF / 0603
Close to

1
MIC

1
R515 BB Close to EarJack
R512

2
2
Analog MIC C525
C511

2
1
[3] AU_VIN0_P 2 1

1
2
C527
C513 C508

2
1 MIC1 C524

2
1
C / 4700 / nF / 0603 2 [3] AU_VIN1_P 2 1 HP_MIC
C512
Microphone
[3] AU_VIN0_N 2 1

2
1
B B
R513

1
R516 together then single

1
2
[3] ACCDET
1 2 via to main GND

C510
C509

2
1
R517
if you use digital MIC,
please change cap

2
(C511,C512) to 1.0uF

together then single via to main GND

A A

Title
Audio
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 8 of 19

5 4 3 2 1

NC-4MIL_
 5 4 3 2 1

LCM
cap for iSINK BL flicking improve, CON1201

close to LCM connector

ISINK0 1 LEDK1
VBAT 2 LEDA

2
C1203 3
C / 1000 / nF / 0402 YU
D 4 XR D

1
5 YD
6 XL
VIO28_PMU 7 VDD2_(AVDD) CTP
VIO18_PMU 8 VDD1_(IOVDD)
ISINK0 9 LEDK8
[2] LPTE 10 TE
11 IM0
12 IM1
13 IM2
14 LANSEL
[2] GPIO_LRSTB 15 RESETB
ISINK3 16 LEDK7
ISINK3 17

GT_DRV0
GT_DRV1
GT_DRV2
GT_DRV3
GT_DRV4
GT_DRV5
GT_DRV6
GT_DRV7
GT_DRV8
LEDK6
ISINK2 18 LEDK5
ISINK2 19 LEDK4

41
40
39
38
37
36
35
34
33
32
31
ISINK1 20 LEDK3 U1201
Based on your system level design , if ISINK1 21 LEDK2

EP
better LCD uniformity is needed on 22

DRV0
DRV1
DRV2
DRV3
DRV4
DRV5
DRV6
DRV7
DRV8
DB17

AGND
[3] ISINK0 ISINK0
23 DB16
your system , please refer to BLISINK0 24
[3] ISINK1 ISINK1 DB15 GT_SENS0 1 30 GT_DRV9
uniformity with iSINK improve proposal 25 SENS0 DRV9
ISINK1 DB14 GT_SENS1 2 29 GT_DRV10
26 SENS1 DRV10
[3] ISINK2 ISINK2 DB13 GT_SENS2 3 28 GT_DRV11
27 SENS2 DRV11
ISINK2 DB12 GT_SENS3 4 27 GT_DRV12
28 SENS3 DRV12
[3] ISINK3 ISINK3 DB11 GT_SENS4 5 26 GT_DRV13
29 SENS4 DRV13
ISINK3 DB10 GT_SENS5 6 25 GT_DRV14
30 SENS5 DRV14
DB9 GT_SENS6 7 24 GT_DRV15
31 SENS6 DRV15
DB8 GT_SENS7 8 23 GT_DRV16
32 SENS7 DRV16
DB7 GT_SENS8 9 22
33 SENS8 NC
DB6 GT_SENS9 10 21 GPIO_CTP_RSTB [2]
34 SENS9 RSTB
DB5
35 DB4
36 DB3
C C
37 DB2
AVDD28
AVDD18
DVDD12
DGND
INT
SENSOR_OPT1
SENSOR_OPT2
I2C_SDA
I2C_SCL
DVDDIO

38 DB1
39 DB0
11
12
13
14
15
16
17
18
19
20

40 RDX
41 WRX C1204 C1207
42 DCX C / 1000 / nF / 0402 C / 1000 / nF / 0402
43 CSX 1 2
Based on your system level design , if better DVDDIO_CTP
2 1
desense performance is needed on your 44 NC
45 NC
system , please refer to desense 46 NC
47 NC
performance enhance proposal 48 NC
AVDD18_CTP
DVDD12_CTP

49 GND SCL_1 [2,21]

Based on your system level design , if better VIO28_PMU
SDA_1 [2,21]
desense performance is needed on your 50 NC
100-ohm EINT_CTP [2]
100-ohm
system , please refer to desense 51
2
2

DSI_VSS
[2] MIPI_TDP1 52 DSI_D1P
[2] MIPI_TDN1
performance enhance proposal 53 C1205 C1206
DSI_D1N
1
1

54 DSI_VSS
55 DSI_CLKP
56 DSI_CLKN
57 DSI_VSS
58 DSI_D0P
59 DSI_D0N
[2] MIPI_TCP 60
[2] MIPI_TCN DSI_VSS
61 VDD3(NC)

[2] MIPI_TDP0
[2] MIPI_TDN0
44
43
42
41

B B

20 21
19 22
GT_DRV9 18 23 GT_DRV16
0R YAGEO PN: YC102-FR-070R GT_DRV10 17 24 GT_DRV15
GT_DRV11 16 25 GT_DRV14
GT_DRV12 15 26 GT_DRV13
14 27
13 28
GT_SENS0 12 29 GT_DRV8
GT_SENS1 11 30 GT_DRV7
GT_SENS2 10 31 GT_DRV6
GT_SENS3 9 32 GT_DRV5
GT_SENS4 8 33 GT_DRV4
GT_SENS5 7 34 GT_DRV3
GT_SENS6 6 35 GT_DRV2
GT_SENS7 5 36 GT_DRV1
GT_SENS8 4 37 GT_DRV0
GT_SENS9 3 38
2 39
1 40

CON1202

A A

Title
LCD, Touch
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 9 of 19

5 4 3 2 1
 5 4 3 2 1

2
C1301
D D

1
Main CAM C / 1000 / nF / 0402
2V8
VCAM_AF_PMU

2v8 VCAMA_PMU

1
C1302

2
Reserve cap footprint for better
CON1301
camera performance Based on your system level design , if better
1 AGND AF_AGND 2
3 STROBE AF_VCC 4 please refer camera power desense performance is needed on your
[2] SDA_0 5 SIOD PD 6 100-ohm 100-ohm
7 8 noise improve proposal system , please refer to desense MIPI_RDP1 [2]
[2] SCL_0 SIOC AVDD
9 10 SDA_0 [2] MIPI_RDN1 [2]
[2] GPIO_CMRST RESETB INTD performance enhance proposal
11 PCLK INTC 12 SCL_0 [2]
13 VSYNC DGND 14
15 HREF MDP1 16
[2] GPIO_CMPDN 17 PWDN MDN1 18
19 DATA9 DGND 20
21 DATA8 MCP 22 MIPI_RCP [2]
23 DATA7 MCN 24 MIPI_RCN [2]
25 DATA6 DGND 26
27 DATA5 MDP0 28
29 DATA4 MDN0 30
31 DATA3 DGND 32
33 DATA2 XCLK 34 CMMCLK [2]
35 DATA1 DVDD 36 MIPI_RDP0 [2]
37 DATA0 DOVDD 38 MIPI_RDN0 [2]
39 DGND DGND 40

C C

1v2
VCAMD_PMU

1
C1303

2
C / 1000 / nF / 0402

1v8 VCAMD_IO_PMU

1
only 150mA from VCAMD
C1310

2
C / 1000 / nF / 0402 please check your CAM module DVDD current
external LDO is required for DVDD current > 150mA

Sub CAM
CON1302

PWDN 1 GPIO_CMPDN2 [2]

HREF 3 CMHSYNC
B B
VSYNC 5 CMVSYNC
RESET 7 GPIO_CMRST2 [2]
DVDD 9 VCAMD_PMU
DOVDD 11 VCAMD_IO_PMU
AVDD 13 VCAMA_PMU
DGND 15
PCLK 17 CMPCLK
DGND 19
XCLK 21 CMMCLK
AGND 23
SIO-D 24 SDA_0 [2]
SIO-C 22 SCL_0 [2]
D9 20 CMDAT7
D8 18 CMDAT6 Based on your system level design , if better
D7 16 CMDAT5
D6 14 CMDAT4 desense performance is needed on your
D5 12 CMDAT3
CMHSYNC
system , please refer to desense CMHSYNC [2]
D4 10 CMDAT2
CMVSYNC CMVSYNC [2]
D3 8 CMDAT1 performance enhance proposal
CMPCLK CMPCLK [2]
D2 6 CMDAT0
[2] CMMCLK CMMCLK
D1 4
D0 2

CMDAT4 CMDAT4 [2]

CMDAT5 CMDAT5 [2]
CMDAT6 CMDAT6 [2]
CMDAT7 CMDAT7 [2]

A A

CMDAT0 CMDAT0 [2]

CMDAT1 CMDAT1 [2]
CMDAT2 CMDAT2 [2]
CMDAT3 CMDAT3 [2]

Title
Camera
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 10 of 19

5 4 3 2 1
 5 4 3 2 1

USB HS IF
CON1401
D D

7
8
Based on your system level design , if

GND0
GND1
better ESD performance is needed on
5 GND
your system, please refer to ESD
performance enhance proposal
4 ID

[2] USB_DP 3 D+
[2] USB_DM

2 D-

1 VBUS

GND3
GND2
C C

6
9
VBUS

Based on your system level design , if better

desense performance is needed on your
system , please refer to desense
performance enhance proposal

B B

A A

Title
USB
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 11 of 19

5 4 3 2 1
 5 4 3 2 1

Micro SD CARD
D Shielding connect to ground D

VMCH_PMU

CON1801

7 DAT0
8 DAT1
1 DAT2
Based on your system level design , if 2 DAT3
better MSDC signal quality is needed on
3 CMD
[2] MC1DAT2
your system, please refer to SD card D 5
[2] MC1DAT3 CLK
4 VDD
[2] MC1CMD
performance enhance proposal
6 VSS
[2] MC1CK

[2] MC1DAT0 10
[2] MC1DAT1 CD2
C 9 C
CD1
11 SHIELD

1
12 SHIELD
C1801 13 SHIELD
14

2
SHIELD

[2] MC1_INS

B B

A A

Title
Memory CARD
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Thursday, December 27, 2012 Sheet 12 of 19

5 4 3 2 1
 5 4 3 2 1

D D
Based on your system level design , if better ESD performance is needed
on your system, please refer to ESD performance enhance proposal

CON1901 SIM1

11
10
9
C4

G
G
G
DP DM C8

[3] SCLK C3 SIM1 C7

CLK I/O SIO [3]

[3] SRST C2 RST VPP C6

VSIM1_PMU C1 VCC GND C5

1
C C1901 C
C / 1000 / nF / 0402

2
[3] SCLK2 3 CLK SIM2 I/O 7 SIM2 SIO2 [3]

[3] SRST2 2 RST VPP 6

VSIM2_PMU 1 VCC GND 5

G
G

1
C1902

12
13
C / 1000 / nF / 0402

2
B B

A A

Title
SIM
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Thursday, December 27, 2012 Sheet 13 of 19

5 4 3 2 1
 5 4 3 2 1

D D

DO NOT put pull-up

resistor on PWRKEY SW2001
[3] PWRKEY 2 1
4 3
Power Key

5
Based on your system level design , if better ESD
performance is needed on your system, please
C refer to ESD performance enhance proposal C

R2002 SW2002 R2004

[2] KROW0 1 2 2 1 1 2 KCOL0 [2] Volume Up
4 3

5
B B

R2003 SW2003 R2005 Volume Down

[2] KCOL0 1 2 2 1 1 2 KROW1 [2]
4 3

5
A A

Title
KP
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Thursday, December 27, 2012 Sheet 14 of 19

5 4 3 2 1
 5 4 3 2 1

G-Sensor ALS & PS Sensor

VIO28_PMU ALS I2C address: 0X90 to 0X92
D D
G Sensor I2C address
PS I2C address : 0XF0 to 0XF2
0000 111X
VIO18_PMU
X : pin ADDR C2103

2
R2126
C / 1000 / nF / 0402

1
U2106

2
1
1
7 VDD ADD 1
U2103
3 VDDIO SDA 2 SDA_1 [2,12]
D2110 1 GND VDD 3
11 VDDIO2 SCL 12 SCL_1 [2,12] CM3652
SCL 6 SCL_1 [2,12]

2
SDA 5 SDA_1 [2,12]
10 VDD2 INT 5 EINT_ACC [2] 2 LED INT 4 EINT_ALPXS [2]

1
4 RES GND2 6

1
C2116 C2104

GND
GNDIO
2

9
8

2
C C

B B

A A

Title
MEMS Sensors
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Thursday, December 27, 2012 Sheet 15 of 19

5 4 3 2 1
 5 4 3 2 1

D SH8001 1 2 D
[2] SPI_MISO SPI_MISO [2]
[2] SPI_MOSI
SH8002 1 2 SPI_MOSI [2]
[2] SPI_SCK
SH8003 1 2 SPI_SCK [2]
SH8004 1 2 SPI_CSB [2]
[2] SPI_CSB

[2] GPIO_TV_RST SH8009 1 2 GPIO_TV_RST [2]

CMMB
[2] EINT_CMMB SH8010 1 2 EINT_CMMB [2]

VGP1_PMU SH8011 1 2 VGP1_PMIC

VGP3_PMU SH8012 1 2 VGP3_PMIC

C C

[2] GPIO_FLASH_EN SH8007 1 2 GPIO_FLASH_EN [2]

[2] GPIO_FLASH_SEL SH8008 1 2 GPIO_FLASH_SEL [2] Flash LED driver

SH8005 1 2 EINT_MAG [2]

[2] EINT_MAG
SH8006 1 2 EINT_GY [2]
[2] EINT_GY Magnetic, Gyro sensor
B B

A A

Title
Others
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Thursday, December 27, 2012 Sheet 16 of 19

5 4 3 2 1

NC-4MIL_
 5 4 3 2 1

D D

Camera Flash Torch : <150mA

Flash : <1000mA
LED1301

FLASH_LED/LUW_F8DN

U1304 1 A K 2

VBAT 1 10

1
VIN VOUT
C1326

1
2 C1 PGND 9

2
C1329
C / 1000 / nF / 0402 3 8

2
C2 SGND
GPIO_FLASH_SEL 4 FLASH FB 7

C GPIO_FLASH_EN 5 6 C

GND
EN RSET

1
11
C1325
C / 4700 / nF / 0603

2
1
1
R1317
R1315
R0805

2
2
VIH = 1.3V Rset Rsen

Yageo : RL0805FR-7W0R4L

SENSOR_FLASH_SEL
H: Flash mode Vfb(Torch) = 47mV
L: Torch mode Vfb(Flash) = 1.26/Rset x10.2K
I_out = Vfb / Rsen
B B

A A

Title
LED flash
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Thursday, December 27, 2012 Sheet 17 of 19

5 4 3 2 1
 5 4 3 2 1

M-Sensor Gyro Sensor

I2C Address: 0x68 (Write:0xD0, Read:0xD1)
D D

2
M Sensor I2C address C2110
SCL_1 50V

1
CAD1 / CAD0 / Add SDA_1
VIO28_PMU VIO18_PMU 0 / 0 / 0x0C

25
24
23
22
21
20
19
U2105 0 / 1 / 0x0D U2102
1 / 0 / 0x0E
B1 D4

SCL
SDA
GND
VDD 1RSTN
/ 1 / 0x0F

RESV
RESV
CPOUT

CLKOUT
C4 VID TRG C3 1 CLKIN GND 18
2 17

1
NC NC
C2 TST1 SCL/SK A3 SCL_1 3 NC NC 16
C2118 4 15
NC NC

2
B3 RSV SDA/SI A4 SDA_1 5 NC NC 14

1
6 IME_DA VDD 13 VIO28_PMU
C2117 D1 B4

1
CAD0 SO

2
D2 A2 C2109

IME_CL
VLOGIC
AD0
REGOUT
FSYNC
INT
CAD1 CSB

7
8
9
C1 A1 EINT_MAG

10
11
12
VSS DRDY
EINT_GY
C C
VIO18_PMU

1
1
C2107
C2108

2
2

B B

A A

Title
eCompass, Gyro
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Monday, December 24, 2012 Sheet 18 of 19

5 4 3 2 1
 5 4 3 2 1

VDDIO

VGP1_PMIC 2 1 C1603 C1604

1
1
SH1601

2
2

1
C1601
C / 1000 / nF / 0402

2
D D

VDD_1V2_CMMB VDDRF

FB1601

VGP3_PMIC 2 1
SH1602 C1605 C1606

1
1

1
C1602
C / 1000 / nF / 0402

2
2

2
C C

GPIO_TV_RST

EINT_CMMB

SPI_CSB IF258
SPI_MOSI VDDRF
C1611 VDD_1V2_CMMB
SPI_MISO

1
SPI_SCK L1602
Y1601

1
C1608 R1603
4 GND2 X1 1 2 1 2 1 CLK3_CMMB

2
1
1

L1601 3 2

1
X2 GND1 C1607

2
1
C1612 C1609 C1610 26MHz co-clock
2
2

VDDRF
1 2

1
2
C1613
U1601

16
15
14
13
12
11
10
9
33

2
ANT1601

GND

MIXIN
XTALP
VDD12
XTALN

VDDRF
VDDBB
REGCAP
L1609

LNALOAD
C1615 C1614 17 8
RFGND MMIS_D3 SPI_CSB
CMMB_ANT 18 UHFIN MMIS_VLD 7 SPI_MOSI
L16071 2 1 2 1 2 19 6
NC1 MMIS_CLK SPI_SCK
VDD_1V2_CMMB 20 VDD12 MMIS_DO 5 SPI_MISO
B 1 2 21 4 VDDIO B

2
2
GPIO15 VDDIO
TP1601 1 22 GPIO7/UART_TXD GND 3
L1605 L1606 23 2 VDD_1V2_CMMB
GND VDD12
VDDIO 24 VDDIO GPIO14 1 EINT_CMMB
close to the chip

1
1
NC2
NC3
GPIO1
RSTN
MGND
MMIS_D2
MMIS_D1
VDDIO
VDDIO

25
26
27
28
29
30
31
32
1 TP1602

1
1
R1604
R1606

2
2

The circuit
GPIO_TV_RST
is used for
Close to Antenna
antenna
matching

Note:
Leave these NC pins floating, do not
connect them to GND or Power

A A

Title
CMMB
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Monday, December 24, 2012 Sheet 19 of 19

5 4 3 2 1

NC-4MIL_