A Reduced Switching Loss PWM Strategy to Eliminate

Common Mode Voltage In Multilevel Inverters

Nho-Van Ng., Tam Ng. Khanh Tu, Hai Quach Thanh Hong-Hee Lee
Department of Electrical and Electronics Engineering Department of Electrical Engineering
Hochiminh City University of Technology University of Ulsan
Hochiminh City, Vietnam Ulsan, Korea
nvnho@hcmut.edu.vn hhlee@ulsan.mail.ac.kr

Abstract— This paper introduces a novel PWM technique to
eliminate common mode voltage (CMV) in multilevel inverters
using the three zero common mode vectors. Similarly, as in
conventional PWM for multilevel inverters, this PWM can be
properly depicted in an active two-level voltage inverter. With
the help of two standardized PWM patterns, the
characteristics of the PWM process, as a switching time
diagram and switching state sequence, can be fully explored in
that active inverter. Due to the existence of an unequal number
of commutations of three-phases in each sampling period, the
optimization of the switching loss is achieved by a proposed
current mapping algorithm. The switching loss reduction can
be up to 25% as compared to the same PWM technique with
non-optimized algorithms. The theoretical analysis is verified
by simulation and experimental results.
I. INTRODUCTION
In recent year, great progress has been made in the
development of multilevel inverters in electric drives and
other applications. Two basic circuits are commonly used in
practice: diode clamped multilevel inverters, cascaded
multilevel inverters as shown in Fig. 1. Three main PWM
schemes are commonly used are the space vector PWM, the
carrier-based PWM, and the selective harmonic elimination
PWM techniques [1-3].
It has been well-known that the common-mode voltages
are associated to the excessive bearing currents which may
conventional Discontinuous PWM technique (DPWM) [9].
In order to attain reduced common mode voltage at a high
modulation index, a new DPWM pattern from three non-
nearest vectors was proposed [10]. In another work, a trade-
off in the THD factor and switching loss for reducing the
number of common mode current pulses (dv/dt) could be
managed with a change in sequence of the non-nearest
vectors [11].
In order to avoid the common mode influence, in
another trend, researchers have tried to fully eliminate the
common mode voltage. The idea of complete CMV
elimination that restricts the inverter switching states to
those states of zero CMV was first proposed by K.
Ratnayake and Y. Murai in [12] for a three level NPC
inverter. In [13], the modulation of selected zero CMV
states has been applied to the three level NPC using both
carrier based and space vector modulation scheme. Similar
to [12], the method utilizes three zero CMV vectors in
three level NPC inverter to synthesize the reference output
voltages. However, the rule of distribution of these vectors
in each switching sequence is not mentioned. Furthermore,
the symmetrical double sided pattern which consists up to
twelve commutations causes a considerable switching loss.
SW1A
A B C
vdc
SW2A

cause premature motor bearing failure and electromagnetic SW1A

interference [4-6]. There have been a number of approaches vdc

SW3 A vdc vdc vdc

to cope with the CMV issue including the use of extra SW4 A
SW2A
O
hardware with passive and/or active devices. However, the A B C

extra hardware utilization causes a significant increase in vdc

SW3A
the system’s volume or much more complex control vdc vdc vdc
methods. The multi-level inverters have high a number of vdc
SW4 A
switching states that can either reduce or eliminate the
CMV. Based on this advantage, many researches for the O

CMV mitigation have been made using multi-level

inverters [7-8]. Fig. 1. Multilevel Inverter circuits: a) five-level Diode clamped inverter
and b) five-level cascade inverter
In partial PWM methods to eliminate common mode
voltage, the output voltage can be obtained normally by a

978-1-4799-5776-7/14/$31.00 ©2014 IEEE 219

 In this paper, a simple carrier based method to cope with and
this problem is presented. Its main contributions are s1X ≤ s 2X ≤ ....... ≤ s n−2X ≤ s n−1X ,X=A,B,C ( for diode
clarified in the following points:
clamp inverter topology) (4)
- As a general principle for an n-level inverter, all n −1
switching sequences and corresponding switching time The component (∑ s jX )Vdc (X=A,B,C) in (3) is called
diagrams will be derived from two generalized PWM j=1
patterns. The two patterns represent switching state n −1
sequence of corresponding active two level inverter. The the switching voltages. We define VXn = ∑ s jX (*) as the
algorithm to select the PWM pattern can be applied to j=1
arbitrary number of levels without losing the generality. normalized switching voltage which, for further analysis,
- The number of commutations per sampling period are can be used to represent VXO . Relationship between VXn
reduced to eight. Besides, the switching state sequence is and VXO is described as
locally optimized within the standardized PWM patterns,
which helps to reduce switching loss. VXO n −1
VXn = + (5)
The experimental results obtained with five-level Vdc 2
cascaded inverter are used for verifying the performance of
the proposed PWM strategy.
The normalized switching voltage VXn (*) can be
decomposed into two components LX and sX :
II. PROPOSED PWM METHOD TO ELIMINATE
COMMON MODE VOLTAGE VXn = LX + s X (6)

A. Voltage modeling of multilevel inverter and offset During a sampling period, L X is a constant integer
condition for eliminating common mode voltage
value which represents the base component of VXn and s X
Due to the difference in structure of the diode clamped is the active component of VXn which can be changed
inverter and cascade inverter, as illustrated in Fig. 1 for
five-level inverter, established rules of switching between 0 and 1 during a sampling time period. Taking (5)
combinations for a same reference output voltage are and (6) into account, the equivalent circuit of the
completely different. In this paper, the analytical process for instantaneous voltage of VXO is derived as in Fig. 2(a).
the two topologies can be unified by a simple voltage ( LA , LB , LC ) is named as the normalized three phase base
modeling. With selected neutral point ‘O’ and designated
voltages and (s A ,s B ,sC ) the normalized three phase active
switches of A-phase represented as
voltages in Fig. 2a.
SW1A ,SW2A ,SW3A ,SW4A for the two topologies in Fig.
1, the pole voltage vAO is generally determined as If ξX is defined as the average active component of s X
in a sampling period, the average value of VXn defined as
VAO = (s1A + s 2A + s3A + s 4A ) Vdc − 2Vdc (1)
v Xn can be derived as follows:
where s1A ,s 2A ,s3A ,s 4A represent the switching states of
v Xn = LX + ξ X ; 0 ≤ ξ X ≤ 1 (7)
SW1A ,SW2A ,SW3A ,SW4A respectively, s1A is ‘1’ if SW1A is
on otherwise its value is ‘0’. and the equivalent circuit of the average voltage of VXO
can now be described as in Fig. 2(b).
It should be noting that s1A ,s 2A ,s3A ,s 4A can be selected
randomly in the five level cascaded inverter while are Let define v*X 1 (X=A,B,C) the reference output
further restricted in five level diode clamp inverter due to fundamental voltages, v Xn in (6) can also be expressed as
the limit of its switching combinations. The constraint is
simply expressed as v*X 1 *
v Xn = + voff (8)
s1A ≤ s 2A ≤ s3A ≤ s 4A (2) Vdc
*
For an n-level inverter of the two topologies, (1) and (2) The offset voltage v off of the circuit in Fig. 2(c), for any
can be generalized as, X=A,B,C :
PWM method can be designed to have any value in the
(n−1) limits as:
VXO = (s1X +s2X +.... +sn−2X +sn−1X )Vdc − Vdc
2
(3) MIN * MAX
n−1
(n−1) v0min = − ≤ voff ≤ v0max = (n −1) − (9)
= (∑sjX )Vdc − Vdc Vdc Vdc
j=1 2

220
 where MAX and MIN are the highest and the smallest
of the three fundamental voltages (v*A1 , v*B1 , vC* 1 ) and n is the
number of levels.
The equivalent circuit of the average voltage of VXO
following (5),(8) is described in Fig. 2c.
It can be seen from (11) that under the condition of the
eliminating CMV PWM control:
f n = f ZCMV = 3(n − 1) / 2 (13)
For example, considering the cascaded five level
inverter in Fig. 3, among 125 possible combinations, there
are 19 switching combinations which produce zero CMV.
All zero CMV vectors satisfy (13) with f n = 6 . With a
normalized switching state of ZCMV described as
(VAn ,VBn ,VCn ) = (4,1,1), for example, the pole leg voltages
are derived using (5) as VAO = 2Vdc , VBO = − Vdc ,
VCO = −Vdc .

Fig. 2. a) Equivalent circuit of instantaneous three-leg voltages of n-

level voltage source inverter; b) Average voltages modeling of three-leg Fig. 3. Five-level space vector diagram with zero CMV state (bold
voltages; c) Average voltages modeling from reference fundamental letters)
voltage and offset voltage components; d) Total switching voltage and its
components ( Fe = ξ A + ξ B + ξ C , FL = LA + LB + LC ).
In case of the equivalent circuits described in terms of
average voltages in a sampling period as shown in Fig. 2(b)
and Fig. 2(c), with a note that (v*A1 + v*B1 + vC* 1 ) = 0 , the
The offset for eliminating CMV v0 ff , ZCMV condition of zero average CMV results in:
*
The common mode voltage defined for n-level inverter v off = v off , ZCMV = ( n − 1) / 2 ( 14)
in Fig. 1 is described as :
and the sum of the average values of VXn (X=A,B,C)
V + VBO + VCO
Vcm = AO (10) defined as F = v An + vBn + vCn is obtained with the
3
following value:
The instantaneous value of Vcm following Fig. 2(a) is
derived as
F = FZCMV = FL + Fe = 3(n − 1) / 2 (15)
(VAn + VBn + VCn − 3(n −1) / 2).Vdc
Vcm = (11) where FL and Fe are determined respectively as:
3
The combinations of (VAO ,VBO ,VCO ) which do not FL = L A + LB + LC (16)
contribute any common-mode voltage, represent the zero Fe = ξ A + ξ B + ξ C ;; 0 ≤ Fe ≤ 3 (17)
CMV vectors in the vector diagram of n-level inverter
which result in zero value of Vcm . The functions F , FL , Fe determine respectively the
total switching voltage, total base voltage and total active
We define f n as
voltage as described in Fig. 2(d).
f n = VAn + VBn + VCn (12)

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 B. Medium Triangle active voltage vector diagram of
the Two-level active voltage Inverter under eliminating
common mode voltage PWM control
In space vector diagram of a multi-level inverter, a
discrete vector can be decomposed into two components as
follows:
G G G
VS = L+ s (18)
G
where L is the pointing vector formed by the three Fig.4: Medium triangle active voltage vector diagrams: a) switching
G
phase base voltages and s is the active vector formed by the states for Fe = 2(FL = 3(n−1) / 2 − 2) and b) switching states for
three phase active voltages in Fig. 2(a). Following (18), any Fe =1(FL = 3(n−1) / 2 −1) .
discrete vector in the space vector diagram of an n-level
G JJG
inverter can be represented by (L,s) . Its worth noting that
the three zero common mode vectors (ZCMV) in the space For space vector diagram with ZCMV of a five-level
G
vector diagram have the same base voltage vector L which inverter as shown in Fig. 3, 24 equilateral medium triangles
tip locates at center of the equilateral medium triangle defined by three zero common mode vectors can be found:
formed by tips of the three vectors. twelve triangles, which corresponding base vectors meet the
A simple carrier based ZCMV PWM control method is condition FL = FL1 = 4 , confine the light area; the others,
established under the consideration of (6), (13) for satisfy FL = FL2 = 5 , cover the shaded area.
instantaneous voltage modeling in Fig. 2(a) and (7), (8),
(14)-(17) for average voltage modeling in Fig. 2(b), 2(c), The value of the base voltage and the active voltage can
2(d). It has been shown that the function FL in (16) is be deduced from (20), (21):
determined by the base voltage vector which tip is located at ⎧⎪ Int (vXn ) if v Xn < n − 1
the center of the active triangle and the function Fe is LX = ⎨ ; 0 ≤ LX ≤ n − 2 (20)
⎩⎪ n − 2 if v Xn = n − 1
related to the active voltage vectors of the medium triangle
vector diagram as illustrated in Fig. 4. A general analysis (ξ A , ξB , ξC ) = (v An − LA , vBn − LB , vCn − LC ) (21)
has been shown that, for an n-level inverter, the ZCMV
condition confines the possible values of FL , Fe to those The values v Xn under the conditions of ZCMV are
expressed as: defined by (8) and (14) and Int (v Xn ) denotes a function
FL = 3(n −1) / 2 − 2; Fe = 2 (a) that returns a nearest lower integer value of v Xn .
FL = 3(n −1) / 2 −1; Fe = 1 (b) (19)
FL = 3(n −1) / 2 ; Fe = 0 (c) C. ZCMV PWM patterns and ZCMV PWM control
algorithm
The proposed CMV elimination PWM in multi-level
inverters can be obtained by solving (19). With exception of Based on the medium triangle active vector diagrams
case (19.c) related to several pivot vectors, the two generalized for an n-level inverter as described in Fig. 4, the
remaining available values of FL , Fe are further limited to PWM switching state sequence of the active voltage vectors
(19.a), (19.b). in the ZCMV PWM control can be grouped into two PWM
patterns related to the Fe values.
In case FL = 3(n − 1) / 2 − 2 and Fe = 2 (19.a), the
In case Fe = 1 , the active switching state sequence
condition of Fe = 2 will be realized with three active
forms PWM pattern 1 as described in Fig. 5(a). Two from
switching states as (1,1,0), (0,1,1) and (1,0,1) in the active
three ABC phases are mapped to s1 and s2 that the s1 -level
voltage hexagonal diagram as illustrated in Fig. 4(a).
varies as 0-1-0 in a sampling period and the s2 -level
Similar to the previous case, in case
varies as 1-0-1 in a sampling time period. All of them have
FL = 3(n −1) / 2 −1 and Fe = 1 (19.b), the condition of a single pulse waveform. The remaining phase is mapped to
Fe = 1 will be realized with three active switching states as the d-phase that the d-level will vary as 0-1-0-1-0 and has a
double pulse waveform in a sampling time period.
(1,0,0), (0,1,0) and (0,0,1) in the active voltage hexagonal
diagram as in Fig. 4(b). In case Fe = 2 , the active switching state sequence
corresponds to PWM pattern 2 as described in Fig. 5(b).
Two from ABC phases are mapped to s1 and s2 that the s1 -

222
level varies as 0-1-0 in a sampling period and the s2 -level where ton and toff represent the turn-on and turn-off
varies as 1-0-1 in a sampling time period. All of them have time of the switching devices respectively, and fiA (θ) is the
a single pulse waveform. The remaining phase is mapped to switching current function which instantaneous value is
the d-phase that the d-level will vary as 1-0-1-0-1 and has a defined as product of the number of commutations on A-
double pulse waveform in a sampling time period. phase in a switching period and the absolute value of its
1 1
corresponding current i A (θ )
1 − ξs 2 ξ s1
ξ s1 1 − ξs 2 f iA (θ ) = k i A (θ ) (23)

The switching loss function (SLF) is defined as:

0 0
Pswave
SLF = (24)
s1 0 0 1 1 0 0 s1 0 1 1 1 1 0
P0
s2 s2 1 1 0 0 1 1
where P0 is the maximum value of the switching loss
1 0 0 1

d d
attainable for the defined load currents.
0 1 0 0 1 0 1 0 1 1 0 1

T1 T2 T3 T2 T1 T1 T2 T3 T2 T1
2 2 2 2
When using the proposed PWM method with two
2 2 2 2

a) Pattern I b) Pattern II
Fe = ξ s1 + ξ s 2 + ξ d = 1 Fe = ξ s1 + ξ s 2 + ξ d = 2 standardized PWM patterns in Fig. 5, the distribution of
commutations in a switching period is unequal on each
Fig. 5: Two Standardized virtual PWM patterns from three-nearest
vectors of zero common mode voltage phase. It can be seen that the d-sequence contains a double
number of commutations compared to the other s1 ,s2 -
Table I:
sequences. The factor k is thus determined as follows:
Possible Mapping functions and modulating signals determination
⎧
⎪2 if A → d
A→d A→d A → s1 A → s2 A → s1 A → s2 k = ⎪⎨ (25)
⎪
B → s1 B → s2 B→d B→d B → s2 B → s1 ⎩1 else
⎪
⎪
C → s2 C → s1 C → s2 C → s1 C→d C→d
By substituting (25) into (23), it can be concluded that
ξs1 = ξB ξs1 = ξC ξs1 = ξ A ξs1 = ξC ξs1 = ξ A ξs1 = ξ B fiA (θ) equals double the absolute value of the
ξs2 = ξC ξs2 = ξ B ξs2 = ξC ξs2 = ξ A ξs2 = ξ B ξs2 = ξA corresponding phase current in the interval that the A-phase
is mapped into the d-sequence (A → d) and equals the
For three phase outputs with the use of the two Patterns absolute value of the current in other cases.
in Fig. 5, six possible Mapping functions are listed in Table
I. Different Mapping functions result in different three phase The Mapping function, as described in Table I, can be
active switching sequences. For example, when using the altered between six possible cases so that an arbitrary output
Mapping function (A → d ,B → s1,C → s2 ) for the Pattern I, phase can be mapped into the d-sequence. If all the selected
Mapping functions satisfy the constraint that only output
three phases A,B,C will be mapped to s1,s2 ,d - phase of minimum absolute current is mapped to the d-
sequence respectively. Hence the three-phase active sequence, the switching current function described in (23)
switching sequence expressed as (s A,s B ,sC ) is will always be obtained with minimized value. Hereby, the
switching loss function in (24) can be optimized. Based on
(0,0,1) → (1,0,0) → (0,1,0) → (1,0,0) → (0,0,1). If the mapping this idea, a current-based Mapping PWM algorithm which
function, in another example, is selected as optimizes the switching loss is proposed.
(A → s1,B → s2 ,C → d ) , the three-phase active switching i A i B iC

sequence will be (0,1,0) → (0,0,1) → (1,0,0) → (0,0,1) k X = iX ; X = A, B,C

→ (0,1,0)
mx = max( k A , k B , k C )
md = mid( k A , k B , k C )

III. SWITCHING LOSSES OPTIMIZATION mn = min( k A , k B , k C )

The switching losses linearly increase with the k A = mn kB > k C A → d, B → s1,C → s 2

y
magnitude of the commutating phase current. The average y
n
n A → d,B → s 2 ,C → s1
value of the local (per carrier cycle) switching loss over the
A → s1, B → d,C → s 2
fundamental (for instance, for the phase A) can be k B = mn
y
kA > kC

n
y Selected Mapping
function

calculated as [14]: n
A → s 2 , B → d,C → s1

kA > kB A → s1, B → s2 ,C → d
kC = mn y
2π
1 Vdc (t on + t off ) n A → s2 ,B → s1 ,C → d

Pswave =
2π 2Ts ∫ fiA (θ)d θ (22)
0 Fig.5b- Block diagram of the proposed Current-Based Mapping PWM
algorithm to optimize the switching loss.

223
 is necessary to determine the range of the switching loss
d s1 s1 d s2 s2 d s1 A
function. This can be done by an analysis of a so-called
iABC
s2 s2
s1 d
d
s2
s1
s2
s1
d
d
s1
s2
s1
s2
d
B
C
voltage-based mapping algorithm under different phase
Im
iA i
B
i
C displacement factors. The voltage-based mapping algorithm
Im
can be simply implemented by replacing iX (X = A,B,C)
a) 00

ωt
with the reference output voltages v* X 1(X = A,B,C) as
-Im
inputs of the flow diagram in Fig.5b. mx, md , mn are then,
-Im

0 π/6 π/2 5π/6 7π/6 3π/2 11π/6 13π/6 15π/6

fiA respectively, the maximum, medium and minimum of the
absolute values of v* X 1(X = A,B,C) . The voltage-based
Im
Im
b)
00 ωt mapping algorithm which operation following the
fiB
Im
Im
waveforms of the reference output voltages is illustrated in
Fig. 7(a). Since the rule of switches distribution of the
00 ωt voltage-based mapping PWM is based on information of
fiC
Im
reference voltage (offline), the waveform of fiA (θ) is
Im
c)
changed differently depending on the current phase
00 ωt
displacement angle ϕ . For example, three cases of phase
Fig. 6: Current-based mapping PWM method (a) and switching displacement angle: ϕ= 0 , ϕ = π / 6 , ϕ = π / 2 in Fig. 7(b),
current functions of three phase: (b) fiA (θ) (c) fiB (θ) (d) fiC (θ)
7(c), 7(d) will result in three different waveforms of fiA (θ)
as shown in Fig. 8(a),8(b),8(c).
s2 A
In the proposed Mapping PWM algorithm with
d s1 s1 d s2 d s1
v* X1(X=A,B,C) s2 s2 d s1 s1 d s2 s2 B
s1 d s2 s2 d s1 s1 d C
optimized switching loss, the feedback currents iA,iB ,iC are Vm
v* A1 v* B1 v* C1

utilized as inputs of the flow diagrams kX = iX (X = A,B,C) . a) 0

-Vm
ωt
mx, md , mn are determined, respectively, as the maximum, 0 π/6 π/2 5π/6 7π/6 3π/2 11π/6 13π/6 15π/6
iA(ϕ=0)
medium and minimum of the absolute values of iA,iB ,iC . Im

The Mapping function is chosen so that the phase with b) 0 ωt

minimum absolute current is mapped to the d-sequence. The -Im
ϕ=0

selected Mapping function is then utilized to complete the iA(ϕ=π/6)

Im

proposed PWM scheme of zero CMV. c) 0 ωt

ϕ=π/6
Figure 6(a) illustrates the operation of the proposed -Im
iA(ϕ=π/2)
current-based mapping method in Fig.5b following the Im

feedback waveforms of the output currents. By using (23), d) 0 ωt

(25), the A-phase switching current function waveform -Im ϕ=π/2

fiA (θ) is derived as illustrated in Fig. 6(b). Since the A-

Fig. 7: Voltage-based mapping PWM method
phase is set to the d-sequence during the interval that its with different current phase displacement b. ϕ = 0 c.
current attains a minimum absolute value, the waveform of ϕ = π / 6 d. ϕ = π / 2
fiA (θ) always confines a minimized Ampere-second area
ωt
regardless of the load displacement factor. Hence the f iA(ϕ = 0)
0 π/6 5π/6 7π/6 11π/6 13π/6

waveform fiA (θ) corresponds to a minimum value PswOpt of a)

ImIm

the switching loss Pswave defined by (22): 0 0 ωt

f iA(ϕ=π/6)

1 Vdc I m (ton + toff )

2Im
2Im

b)
PswOpt = AOpt (26)
Im
Im

4π Ts 0
0 ωt
f iA(ϕ=π/2)

2Im
2Im

Aopt = 8 − 2 3 = 4.5359 c) Im
Im

0 0 ωt
Similarly, the optimized waveforms of the B and C-
phase switching current functions are shown in Fig. 6(c) and Fig. 8: Waveforms of switching current function using voltage-based
6(d) respectively. PWM method a. ϕ = 0 b. ϕ = π / 6 c. ϕ = π / 2

To evaluate the improvement of the switching loss In the case ϕ= 0 , the A-phase output current, as
when using the proposed Current-based Mapping PWM, it illustrated in Fig. 7(b), is in phase with its corresponding

224
reference voltage v*A1 . As can be seen from Fig. 8(a), the
waveform of the A-phase switching current function is
identical to one obtained by using the Current-based
Mapping algorithm in Fig. 6(b). The switching loss Pswave
is thus corresponding to the minimum value PswOpt
expressed in (26). A general evaluation using (22), (23),
(25) has been shown that the switching loss Pswave
increases from its optimum value PswOpt to its maximum
value P0 attainable for the defined load current if the phase
displacement ϕ increases from 0 to π / 2 . As can be seen
from Fig. 7(d), at ϕ = π / 2 , the A-phase is set to the d-
sequence of double commutations during the interval its
current attains maximum absolute value. P0 can be
computed as:
V I m (ton + toff )
P0 = 1 dc AMax ; AMax = 6
2π 2Ts
As a result, the SLF characteristics of the Voltage-based
mapping algorithm along with the Current-based mapping
algorithm (optimizing algorithm) analyzed in the region
0≤ϕ≤π are illustrated in Fig. 9.
SLF(ϕ)
1 (1)
0.9
(2)
0.756
0
0 π /6 π /3 π /2 2π/3 5π/6
ϕ
Fig. 9: Characteristic of Switching Loss Function SLF(ϕ) of the
Voltage-based mapping PWM method (1) and Optimizing method (2)
By applying the optimizing algorithm at the power
factor of 0.85, in comparison with the voltage-based
mapping PWM algorithm, the switching loss function
decreases by about 10%. For PF<0.55, the reduction can be
more than 20%. Figure 9 shows that the switching loss
function can be reduced by 25% at the phase displacement
of 90 degrees. Since the number of commutations in a
switching period of the proposed PWM method, as
compared to [12,15], is reduce to two third, the switching
loss function can be then reduced by 43% compared to the
two mentioned methods.
IV. EXPERIMENTAL VERIFICATION
In order to verify the validation of the proposed PWM
strategy, experimental results were obtained by applying the
proposed schemes to a five-level cascaded inverter. Each H-
Bridge is made up of IGBTs using FGL-60N100-BNTD.
The DC voltage on each H-Bridge is held constant at 100V.
The rating of each DC-link capacitor used for the
experimental setup is 4700μF The load is R-L load which,
in each experiment, can be set at different value to create
different phase displacement factors . The fundamental
frequency f o is selected as 50 Hz. The frequency of the
triangle carrier waveform f s is 2.31 kHz. In online
algorithm for switching loss optimization, two additional
Hall sensors LA55-P are used to measure two output
currents. Since the three phase load is balanced, the third
current can be deduced from the two measured currents.
For comparison, the conventional sinusoidal PWM method
is also realized.
Figure 10 depicts the obtained waveforms and FFT
analysis of phase voltage vAN (N is the load neutral), phase
current iA and CMV vNO of the conventional sinusoidal
PWM method. As a comparison, the same quantities are
given in Fig. 11 for the proposed PWM method with CMV
elimination and switching loss optimization. There are
different of levels of line-to-line voltage when the inverter
operates with and without CMV elimination scheme, as
shown in Fig. 10(a) and Fig. 11(a). Also, it can be noted
(27) from the FFT analysis in Fig. 10(d), 10(e) and Fig. 11(d),
11(e) that the conventional method yields better results of
output voltage and current THD. These difference can be
explained based on the limited number of switching states
under condition of zero CMV compared to the conventional
PWM method.
π
Fig. 10: Experimental results Fig. 11: Experimental results
when using conventional Sinusoidal when using proposed PWM method
PWM method at modulation index with CMV elimination (Current-
m = 0.866 based Mapping), at modulation
index m = 0.866
iA
Fig. 12: Experimental results when using proposed PWM method with
CMV elimination (Voltage-Based Mapping), at modulation index
m = 0.866 ( f o = 50 Hz , R = 40Ω, L = 180mH )
Because of this, a greater distance among the closet
active switching states in the vector diagram causes a
greater harmonic distortion. Figure 10(c), 10(f) and Figure
11(c), 11(f) illustrate the CMV waveform and its FFT
analysis in the two PWM methods. The CMV which is
represented with large magnitude in Fig. 10(c) has been
225
eliminated in Fig. 11(c). The existence of switching spikes
in the CMV waveform in Fig. 11(c) are on account of the
dead-time intervals during switching transitions.
iA
Fig. 13: Experimental results when using proposed PWM method
with CMV elimination (Switching loss optimizing Mapping), at modulation
index m = 0.866 ( f o = 50 Hz , R = 40Ω, L = 180mH )
Experimental results including waveforms of three phase
currents iX (X = A, B, C ) and A-phase output voltage vAN
are shown in Fig. 12 for voltage-based mapping algorithm
and in Fig. 13 for switching loss optimizing mapping
algorithm. In Fig. 12, the load is R = 40Ω, L = 180mH which
corresponds to ϕ = 55 degree. A double commutation on
A-phase doesn’t occur around its zero current value. By
using the same experiment configuration in Fig. 12 and
applying the current-based mapping algorithm (switching
loss optimizing algorithm), the experimental results are
obtained as depicted in Fig.13. A double commutations on
A-phase, as observed from Fig. 13, are confined to
intervals of minimum absolute value of its current.
V. CONCLUSION
In this paper, a novel PWM strategy to eliminate
common mode voltage for multi-level inverter using three
zero common mode vectors has been proposed. By using a
proper coordinate transformation, modulation of a n-level
inverter with common mode voltage elimination is
simplified to that of a active two level inverter with three
available switching states. Based on a general analysis of a
n-level inverter, two generalized virtual patterns are
proposed to cover the whole space vector diagram. The two
proposed patterns result in switching sequences with a
minimum number of commutations among those in which
each switching state is symmetrically distributed. Using the
optimizing PWM algorithm, the local reduction of switching
loss can be up to 25% as compared to non-optimized
algorithms.
ACKNOWLEDGMENT
This research is funded by Vietnam National Foundation for
Science and Technology Development (NAFOSTED) under
grant number 103.01-2011.67 and partly funded by
Minister of Science and Technology under grant project
number KC.03.17/11-15
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