Fast-Processing Modulation Strategy for the Neutral-Point-Clamped Converter with
Total Elimination of the Low-Frequency Voltage Oscillations in the Neutral Point
J. Pou, P. Rodríguez, V. Sala, J. Zaragoza,
Power Quality and Renewable Energy (QuPER)
Research Group
Departments of Electronic and Electrical Engineering
Technical University of Catalonia
Catalonia, SPAIN
pou@eel.upc.edu
Abstract – This paper presents a novel modulation strategy for
the neutral-point-clamped converter. This strategy overcomes
one of the main problems of this converter, which is the low-
frequency voltage oscillation that appears in the neutral point
under some operating conditions. The proposed modulation
strategy can completely remove this oscillation for all the
operating points and for any kind of loads, even unbalanced and
nonlinear loads. The algorithm is based on a carrier-based PWM.
Nevertheless, it can generate the maximum output voltage
amplitudes attainable under linear modulation, such as space-
vector modulation. Furthermore, this technique can be
implemented with a very simple algorithm, and hence can be
processed very quickly. A control loop for balancing the voltages
on the dc-link capacitors is also proposed. This balancing strategy
is designed so that it does not increase the switching frequencies
of the devices when it is applied to the converter. The proposed
modulation technique is verified by simulation and experiment.
I. INTRODUCTION
Multilevel converters can provide more than two voltage
levels at the outputs. Consequently, they can generate better
output voltage spectra than the classical two-level converter.
Another advantage of multilevel converters is that their
devices only have to stand a portion of the maximum voltage
generated at the outputs. These two features make the use of
multilevel converters practical for high-power applications, in
which high voltages must be handled. Moreover, the improved
voltage spectra allows for reduction of the switching
frequencies of the devices. This is crucial in high-power
applications, not only because of the potential for reducing
switching losses, but also because of the intrinsic length of the
ton and toff switching times of these devices.
The multilevel converter topology most extensively applied
at present is the neutral-point-clamped (NPC) converter [1],
which is a three-level converter (Fig. 1). For proper operation
of this topology, the neutral-point (NP) voltage must be kept at
one half of the dc-link voltage. If there is no external control
for the voltages on the capacitors, the modulation strategy
must be designed to achieve voltage balancing between the
capacitors. A great deal of research has been focused on this
field [2]-[5]. Although the averaged NP voltage can be
controlled, a low-frequency NP voltage oscillation appears
under some operating conditions. This is a significant
drawback of this converter, since the dc-link capacitors and the
0-7803-9252-3/05/$20.00 ©2005 IEEE
R. Burgos, and D. Boroyevich
Center for Power Electronics Systems (CPES)
Department of Electrical and Computer Engineering
Virginia Polytechnic Institute and State University
(Virginia Tech)
Virgina, USA
1
sa4 sb4 sc4
vC2
C
sa3 sb3 sc3 ia a
i0
0 ib b
Vdc
(NP) ic
Load
c
sa2 sb2 sc2
C
vC1
sa1 sb1 sc1
-1
Fig. 1. Three-level diode-clamped converter (or NPC converter).
devices of the converter must be designed to stand this
oscillation. Furthermore, if the modulation algorithm does not
take into account this NP voltage oscillation, the output
voltages will contain low-frequency distortion. The
feedforward PWM [6] can completely avoid such voltage
distortion at the output; however, the low-frequency NP
voltage oscillation still remains.
In [7], an interesting modulation strategy able to cancel low-
frequency voltage oscillation in the NP is proposed. The
analysis is based on the use of virtual vectors in space-vector
modulation (SVM). Nevertheless, the algorithm is finally
implemented using a carrier-based PWM. With this approach,
however, one has to deal with angles and trigonometric
functions, which complicates its application. While the
algorithm can achieve an averaged NP current equal to zero,
since the voltages on the capacitors are not naturally balanced,
they preserve any original imbalance from the start up of the
system. Furthermore, since the voltages are not regulated, they
may deviate without control.
The modulation algorithm proposed in this paper can also
enable the locally-averaged NP current to be equal to zero.
However, the algorithm is based on a very simple treatment of
the modulation signals, which is spectacularly easy to
implement, even in a low-feature microprocessor. This
strategy makes use of two carrier waveforms, just as in a
standard SPWM. This paper also proposes an efficient
voltage-balancing compensator that neither increases the
switching frequencies of the devices nor distorts the output
voltages. The paper ends by showing simulation and
experimental results and drawing some conclusions.
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 II. BASIS OF THE METHOD p p
vcarrier vcarrier
1 vip 1
In SPWM, each phase is controlled by one modulation
signal. In some approaches (e. g. [8],[9]), a zero-sequence
signal is added to provide NP current control, which vi vip
consequently helps to achieve voltage balance. However, the
low-frequency NP voltage oscillations cannot be completely vi
removed by means of these strategies. The modulation
technique proposed here is based on the use of two modulation n
vcarrier n
vcarrier
signals for each phase of the converter. The process to obtain 0 0
these signals is described below.
First, the original modulation signals are modified to obtain
vin vin
SVM patterns in order to achieve the maximum range for
linear operation mode, as follows:
va ' = va − v0

vb ' = vb − v0 , and (1)
v ' = v − v ,
 c c 0 -1 -1
max(va , vb , vc ) + min(va , vb , vc )
where v0 = . 0 1
2 0 1
The two modified modulation signals for each phase will be Time/Ts Time/Ts
obtained from these signals, which must accomplish: (a) (b)
va ' = vap + van , Fig. 2. Two possible situations for the calculation of the duty cycle di0:
 +1
vb ' = vbp + vbn , and (2) (a) vin+1 < vip , and (b) vin+1 > vip , for vin = vin + 1 .
v ' = v + v ,
 c cp cn

where vip ≥ 0 and vin ≤ 0 , with i={a, b, c}. The signals with i 0 = d a 0 i a + d b 0 ib + d c 0 i c , (6)
the subscript ‘p’ will only cross the upper carrier, in which d i 0 = si 0 for i={a, b, c}. Assuming that the
p
vcarrier ∈ [0, 1] , and the signals with the subscript ‘n’ will only frequency of the carriers is much higher than the frequency of
n
cross the lower one, vcarrier [− 1, 0] . In Section IV, the process the modulation signals, the duty cycles can be expressed as
follows:
that is implemented when comparing the modulation signals
with the carriers is explained. It is anticipated that the d i 0 = vin+1 − vip where vin+1 = vin + 1 . (7)
connection to the NP (‘0’ level) is produced when: Relationship (7) is obtained from (3) and using basic
 vip > vcarrier
p n
and vin < vcarrier , or trigonometry in Fig. 2. As a result:
 p n
(3) +1
i0 = van +1
− vap ia + vbn +1
− vbp ib + vcn − vcp ic . (8)
vip ≤ vcarrier and vin ≥ vcarrier .
The two inner transistors of a phase leg of the converter If:
(Fig. 1) are in the on state when the corresponding NP control van − vap = vbn − vbp = vcn − vcp = v x , or (9)
variable si0 ∈{0, 1}, for i={a, b, c}, is activated. In other +1
van +1
− vap = vbn +1
− vbp = vcn − vcp = 1 + v x ,
words, when a variable si0 takes the unity value, the
subsequent output phase is connected to the NP; otherwise it then the averaged NP current would be:
takes the value of zero. When one phase leg is clamped to the i0 = 1 + v x (ia + ib + ic ) (10)
NP, its output current is injected to this point. Therefore, the Since the neutral of the load is open (Fig. 1) or is just a
current i0 can be expressed as follows: triangle-connected load, there is not a zero-sequence of
i0 = s a 0ia + sb 0ib + sc 0ic . (4) current. Subsequently, the sum of the output currents is always
In order to preserve voltage balance, the locally-averaged zero ( ia + ib + ic = 0 ); hence, i0 becomes zero.
NP current must be zero. Therefore, it is necessary to operate In conclusion, the problem of maintaining the locally-
with the averaged NP current instead of the instantaneous averaged voltages on the dc-link capacitors constant is reduced
current. The averaged NP current is obtained by using the to find a proper value for vx. An infinite number of solutions
moving average operator: can be found; however, one especially interesting solution can
t achieve minimum switching frequencies in the devices of the
∫
1
x (t ) = x(τ )dτ , (5) converter. This solution is found by forcing the variables vip
Ts t −Ts and vin to be zero for the maximum time possible, since when
where Ts is the sampling or switching period. Applying this these signals are zero some of the transistors do not switch
operator to (4), one obtains the following: (none of the modulation signals cross a carrier signal).

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 1.5
Regarding this restriction and relationships (1), (2) and (9), the
va vb vc
following solution is obtained:
1
max(va , vb , vc ) − min(va , vb , vc )
vx = − . (11)
2 0.5

The new modulation signals would be:

 vi − min(va , vb , vc ) 0

vip = and
 2 for i = {a, b, c}. (12)
v − max(va , vb , vc ) -0.5
 vin = i ,
 2
-1
The algorithm can be easily implemented using the scheme
shown in Fig. 3. -1.5
0 π/3 2π/3 π 4π/3 5π/3 2π
Under the assumption of sinusoidal modulation signals,
Angle
such that:
(a)
 v a = m SPWM cos ω t ,

vb = m SPWM cos (ω t − 2π / 3), and
1.5
(13)
v = m
 c SPWM cos (ω t + 2π / 3), 1
vap
the solution for vap is:
0.5
- for 0 ≤ ω t ≤ 2π 3 ,
v ap = (v a − v c ) 2 = ( 3 2) m SPWM cos(ω t − π 6 ), 0

- for 2π 3 ≤ ω t ≤ 4π 3 , -0.5

vap = 0, (14) van

- for 4π 3 ≤ ω t ≤ 2π ,
v ap = (v a − vb ) 2 = ( 3 2) m
and for van it is:
- for 0 ≤ ω t ≤ π 3 and 5π 3 ≤ ω t ≤ 2π ,
van = 0,
- for π 3 ≤ ω t ≤ π ,
v an = (v a − vb ) 2 = ( 3 2) m SPWM
- for π ≤ ω t ≤ 5π 3 ,
v an = (v a − vc ) 2 = ( 3 2) m
SPWM cos(ω t + π 6 ),
cos(ω t + π 6 ), and
SPWM cos(ω t − π 6 ).
-1
-1.5
0 π/3 2π/3 π 4π/3 5π/3 2π
Angle
(b)
Fig. 4. Example for sinusoidal modulation signals:
(a) original signals and (b) modified signal for phase a.
(15) Fig. 4 shows the waveforms for this example. The amplitude
of the modulation signals (mSPWM), which is also defined as the
modulation index, is adopted to be m SPWM = 2 3 = 1.1547 .
The modified modulation signals for phase b have the same
shape but with a 2π/3 phase-shift delay, and for phase c the
modulation signals have a 2π/3 phase-shift advancement.
Note that the modified modulation signals are within the
range [-1,1], which means that the converter would operate
under linear modulation. Therefore, this example shows that
the maximum modulation index achievable for linear
modulation mode (mSPWM=1.1547) can be achieved by this
method. This maximum value is also obtained by space-
vector modulation or by other carrier-based PWM strategies
that make use of a proper zero-sequence signal. However, the
method proposed here has the important advantage of
maintaining equal voltages on the dc-link capacitors
(disregarding switching ripples).

III. COMPENSATION FOR IMBALANCES

Using the proposed modulation technique, the locally-

averaged NP current is kept to zero, and consequently the
Fig. 3. Scheme for the generation of vip and vin from vi (i={a,b,c}). locally-averaged voltages on the dc-link capacitors are

1056
constant. However, this does not imply that these voltages
are equal. In fact, in theory, if the initial voltages on the
capacitors were different, this modulation strategy would
tend to preserve imbalance because the locally-averaged NP
current is zero. In practice, the situation is even worse since
dead times, different values and behavior of the components,
etc., can make the voltages drift slowly and without control.
Thus, some compensation for voltage imbalances must be
provided.
A control method for voltage compensation can be simply
shifting the modified modulation signals in accordance to the
sign of the voltage error (∆vC>0). An inconvenience of this
method is that when the signals are shifted, they do not
preserve any interval clamped to zero. As a consequence, the
switching frequencies of the devices increase. Furthermore,
the sign of the power flux in the system needs to be known in
order to provide a proper shift to the signals. The balancing
strategy proposed in this paper avoids increasing the
switching frequencies of the devices. Moreover, it does not
need to detect the direction of the power flux in the system.
This technique is explained below.
Regarding vap and van in Fig. 4(b), none of the signals are
clamped to zero throughout the intervals π 3 ≤ ω t ≤ 2π 3
and 4π 3 ≤ ω t ≤ 5π 3 . Therefore, the modified modulation
signals of phase a can be shifted up or down during these
intervals without increasing the switching frequencies of the
devices. Similarly, there are other intervals for phases b and
c in which none of the associated modulation signals are
clamped to zero, and therefore can be shifted. Although this
strategy preserves the switching frequency of the devices
when the compensator is activated, a significant drawback is
the extremely slow voltage-balancing dynamics of the
system. This occurs because only the modified modulation
signals associated to one phase are shifted at any time. In
order to improve the balancing dynamics, the sign of the
output currents should be sensed. Furthermore, relationship
(2) must be preserved in order to avoid distortion in the
output voltages during the compensation. This occurs if the
offset applied to the modified modulations signals have
opposite signs. The offset applied to vip is:
vi _ off = − k p ∆vC ⋅ sign(∆vC ii ) ⋅ sign(vip − vin − 1) . (17)
The absolute value of the voltage imbalance is multiplied
by variable kp. The term sign(∆vC·ii) defines a sign for the
compensation. Nevertheless, the final sign of the offset
depends on sign(vip−vin−1) or sign(vip−v’in), in accordance
with the two possible cases shown in Fig. 2.
IV. CONTROL SIGNALS FOR THE TRANSISTORS
The output level activated at each phase of the converter is
defined by a comparison of the modified modulation signals
with the carriers, as follows:
p
If vip > vcarrier then xip = 1, otherwise xip = 0
n 
If vin < vcarrier then xin = 1, otherwise xin = 0 
x i = x ip − x in , i ∈ {a, b, c}. (18)
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These variables can take three values, xi ∈ {− 1, 0, 1} ,
which are the possible output levels for each phase. In order
to obtain the control functions of the transistors, the
following relationships are needed:
s i 4 = 1 if x i = 1,
 s = 1 if x i = 1 or x i = 0,
 i3
 (19)
 s i 2 = 1 if x i = 0 or x i = −1, and
 s i1 = 1 if x i = −1.
If the respective above conditions are not met, then
variables si1, si2, si3, and si4 are correspondingly zero. These
variables are associated to the on and off states of the
transistors (on=‘1’ and off=‘0’), where two of them are
always on for each of the valid 27 electrical states of this
converter.
V. EXPERIMENTAL RESULTS
The proposed modulation technique has been verified by
simulation and experiment. The values of the dc-link voltage
and the capacitors are Vdc=96 V and C=1100 µF,
respectively. The converter operates over an R-L Wye-
connected load with L= 50 mH and R= 10 Ω. The frequency
of the carriers is 5 kHz and the modulation index mSPWM=0.9
in all the results.
Fig. 5(a) and 5(b) show the results obtained from the
application of a standard SPWM. In Fig. 5(a), a line-to-line
output voltage (vab) is illustrated, and in Fig. 5(b) the
variables shown are the voltages on the dc-link capacitors
(vC1 and vC2) together with two output currents (ia and ib).
Note that there are significant low-frequency voltage
oscillations on the dc-link capacitors. The modulation
frequency has been selected to be very low in this example
(fm=20 Hz) in order to emphasize this effect. Fig. 5(c) and
Fig. 5(d) show the same results when the proposed
modulation technique is applied. In this case, the voltages on
the dc-link capacitors do not contain any low-frequency
oscillation, but only high-frequency ripples related to the
switching frequency. Note, however, that the switching
frequencies of the devices increase compared to the former
case, since there are intervals in which the line-to-line
voltages commutate among three states of the converter
instead of two. This is produced when neither of the two
corresponding modified modulation signals is clamped to
zero.
In Fig. 6, the modulation frequency in this example is f=80
Hz. Observe that the voltages on the dc-link capacitors
become equal very quickly.
Fig. 7 shows a simulation example in which a set of
second and fourth current harmonics have been added to the
load currents. These harmonics are very harmful for the
standard SPWM strategy, since they may introduce
instability to the NP voltage, which is also a problem when
operating under standard SV-PWM techniques [10].
However, when the proposed modulation strategy is applied,
the voltages on the dc-link capacitors do not show any
negative effect and the system is always stable.
 vab vab

(a) (c)

v C1
vC1, vC2

v C2

ia ib ia ib

(b) (d)

Fig. 5. Experimental results:

(a) and (b) for standard SPWM, and (c) and (d) for the proposed modulation strategy.

v C1

v C2

ia ib

Fig. 6. Dynamics of the voltage compensator operating over a linear load.

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(V), (A)
60
vC1
40 vC2 Standard SPWM
becomes unstable
20 ia* 5 ib *5 ic *5
0
-20
0 25 50 75
Time (ms)
Fig. 7. Dynamics of the voltage compensator operating over a nonlinear load
(simulation results).
VI. CONCLUSION
The modulation technique proposed in this work
completely removes the low-frequency voltage oscillations
that appear in the NP of the three-level inverter for some
operating conditions. This technique is also able to attain the
maximum amplitudes achievable under linear modulation, and
its algorithm is very simple and can therefore be quickly
processed in real time. Furthermore, unbalanced and nonlinear
loads no longer produce additional low-frequency voltage
oscillations or instability to the NP. The only drawback of this
strategy is that the switching frequencies of the devices are
one-third higher than a standard SPWM. The method proposed
for voltage compensation performs very well. It is able to
preserve constant switching frequencies on the devices and
introduces no distortion in the output voltages.
This strategy will help to extend the use of the NPC
converter to lower-power applications. One reason for this is
that the modulation algorithm can be straightforwardly
implemented in a very simple microprocessor. Furthermore,
since there is no longer low-frequency voltage oscillation in
the NP, the values of the dc-link capacitors can be
significantly reduced. An interesting application could be the
use of MOSFETs for the synthesis of the NPC converter
operating at about 600 V in the dc bus. Since the NP voltage
never oscillates, the devices would only have to support half
of the dc-link voltage.
VII. ACKNOWLEDGMENT
This work was supported by the Departament
d’Universitats, Recerca i Societat de la Informació of the
Generalitat de Catalunya, under grants 2004BE00105 and
2004BE00060, and by the Ministerio de Ciencia y
Tecnologia of Spain under Project ENE2004-07881-C03-02.
This work made use of Engineering Research Center
Shared Facilities supported by the National Science
Foundation under NSF Award Number EEC-9731677 and
the CPES industry Partnership Program. Any opinions,
findings and conclusions or recommendations expressed in
this material are those of the authors and do not necessarily
reflect those of the National Science Foundation.
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