Analog Integr Circ Sig Process
DOI 10.1007/s10470-011-9717-3
Design and implementation of PFM mode high efficiency boost
regulator
Khondker Zakir Ahmed • Syed Mustafa Khelat Bari
Didar Islam • A. B. M. Harun-ur Rashid
Received: 13 September 2010 / Revised: 11 July 2011 / Accepted: 13 July 2011
Ó Springer Science+Business Media, LLC 2011
Abstract This paper presents the design and implemen-
tation of a low voltage DC–DC asynchronous boost regu-
lator that works in PFM (pulse frequency modulation)
mode. The booster is designed to supply low load condition
of up to 20 mA with high efficiency. The total bias current
of the chip is only 5 lA when operating with 1 mA load
and the number goes to maximum of 18 lA with maximum
load condition of 20 mA. The ultra low bias current enables
the chip to maximize its efficiency in the entire load range.
The chip features on-chip over current protection scheme
and thermal protection scheme. The boost regulator is
implemented in 0.5 lm BiCMOS process technology. The
maximum measured efficiency of the fabricated chip is
86%.
Keywords DC–DC boost regulator  PFM mode boost
regulator  Low current boost regulator  High efficiency
K. Z. Ahmed (&)
Department of Electrical and Electronic Engineering,
East West University, Dhaka, Bangladesh
e-mail: zakir.ak@gmail.com
S. M. K. Bari
Department of Electrical and Electronic Engineering, American
International University—Bangladesh, Dhaka, Bangladesh
e-mail: mustafa.ryadh@gmail.com
D. Islam
Power IC Ltd., Dhaka, Bangladesh
e-mail: didar@picsemi.com
A. B. M. H. Rashid
Department of Electrical and Electronic Engineering,
Bangladesh University of Engineering and Technology,
Dhaka, Bangladesh
e-mail: abmhrashid@eee.buet.ac.bd
•
boost regulator  Inductive boost regulator  On-chip
current limit protection  On-chip thermal protection
1 Introduction
With the proliferation of mobile handheld devices comes
the increasing demand of higher efficiency voltage regu-
lator to maximize the operating/standby time for equip-
ments. The power managements ICs (PMIC) used in these
devices are thus required to be of higher efficiency. For
most of the battery operated devices the required voltage
for the analog circuits are higher than the battery terminal
voltage, which is why the presence of boost regulators are
so common in almost all portable devices. PWM (pulse
width modulation) and PFM (pulse frequency modulation)
are two most common topologies used in boost conversion.
PWM mode Boost Regulators operate in fixed frequency
operation and are capable to supply higher load with higher
efficiency. But at lower load condition, due to the constant
switching loss, the efficiency degrades significantly [1–7].
PFM mode Boost Regulators, on the other hand operate in
discontinuous conduction mode (DCM) and hence skip
pulses at light load condition [1, 8]. Pulse skipping helps to
minimize switching loss and thus increase efficiency
especially at lower loads. To take the advantage of both
modes of operations, many commercially available chips
are implemented in a combination of dual modes (PWM
and PFM) [9–12]. Although many high power high effi-
ciency boost converters are implemented [13, 14], the
design complexity and additional cost hinder to adopt these
topologies for very low power and low cost systems. For
design simplicity and low transistor count the PFM topol-
ogy is a convenient choice. Some recent works are reported
on this topology [1, 2, 15]. Specially as reported in [1], a
123

converter is designed with adaptive ON-time (variable as a
function on input voltage). In the adaptive ON-time
topology, the major intention is to keep the inductor peak
current fixed. Since the rate of change of inductor current
varies linearly with input voltage, to keep the peak current
same with increasing input voltage the ON-time has to be
inversely proportional to the value of input voltage. The
basis of designing an adaptable on time is simply to gen-
erate a current that is proportional to input voltage and then
design a current on capacitor delay element that will ulti-
mately be used as the ON-time output. However, the var-
iation of current with input has a problem with degree of
variation. With wide input variation the time generating
current will also be varying widely producing problem with
the multiplication of the current steering circuit. Also if the
current become comparable to the leakage of the transistors
this might produce significant errors in ON-time. Although
these problems can be overcome using high current oper-
ation and larger transistor sizing, the cost paid is the reli-
ability of the additional circuit element and extra current
budget. For high current operation, current budget may be
relaxed in the order of tens of lA, however for low current
operation this is not a very wise choice where the overall
ground current budget is limited to few lA only. The
adjustable ON-Time through inductor peak current control
offers another advantage of eliminating the need of current
limiting circuit. However, in fixed ON-time topology the
burden of adding another block can be minimized by
designing low current fast response comparator. In brief,
although adjustable ON-time has some advantages
Fig. 1 Functional block
diagram of the implemented
boost regulator
123
Analog Integr Circ Sig Process
regarding output voltage ripple and conduction losses due
to higher current peaks and need of current limit circuitry
when compared to fixed ON-time, the simplicity of design
topology makes fixed ON-time topology a better choice in
terms of reliability and easiness of implementation.
This proposed IC is implemented with a fixed ON-time
topology where the time generated is independent of input
voltage which is implemented by simply a current on
capacitor circuitry. Since the ON-time is fixed, the current
steering circuit has no such issue of matching wide range of
current, hence is more reliable compared to adaptive ON-
time generator circuit. The price of increased peak current
is however paid off by designing the power transistor
channel on resistance to as low as possible with the mini-
mized die area. This IC also employs the outcome of the
mathematical analysis of efficiency optimization for PFM
mode boost regulators performed in [15] where it is shown
that single pulse operation has higher efficiency than multi
pulse operation, this paper describes a newly designed and
implemented high efficiency PFM mode boost regulator.
The implemented Boost Regulator consumes only 5 lA of
bias current in low load condition. The chip is designed and
fabricated in 0.5 lm BiCMOS process. Test results from
fabricated chip are presented.
2 Topology and circuit description
The block diagram for the implemented boost regulator is
shown in Fig. 1. The operation of the regulator is mainly
Analog Integr Circ Sig Process
divided into two broad modes, startup operation and reg-
ular operation. The startup mode operation is controlled by
a startup oscillator, startup bias current generator and an
under voltage lockout (UVLO) block and in the regular
operation mode control logic block, precise bias/reference
generator, internal power MOSFET with driver, over
temperature protection (OTP) circuit, fixed frequency TON
generator and low battery detection (LBI/LBO) circuit
perform the major roles. Separate modes of operation are
described below.
2.1 Start up operation
When the chip gets connected to the input with EN pin
turned OFF (voltage level LOW), which is the case of
standby mode output voltage is charged to input level
through external inductor and Schottky diode. This situa-
tion is denoted as shut down condition. During shut down
condition all internal nodes are properly managed to
ground state to ensure zero leakage. When EN pin is made
HIGH, it releases UVLO, start up oscillator, start up bias
current generator and start up current limit circuit blocks to
operate on their own and the chip is now turned ON. The
UVLO block ensures that all other blocks still remain in
shut down mode except these four start up blocks. the start
up oscillator which is a ring type oscillator with a fre-
quency of 100 kHz and a fixed duty cycle of 66%, is
designed with digital counter. The counter counts first 16
pulses of the oscillator and makes sure during these 16
pulses, the output remains zero. This is to make sure that
the start up bias generator block gets enough time to pro-
duce bias current for all start up blocks. After the 16 pulses
are elapsed, the oscillator output is available and is fed to
power transistor driver stage which ultimately start turning
ON and OFF the power transistor. Every time the power
transistor is ON, a current builds up through the inductor
and after the ON time is finished, during OFF time, that
current is boosted in the output capacitor, thus building up
the output voltage at every pulse. During this mode the
output voltage is monitored and only limited by the peak
current that is controlled by the start up current limit circuit
and the duty cycle of the start up oscillator. The output
voltage continues to build up until the voltage reaches the
predefined threshold of 2.0 V and the internal reference
(REF) has reached the desired level. The REF is designed
to reach its desired level at 1.8 V which is guaranteed by
designed in all corners and temperature ranges. The extra
head room is kept for random variation that might occur
due to mismatch or other uncontrolled shifts in process. As
soon as the voltage at output crosses 2.0 V level, the UVLO
signal is released that marks the mode transition of the chip
from start up to regular mode. The release of UVLO
enables the regular mode circuit blocks such as error
amplifiers (EAs) and fixed TON generator and disables the
fixed frequency start up oscillator and other start up circuit
blocks.
During the start up mode, the current limit protection is
critical, since if the peak current is not controlled and
limited the bond wire and internal metal interconnect might
burn. Although the internal current limit threshold is crude
during start up due to the crude start up bias current, the
circuit is so designed as to keep the maximum peak current
level below the allowed threshold. When the UVLO signal
is released, the start up current limit circuit operation is
switched over to the regular mode current limit circuit
whose response time is much faster and the threshold level
is more accurately and tightly controlled.
2.2 Regular operation
During normal operating condition, a portion of the output
voltage is sensed via resistor network at feedback (FB)
node. This sensed voltage is then compared with the pre-
defined REF level by the error amplifier (EA) and the
resulting decision is used to generate the fixed ON time
pulse from the fixed TON oscillator. If the FB is below the
REF voltage the fixed TON oscillator continues to generate
pulses and output voltage continues to charge up pulse by
pulse via the input inductor. When the FB goes above the
predefined REF level, the pulse generation stops and the
controller enters into standby mode. Because of the load
connected at output, the output voltage discharges and
when the FB node goes below REF level, the system
generates another pulse. Thus, the controller generates
pulses whose frequency is set by the load demand. Thus the
chip produces fewer pulse at a certain time interval if the
load demand is lower, and produces more pulse if the load
demand is higher which is the basic topology of PFM
scheme. Below are brief description of major circuit blocks
those are remain active during regular mode of operation.
2.2.1 REF block
The bias/REF generator block is a bandgap REF circuit.
The schematic of bandgap REF generation circuit is shown
in Fig. 2. It supplies bias current to all other blocks and
generates necessary REF voltage for the EA, current limit
protection circuit and LBI/LBO signal driving comparator
circuit. The bias current generator block generates both
proportional to absolute temperature (PTAT) current and
‘VBE on Resistor’ type current for different purposes. The
REF voltage is tightly controlled and varies only by 0.5%
for entire temperature range from -40 to 125°C. To min-
imize the process variation and random variation the core
of the bandgap circuit as well as the current mirrors are
well designed and laid out with common centroid matching
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VDD
PCAS PCAS
B4
B3
B3
REF
B2
PT
Fig. 2 Schematic of bandgap REF circuit featuring the bandgap generation core, OTP and UVLO logic generation sections. The start-up and
PTAT current generation circuitries are omitted for simplicity
topology. In addition to this, there is offset trimming option
which can be achieved through the four trim fuse pads.
2.2.2 TON generator block
The TON generator block is actually an oscillator. Each
pulse of the oscillator is requested by EA. Figure 3 shows
the simplified schematic view of the TGEN circuit. In
regular mode, whenever the FB voltage goes below the
internal REF, EA signal goes high and sends a request to
TGEN circuit. On getting the request, SW1 as shown in
Fig. 3, opens and SW2 closes, enabling the ION to charge
C1 at the same time bypassing IOFF to ground. Initially the
value of V1 is zero and starts ramping up whose value is
fixed by the charging current and the value of the capacitor.
Fig. 3 Simplified schematic view of TGEN circuit
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Analog Integr Circ Sig Process
B4
UVLO
VDD
OTP
STUP
At the moment of charge cycle, the drain voltage V3 is
high since the NMOS M1 is OFF and this HIGH signal
SET’s the flip flop. When the ramping voltage V1 reaches
M1 threshold, this immediately bring the V3 to zero which
in turns finishes the ON time of the oscillator. at the end of
ON time, OFF time begins and is similarly controlled by
SW2, M2 and RESET pin of the flip flop shown in Fig. 3.
Although the scheme of the boost regulator is PFM in
which the OFF time is not actually controlled, yet, the
TGEN circuit produces a fixed TOFF which ensures a
minimum OFF (boost) time in case of heavy load condition
when the regulator is expected to produces multiple con-
secutive pulses. In this particular boost regulator the
designed TGEN circuit produces a free running frequency
of 100 KHz and a maximum of 75% duty cycle. The circuit
too, employs current mirror matching and specially gen-
erated bias current to track the variation of the on-chip
capacitor and thus minimize the variation of the ON time
over temperature and process variation.
2.2.3 Error amplifier
Figure 4 shows the EA schematic. The EA used in this
PFM control scheme is a high speed comparator with
hysteresis. At the core of the amplifier there is P-MOSFET
differential pair with common mode input voltage of 1 V.
Analog Integr Circ Sig Process
VDD
FB
REF
IBIAS
VDD
P-CLAMP
VCAS
Fig. 4 EA schematic. N-clamp and P-clamp networks are for clamping the first stage’s output movement in lower and upper direction,
respectively, to produce faster response time
The EA compares the FB node voltage and internal REF
voltage. If at any time the FB voltage goes below REF
voltage, the output EA goes high. This going HIGH at EA
initiates a TGEN pulse which is elapses after fixed TON
of 7.5 ls. After TON is elapsed the inductor current is
boosted to output capacitor and EA continues to monitor
the output voltage through FB. If the FB voltage is still
below REF after the first pulse, the EA which is still
remaining at HIGH state allows the TGEN to generate
consecutive pulses of TON allowing a minimum boost
time set by TOFF. In this multi pulse case, the TGEN is
acting as a free running oscillator. However, if within
boost phase, the FB goes above REF, EA goes LOW and
disabling the TGEN and the regulator goes to standby
mode. This mode prevail until the FB again comes below
REF and the phenomenon repeats itself. For very light
load, two consecutive pulse may be quite wide apart, as
high as milliseconds and with heavier load the time delay
between pulses decreases.
The EA circuit takes only 0.5 lA bias current and the
response time is 250 nS with ±100 mV overdrive. The
differential pair is laid out in symmetric geometry to
minimize common mode noise and offset.
2.2.4 LBI/ LBO
This chip also comes with the feature of low battery indi-
cation. LBI and LBO pins serve that purpose. The LBI pin
is connected to the input voltage with a resistance divider
and if the input voltage falls below the preset value, LBO
signal goes low, providing a flag for system designers to
VDD
VDD
EA
N-CLAMP
VDD
VSS
use it with LED or other indicator systems. LBO comes
with open drain or floating drain feature.
2.3 Different protection schemes (current limit
and OTP)
Two important protection schemes are embedded in this
chip. One is the over current protection scheme (ILIM) and
other is the thermal protection scheme (thermal shut).
Figure 5 shows the current limit circuitry. The inductor
current is monitored during each ON time when the current
flows through the power N-MOSFET via the resistor con-
nected at the source of the device (not shown in the
schematic). If, at any moment, the sensed voltage (CS) is
more than the predefined internal current limit REF
(PROGV), the ON time is terminated and the inductor
current is forcedly discharged to the output capacitor. Thus
the peak current is monitored and controlled below the
designed over current threshold level. Current limit circuit
also play significant role during start up when the output
voltage builds up and hence current demand is very high.
Low threshold PMOS are used to ensure current limiting
operation even at low voltage starup condition.
Thermal protection scheme provides safety in the event
of over temperature in which case the chip might mal-
function. Thermal overload protection limits the total
power dissipation in the IC. When the junction temperature
exceeds TJ = 145°C, the thermal sensor circuit produces
the shutdown logic and turns off most of the internal cir-
cuitry. The thermal sensor turns the internal circuitry on
again after the ICs junction temperature drops by 15°C.
123

NCAS
EAB
PCAS
IBIAS
PROGV
Cap
PGND
Fig. 5 Current limit protection circuit. Note that PGND node is zero potential node yet separated from VSS to match with differential input for
current sensing (CS). Operation during low voltage startup is achieved by using low-VTH PMOS
The over temperature trigger level is set higher that the
maximum operating temperature range (up to 125°C) so as
not to affect the normal mode of operation. OTP logic
generation circuitry is embedded with bandgap REF block
as shown in Fig. 2.
2.4 Design consideration and trade-off
To improve the efficiency of the converter all the blocks
were designed to work in low quotient current. Bias current
savings are achieved mostly through designing low current
band-gap REF circuit (0.7 lA), low current EA (0.5 lA)
and fixed TON generator (1.2 lA).
The major issues with the low current bandgap REF
block are to achieve stability at low current and to over-
come the delay during start-up. The stability is resolved by
designing compensation network. The start-up delay is
reduced by clamping different important nodes to limit rail-
to-rail movements. Also the variation of the REF voltage
and current are increased those are addressed by increasing
the trim range of the REF voltage and current.
Low quotient current comparator tends to be sluggish
and the response time becomes too high. The issues is
addressed by clamping output nodes and there by reducing
the delay of the response time. The worst case delay
guaranteed by design is 2 ls with the TON time around 10
ls.
The impact of decreasing bias current in current limit
block is an increase in current limit decision making delay
during charging time. The current budget of current limit
123
Analog Integr Circ Sig Process
VDD
AOB
GATE
AOC
ILIM
NCAS
CS
VSS
block is optimized by trading off the maximum allowable
delay and the maximum allowable quotient current. The
proposed converter comes with a current limit circuit that
has a maximum of 10% overshoot of current limit thresh-
old due to delay.
3 Layout consideration
Figure 6 shows the top level layout view of the designed
chip. All the bonding pads are seen in the chip die
boundary. For switching current noise minimization extra
ground pad (PGND pad) is used beside analog ground
(AVSS pad). The power MOSFET switch is seen in the
lower side of the die between SW and PGND pin. Most of
the top left portion is covered by vertical parallel stipes
which are actually resistor segments used in the bandgap
REF generator and other blocks. Smaller pads those are
seen below the top left SHUTB (EN pin in the block dia-
gram, shown in Fig. 1) pad, are actually trim fuses, used
for voltage level trimming. Middle and upper right portions
are used by other blocks namely EA, current limit circuit,
low battery detector circuit and control logic circuits. The
die area is 600 versus 800 lm including the seal ring that
surrounds the whole chip.
3.1 Power transistor
This chip uses a multi fingered N-MOSFET as the power
transistor. The main objective of any power transistor is to
Analog Integr Circ Sig Process
Fig. 6 Layout view of the chip
minimize the loss that might occur due to the capacitance
charging and discharging loss at the gate node and the
resistive loss in the direct current path (drain to source).
While increasing the width decreases the RDSON, it, on the
other hand increases the gate capacitance. The designed
RDSON is set at 1X which optimizes both the resistive loss
and switching capacitance loss. The driver of the power
transistor is specially designed to produce the required gate
capacitance charging current that enables the transistor to
turn ON and turn OFF within 100 ns.
3.2 Analog and power traces
Since this is a switching boost regulator that handles high
switching currents, it is a great concern that the ground
bounce from the power lines do not affect the analog signal
traces or analog block. All blocks in the layout are isolated
by surrounding substrate pick up those ensure high level
isolation from each others noise. Since the switching
blocks are more prone to inject noises, circuit blocks like
TGEN oscillator, power transistor driver block and power
transistor itself are surrounded more carefully than other
blocks to maximize isolation. Also, switching nodes are
usually guided by parallel ground lines on both side and
special care was taken to ensure so that switching nodes do
not cross over any analog voltage REF interconnects.
Other than individual isolation of blocks, the whole die
is isolated by a wide seal ring of 20 lm width. The seal ring
has p-type substrate pickup and metal layers that run all the
die boundary and are connected to signal ground. This is to
ensure that if the chip is used with some other circuits in
the same substrate, noises from other circuits could not
affect the operation of this die.
4 Results and discussions
The designed IC fabricated in 0.5 lm BiCMOS process,
has been thoroughly characterized in bench level testing.
Different functional features and test data are presented
below. Figure 7 shows a start up event with input voltage
of 1.5 V and output load of 20 mA. Around 0.5 mS after
the EN pin is released, the switching starts. The initial
blank time is a forced delay designed by the omitting 16
initial pulses of the start up oscillator to ensure that start up
bias generating block is ready by that time, which is
guaranteed by design. The output voltage (channel 2) starts
to get charged up by the inductor current and after it has
crossed a certain level (2 V), the regular REF voltage and
REF bias current takes over. This mode transition is easily
visible in Fig. 7. The output voltage continues to increase
until it reaches the regulation point (for this case, the
regulation point is set at 3.3 V), after which the Boost
Regulator enters the regular mode of operation. During
start up, the chip has two distinct over current limit levels.
The initial current limit is deliberately set higher during the
coarse start up phase. The regular current limit, which takes
over after the transition to normal mode, is tightly con-
trolled and designed to minimize variation over process
and temperature. During the first phase of start up, the bias
current necessary to drive the current limit block is sup-
plied by the start up crude bias generator. The EA is
deactivated during this phase and output voltage increases
blindly, which is only limited by the duty cycle of the start
Fig. 7 Start up with 20 mA load at input voltage = 1.5 V. Ch-1 SW
pin, Ch-2 VOUT pin, Ch-3 EN pin, Ch-4 inductor current
123
 Analog Integr Circ Sig Process

up oscillator and input voltage. However, the tightly con-

trolled UVLO level (2 V) ensures definite transition to
normal mode of operation when bandgap REF block is
ready and EA takes over the control scheme. Figure 7 show
different signals at different pin. Channel 1 shows the
signal at SW pin, that is the drain of the power n-MOSFET
and is connected to the external inductor and schottky
diode. Channel 2 shows the output voltage. Channel 3 and
channel 4 shows the EN pin and inductor current shape
respectively. The output voltage (channel 2) is found to be
around 1.5 V, even before the EN pin is released from low
to high. This phenomenon is due to the fact that, since the
chip is of asynchronous mode which requires external
Schottky diode, the output is pre-charged to input voltage
no matter whether the chip is operating or not.
Normal mode of operation in DCM is shown in Figs. 8
and 9, with 3 and 12 mA load respectively. In both figures,
channel 1 shows the input voltage, channel 2 shows the SW Fig. 9 Normal operation with 12 mA load. Ch-1 VIN (AC coupled),
pin voltage, channel 3 shows the output voltage and Ch-2 SW pin, Ch-3 VOUT (AC coupled), Ch-4 inductor current
channel 4 shows the inductor current shape. Both input and
output voltages (channel 1 and channel 3, respectively) are
AC coupled. As predicted theoretically from the PFM Ground Current vs Load Current
20
topology, with increasing load the frequency of the pulse
Ground Current (µA)

increases, such is found from the tested characteristics of 15

the chip. In Fig. 8, where output load is 3 mA, two suc-
cessive pulses are nearly 80 ls apart. And with 12 mA 10
load, the pulses are only 20 ls apart as shown in Fig. 9.
The ON time which is fixed is around 7 ls in each case. 5
Figure 10 shows the bias current variation with respect
to load variation. Here, for the full range of load variation, 0
the chip bias current is found to vary from below 4.8 lA to 0.01 0.10 1.00 10.00
around 18 lA. From simulation the bias current is found to Load Current (mA)

Fig. 10 Chip ground current (bias current) variation with output load
current

vary from 4.5 lA to around 15 lA. This slight discrepancy

Fig. 8 Normal mode operation with 3 mA load. Ch-1 VIN (AC
coupled), Ch-2 SW pin, Ch-3 VOUT (AC coupled), Ch-4 inductor
current
arises from the optimistic simulation which results from
not fully considering junction leakage currents those are
present in real life scenario. Bias current increases with the
load current due to the fact the pulse frequency increase
causes additional switching event which produces extra
ground current.
Figure 11 shows the load supply capacity of the boost
regulator. As can be seen, the regulator maintains the
output voltage quite close to regulation level up to 25 mA
load, after which output starts to fall sharply making it
unsuitable for higher load. Throughout the useful load
range, 0–20 mA, the output voltage changes only by 0.3%.
Figure 12 shows the measured efficiency of the chip
with different input voltages over its entire load range. The
measured efficiency is found to be increasing with
increasing input voltage. This finding is expected since the

123
Analog Integr Circ Sig Process

Output Voltage vs Load Current topology and test results from the fabricated chip are pre-
3.4
sented in this paper. The chip is found to operate with a
maximum of 86% efficiency at 10 mA load. The ground
Output Voltage (V)

3.35 current is tested and found to vary from 4.8 to 18 lA which

is in close accordance with the simulation result. This low
bias current enables the chip to operate with higher effi-
3.3
ciency in a wide load range thus making it suitable for low
power systems where efficiency maximization is a key
3.25 factor for increasing stand-by time. The current limit and
0.01 0.10 1.00 10.00
thermal protection schemes are tested and found to produce
Load Current (mA)
desired results. The chip is also tested for various load and
Fig. 11 Output load capacity of designed boost regulator found to be capable of supplying a maximum of 20 mA
load current while keeping the output voltage at regulated
level.
Efficiency vs Load Current
Vin=1.2V Vin=1.5V Vin=3V
95%
90%
References
85%
Efficiency

80%
75%
70%
65%
60%
0.01 0.10 1.00
Load Current (mA)
Fig. 12 Boost regulator efficiency profile with load variation with 1.5
V input voltage
chip operates at fixed TON mode, with increased input
voltage, peak inductor current is higher compared to lower
input voltage and hence at each boost cycle, more charge is
transferred to output capacitor which results fewer switching
pulses. The peak efficiency values found are 89, 86 and 86%
for input voltages 3.0, 1.5 and 1.2 V respectively. Below the
load current of 100 lA, the efficiency falls significantly
because the ground current becomes comparable with the
load current. the efficiency is found to vary very little over
the range of 1–20 mA for all input voltage ranges.
The measured efficiency of the proposed converted shows
higher value with higher input voltage as opposed to the
adaptive ON-time topology [1] which shows that efficiency
decreases with higher input voltage. This increment of effi-
ciency establishes that fact that through the minimization of
power transistor channel ON-resistance (RDSON) the trade off
of increasing the peak current is achievable.
5 Conclusion
A PFM mode ultra low bias current DC-DC boost regulator
is designed and experimentally validated with an IC fab-
ricated in 0.5 lm BiCMOS process technology. Design
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Khondker Zakir Ahmed has
completed his B.Sc. in Electri-
cal and Electronic Engineering
from Bangladesh University of
Engineering and Technology
(BUET) in 2004. He is serving
as Senior Lecturer in the
Department of Electrical and
Electronic Engineering, East
West University, Dhaka, Ban-
gladesh since January 2010.
Before joining East West Uni-
versity has served Power IC
Ltd., a fab-less IC design com-
pany where he worked as Senior
IC Design Engineer and IC Testing and Characterization Supervisor
from 2005 to 2010. He has designed and supervised several switching
boost regulator IC projects including WLED driver, low voltage
booster and ultra low current boost regulators. His research interests
include integrated switching regulator, analog circuits, nano-scale
ultra low power circuits and single electron transistor.
Syed Mustafa Khelat Bari has
completed his B.Sc. and M.Sc.
in Electrical and Electronic
Engineering both from Bangla-
desh University of Engineering
and Technology (BUET), in
2004 and 2008 respectively. He
has started his career as Analog
IC Designer in Power IC Ltd.—
a fab-less Semiconductor Com-
pany in Dhaka, Bangladesh. He
has worked as Designer and
Design Team Leader in Power
IC Ltd. from March 2004 to
December 2010 and designed
several power management IC including low voltage low noise LDO
123
Analog Integr Circ Sig Process
regulator and microprocessor supervisor IC. He has joined the
Department of Electrical and Electronic Engineering, American
International University—Bangladesh (AIUB), Dhaka, Bangladesh in
January 2011 and currently serving as Assistant Professor. His
research interests include power management IC, microprocessor
supervisor IC and power electronics embedded system.
Didar Islam has completed his
B.Sc. in Electrical and Electronic
Engineering from Bangladesh
University of Engineering and
Technology (BUET) in 1992 and
M.S. in Electrical Engineering
from University of Florida,
Gainesville, USA in 1996. He
was the founding partner of AIT,
a Florida based Analog IC
designed company (1997–2000),
served as Design Manager in
Maxim Integrated Products Inc.,
USA, (2001–2003) and founder
of Power IC Ltd. (2004). He has
several US patents including QIWKRADIO (single chip CMOS radio).
He is currently residing at Dhaka, Bangladesh and serving as CEO of
Power IC Ltd., developing integrated circuits and embedded systems
for various applications including photo-voltaic cell power conversion
systems.
A. B. M. Harun-ur Rashid has
received his B.Sc. in Electrical
and Electronic Engineering
from Bangladesh University of
Engineering and Technology
(BUET) Dhaka, Bangladesh in
1984, M.Sc. in Electronic
Engineering from Oita Univer-
sity, Japan in 1988 and Ph.D. in
Electronic Engineering from
University of Tokyo, Japan in
1996. He has been serving as
faculty member in the Depart-
ment of Electrical and Elec-
tronic Engineering at BUET
where he is now a Professor. He also served as Design Engineer at
Texas Instruments Japan Ltd. (1988–1993) where he worked on the
research and development of 1.2 lm Bi-CMOS process for mixed
signal VLSI circuits. He was also a Research Fellow at Research
Center for Nanodevices and Systems, Hiroshima University, Japan
(2001–2003) where he demonstrated for the first time very small size
integrated antenna with very high transmission gain achieved by
proton implantation on a Si-substrate. His current research projects
include High frequency (25 GHz) Transceiver circuit design for on-
chip wireless interconnect using integrated antenna, novel circuit
design using carbon nanotube, fault detection and localization in
analog and mixed-signal integrated circuit and Si on-chip wireless
channel modeling.