CD74HC7046A,

Data sheet acquired from Harris Semiconductor

SCHS218
CD74HCT7046A
Phase-Locked Loop
February 1998 with VCO and Lock Detector

Features Description
• Center Frequency of 18MHz (Typ) at VCC = 5V, The Harris CD74HC7046A and CD74HCT7046A high-speed
Minimum Center Frequency of 12MHz at VCC = 4.5V silicon-gate CMOS devices, specified in compliance with
[ /Title JEDEC Standard No. 7A, are phase-locked-loop (PLL)
• Choice of Two Phase Comparators
(CD74 - Exclusive-OR
circuits that contain a linear voltage-controlled oscillator
HC704 (VCO), two-phase comparators (PC1, PC2), and a lock
- Edge-Triggered JK Flip-Flop detector. A signal input and a comparator input are common
6A, to each comparator. The lock detector gives a HIGH level at
• Excellent VCO Frequency Linearity
CD74 pin 1 (LD) when the PLL is locked. The lock detector
• VCO-Inhibit Control for ON/OFF Keying and for Low
HCT70 Standby Power Consumption
capacitor must be connected between pin 15 (CLD) and pin
46A) 8 (Gnd). For a frequency range of 100kHz to 10MHz, the
• Minimal Frequency Drift lock detector capacitor should be 1000pF to 10pF,
/Sub- respectively.
• Zero Voltage Offset Due to Op-Amp Buffer
ject
• Operating Power-Supply Voltage Range The signal input can be directly coupled to large voltage
(Phase- signals, or indirectly coupled (with a series capacitor) to
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
Locked - Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
small voltage signals. A self-bias input circuit keeps small
Loop voltage signals within the linear region of the input amplifiers.
• Fanout (Over Temperature Range) With a passive low-pass filter, the 7046A forms a second-
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads order loop PLL. The excellent VCO linearity is achieved by
the use of linear op-amp techniques.
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC Ordering Information
• Balanced Propagation Delay and Transition Times
TEMP. RANGE
• Significant Power Reduction Compared to LSTTL PART NUMBER (oC) PACKAGE PKG. NO.
Logic ICs
CD74HC7046AE -55 to 125 16 Ld PDIP E16.3
• HC Types
CD74HCT7046AE -55 to 125 16 Ld PDIP E16.3
- 2V to 6V Operation
CD74HC7046AM -55 to 125 16 Ld SOIC M16.15
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V CD74HCT7046AM -55 to 125 16 Ld SOIC M16.15

• HCT Types NOTES:

- 4.5V to 5.5V Operation 1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min) 2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Harris customer service for ordering information.

Applications
• FM Modulation and Demodulation
• Frequency Synthesis and Multiplication
• Frequency Discrimination
• Tone Decoding
• Data Synchronization and Conditioning
• Voltage-to-Frequency Conversion
• Motor-Speed Control
• Related Literature
- AN8823, CMOS Phase-Locked-Loop Application
Using the CD74HC/HCT7046A and
CD74HC/HCT7046A

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. File Number 1920.1
Copyright © Harris Corporation 1998
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 CD74HC7046A, CD74HCT7046A

Pinout Functional Diagram

CD74HC7046A, CD74HCT7046A
(PDIP, SOIC) 2
TOP VIEW 3 PC1OUT
COMPIN 15
CLD
LD 1 16 VCC φ 13
14 PC2OUT
PC1OUT 2 15 CLD SIGIN
1
LD
COMPIN 3 14 SIGIN
VCOOUT 4 13 PC2OUT 6
INH 5 C1A
12 R2 7
C1B 4
C1A 6 11 R1
11 VCOOUT
C1B 7 10 DEMOUT R1
12 VCO
R2 10
GND 8 9 VCOIN
9 DEMOUT
VCOIN
5
INH

C1
6 7 4 3 14
COMPIN SIGIN
VCOOUT

C1A C1B

PC1OUT 2

VREF
+

150Ω
12 R2
- VCO
1.5K
R2 LOCK
LOCK DETECTOR DETECTOR
1
OUTPUT
11 R1 15

R1 CLD
LOCK
- + VCC
VCC

DETECTOR
DEMOUT

UP CAPACITOR
D Q
p
10
CP Q R3
PC2OUT 13
- RD
R5 +
C2

VCC Q
D GND

CP DOWN
Q
RD

INH VCOIN

5 9

FIGURE 1. LOGIC DIAGRAM

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 CD74HC7046A, CD74HCT7046A

Pin Descriptions Phase Comparator 1 (PC1)

PIN NO. SYMBOL NAME AND FUNCTION

This is an Exclusive-OR network. The signal and comparator
input frequencies (fi) must have a 50% duty factor to obtain
1 LD Lock Detector Output (Active High) the maximum locking range. The transfer characteristic of
2 PC1OUT Phase Comparator 1 Output PC1, assuming ripple (fr = 2fi) is suppressed, is:

3 COMPIN Comparator Input VDEMOUT = (VCC/π) (φSIGIN - φCOMPIN) where VDEMOUT

is the demodulator output at pin 10; VDEMOUT = VPC1OUT
4 VCOOUT VCO Output (via low-pass filter).
5 INH Inhibit Input
The average output voltage from PC1, fed to the VCO input
6 C1A Capacitor C1 Connection A via the low-pass filter and seen at the demodulator output at
pin 10 (VDEMOUT), is the resultant of the phase differences
7 C1B Capacitor C1 Connection B
of signals (SIGIN) and the comparator input (COMPIN) as
8 Gnd Ground (0V) shown in Figure 2. The average of VDEM is equal to 1/2 VCC
9 VCOIN VCO Input
when there is no signal or noise at SIGIN, and with this input
the VCO oscillates at the center frequency (fo). Typical wave-
10 DEMOUT Demodulator Output forms for the PC1 loop locked at fo shown in Figure 3.
11 R1 Resistor R1 Connection The frequency capture range (2fc) is defined as the fre-
12 R2 Resistor R2 Connection quency range of input signals on which the PLL will lock if it
was initially out-of-lock. The frequency lock range (2fL) is
13 PC2OUT Phase Comparator 2 Output defined as the frequency range of input signals on which the
14 SIGIN Signal Input loop will stay locked if it was initially in lock. The capture
range is smaller or equal to the lock range.
15 CLD Lock Detector Capacitor Input
With PC1, the capture range depends on the low-pass filter
16 VCC Positive Supply Voltage
characteristics and can be made as large as the lock range.
This configuration retains lock behavior even with very noisy
General Description input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO VCO center frequency.
The VCO requires one external capacitor C1 (between C1A
and C1B) and one external resistor R1 (between R1 and Phase Comparator 2 (PC2)
Gnd) or two external resistors R1 and R2 (between R1 and This is a positive edge-triggered phase and frequency detec-
Gnd, and R2 and Gnd). Resistor R1 and capacitor C1 deter- tor. When the PLL is using this comparator, the loop is con-
mine the frequency range of the VCO. Resistor R2 enables trolled by positive signal transitions and the duty factors of
the VCO to have a frequency offset if required. See logic dia- SIGIN and COMPIN are not important. PC2 comprises two
gram, Figure 1. D-type flip-flops, control-gating and a three-state output
The high input impedance of the VCO simplifies the design stage. The circuit functions as an up-down counter (Figure
of low-pass filters by giving the designer a wide choice of 1) where SIGIN causes an up-count and COMPIN a down-
resistor/capacitor ranges. In order not to load the low-pass count. The transfer function of PC2, assuming ripple (fr = fi)
filter, a demodulator output of the VCO input voltage is pro- is suppressed, is:
vided at pin 10 (DEMOUT). In contrast to conventional tech- VDEMOUT = (VCC/4π) (φSIGN - φCOMPIN) where VDEMOUT
niques where the DEMOUT voltage is one threshold voltage is the demodulator output at pin 10; VDEMOUT = VPC2OUT
lower than the VCO input voltage, here the DEMOUT voltage (via low-pass filter).
equals that of the VCO input. If DEMOUT is used, a load
resistor (RS) should be connected from DEMOUT to Gnd; if The average output voltage from PC2, fed to the VCO via the
unused, DEMOUT should be left open. The VCO output low-pass filter and seen at the demodulator output at pin 10
(VCOOUT) can be connected directly to the comparator (VDEMOUT), is the resultant of the phase differences of
input (COMPIN), or connected via a frequency-divider. The SIGIN and COMPIN as shown in Figure 4. Typical waveforms
VCO output signal has a guaranteed duty factor of 50%. A for the PC2 loop locked at fo are shown in Figure 5.
LOW level at the inhibit input (INH) enables the VCO, while a When the frequencies of SIGIN and COMPIN are equal but
HIGH level disables the VCO to minimize standby power the phase of SIGIN leads that of COMPIN, the p-type output
consumption. driver at PC2OUT is held “ON” for a time corresponding to
the phase differences (φDEMOUT). When the phase of SIGIN
Phase Comparators
lags that of COMPIN, the n-type driver is held “ON”.
The signal input (SIGIN) can be directly coupled to the self-
When the frequency of SIGIN is higher than that of COMPIN,
biasing amplifier at pin 14, provided that the signal swing is
the p-type output driver is held “ON” for most of the input sig-
between the standard HC family input logic levels, Capaci-
nal cycle time, and for the remainder of the cycle both n-type
tive coupling is required for signals with smaller swings.
and p-type drivers are “OFF” (three-state). If the SIGIN fre-

3
 CD74HC7046A, CD74HCT7046A
quency is lower than the COMPIN frequency, then it is the n-
type driver that is held “ON” for most of the cycle. Subse-
quently, the voltage at the capacitor (C2) of the low-pass filter
connected to PC2OUT varies until the signal and comparator
inputs are equal in both phase and frequency. At this stable
point the voltage on C2 remains constant as the PC2 output is
in three-state and the VCO input at pin 9 is a high impedance.
Thus, for PC2, no phase difference exists between SIGIN
and COMPIN over the full frequency range of the VCO.
Moreover, the power dissipation due to the low-pass filter is
reduced because both p-type and n-type drivers are “OFF”
for most of the signal input cycle. It should be noted that the
PLL lock range for this type of phase comparator is equal to
the capture range and is independent of the low-pass filter.
With no signal present at SIGIN, the VCO adjusts, via PC2,
to its lowest frequency.
Lock Detector Theory of Operation
Detection of a locked condition is accomplished by a NOR
gate and an envelope detector as shown in Figure 6. When
the PLL is in Lock, the output of the NOR gate is High and
the lock detector output (Pin 1) is at a constant high level. As
the loop tracks the signal on Pin 14 (signal in), the NOR gate
outputs pulses whose widths represent the phase differ-
ences between the VCO and the input signal. The time
between pulses will be approximately equal to the time con-
stant of the VCO center frequency. During the rise time of
the pulse, the diode across the 1.5kΩ resistor is forward
VCC
VDEMOUT (AV)
1/2 VCC
0 GND
0o 90o φDEMOUT 180o
FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
VDEMOUT = VPC1OUT = (VCC/π) (φSIGIN - φCOM-
PIN); φDEMOUT = (φSIGIN - φCOMPIN)
4
biased and the time constant in the path that charges the
lock detector capacitor is T = (150Ω x CLD).
During the fall time of the pulse the capacitor discharges
through the 1.5kΩ and the 150Ω resistors and the channel
resistance of the n-device of the NOR gate to ground
(T = (1.5kΩ + 150Ω + Rn-channel) x CLD).
The waveform preset at the capacitor resembles a sawtooth
as shown in Figure 7. The lock detector capacitor value is
determined by the VCO center frequency. The typical range
of capacitor for a frequency of 10MHz is about 10pF and for
a frequency of 100kHz is about 1000pF. The chart in Figure
8 can be used to select the proper lock detector capacitor
value. As long as the loop remains locked and tracking, the
level of the sawtooth will not go below the switching thresh-
old of the Schmitt-trigger inverter. If the loop breaks lock, the
width of the error pulse will be wide enough to allow the saw-
tooth waveform to go below threshold and a level change at
the output of the Schmitt trigger will indicate a loss of lock,
as shown in Figure 9. The lock detector capacitor also acts
to filter out small glitches that can occur when the loop is
either seeking or losing lock.
Note: When using phase comparator 1, the detector will only
indicate a lock condition on the fundamental frequency and
not on the harmonics, which PC1 will also lock on. If a detec-
tion of lock is needed over the harmonic locking range of
PC1, then the lock detector output must be OR-ed with the
output of PC1.
SIGIN
COMPIN
VCOOUT
PC1OUT
VCC
VCOIN
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 1, LOOP LOCKED AT fo
 CD74HC7046A, CD74HCT7046A

VCC
SIGIN

VDEMOUT (AV) COMPIN

VCOOUT
VCC
1/2 VCC PC2OUT
GND

HIGH IMPEDANCE OFF - STATE

VCOIN

0 PCPOUT
-360o 0o φDEMOUT 360o

FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE
VOLTAGE vs INPUT PHASE DIFFERENCE: COMPARATOR 2, LOOP LOCKED AT fo
VDEMOUT = VPC2OUT = (VCC/π) (φSIGIN - φCOM-
PIN); φDEMOUT = (φSIGIN - φCOMPIN)

7046 LOCK DETECTOR CIRCUITRY

PHASE DIFFERENCE
SIGIN
UP
FF

PIN 1
1.5kΩ 150Ω LOCK DETECTOR
OUTPUT
DN
COMPIN FF

CLD
PIN 15

LOCK DETECTOR
CAPACITOR

FIGURE 6. CD74HC/HCT7046A LOCK DETECTOR CIRCUIT

LOCK
PIN 1
DETECTOR
1.5kΩ 150Ω
OUTPUT
PIN 15 CLD
LOCK
DETECTOR
CAPACITOR VCAP VTH

FIGURE 7. WAVEFORM PRESENT AT LOCK DETECTOR CAPACITOR WHEN IN LOCK

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 CD74HC7046A, CD74HCT7046A

10M

LOCK DETECTOR CAPACITOR VALUE (pF)

1M

100K

10K

1K

100

10

10 100 1K 10K 100K 1M 10M 100M

f, VCO CENTER FREQUENCY (HZ)

FIGURE 8. LOCK DETECTOR CAPACITOR SELECTION CHART

LOSS OF LOCK
PIN 1
1.5kΩ 150Ω LOCK
DETECTOR
PIN 15 CLD OUTPUT
LOCK
DETECTOR VCAP VTH
CAPACITOR

FIGURE 9. WAVEFORM PRESENT AT LOCK DETECTOR CAPACITOR WHEN UNLOCKED

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 CD74HC7046A, CD74HCT7046A

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
VCO SECTION
INH High Level Input VIH - - 3 2.1 - - 2.1 - 2.1 - V
Voltage
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
INH Low Level Input VIL - - 3 - - 0.9 - 0.9 - 0.9 V
Voltage
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
VCOOUT High Level VOH VIH or VIL -0.02 3 2.9 - - 2.9 - 2.9 - V
Output Voltage
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
-0.02 6 5.9 - - 5.9 - 5.9 - V
VCOOUT High Level - - - - - - - - - V
Output Voltage
-4 4.5 3.98 - - 3.84 - 3.7 - V
TTL Loads
-5.2 6 5.48 - - 5.34 - 5.2 - V
VCOOUT Low Level VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
Output Voltage
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
0.02 6 - - 0.1 - 0.1 - 0.1 V
VCOOUT Low Level - - - - - - - - - V
Output Voltage
4 4.5 - - 0.26 - 0.33 - 0.4 V
TTL Loads
5.2 6 - - 0.26 - 0.33 - 0.4 V
C1A, C1B Low Level VOL VIL or 4 4.5 - - 0.40 - 0.47 - 0.54 V
Output Voltage VOL
5.2 6 - - 0.40 - 0.47 - 0.54 V
(Test Purposes Only)

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 CD74HC7046A, CD74HCT7046A

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
INH VCOIN Input II VCC or - 6 - - ±0.1 - ±1 - ±1 µA
Leakage Current GND
R1 Range (Note 4) - - - 4.5 3 - - - - - - kΩ
R2 Range (Note 4) - - - 4.5 3 - - - - - - kΩ
C1 Capacitance - - - 3 - - No - - - - pF
Range Limit
4.5 40 - - - - - pF
6 - - - - - - pF
VCOIN Operating - Over the range 3 1.1 - 1.9 - - - - V
Voltage Range specified for R1 for
4.5 1.1 - 3.2 - - - - V
Linearity See Figure
8, and 35 - 38 6 1.1 - 4.6 - - - - V
(Note 5)
PHASE COMPARATOR SECTION
SIGIN, COMPIN VIH - - 2 1.5 - - 1.5 - 1.5 - V
DC Coupled
4.5 3.15 - - 3.15 - 3.15 - V
High-Level Input
Voltage 6 4.2 - - 4.2 - 4.2 - V
SIGIN, COMPIN VIL - - 2 - - 0.5 - 0.5 - 0.5 V
DC Coupled
4.5 - - 1.35 - 1.35 - 1.35 V
Low-Level Input
Voltage 6 - - 1.8 - 1.8 - 1.8 V
LD, PCnOUT High- VOH VIL or VIH -0.02 2 1.9 - - 1.9 - 1.9 - V
Level Output Voltage
4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
6 5.9 - - 5.9 - 5.9 - V
LD, PCnOUT High- VOH VIL or VIH -4 4.5 3.98 - - 3.84 - 3.7 - V
Level Output Voltage
-5.2 6 5.48 - - 5.34 - 5.2 - V
TTL Loads
LD, PCnOUT Low- VOL VIL or VIH 0.02 2 - - 0.1 - 0.1 - 0.1 V
Level Output Voltage
4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
6 - - 0.1 - 0.1 - 0.1 V
LD, PCnOUT Low- VOL VIL or VIH 4 4.5 - - 0.26 - 0.33 - 0.4 V
Level Output Voltage
5.2 6 - - 0.26 - 0.33 - 0.4 V
TTL Loads
SIGIN, COMPIN Input II VCC or - 2 - - ±3 - ±4 - ±5 µA
Leakage Current GND
3 - - ±7 - ±9 - ±11 µA
4.5 - - ±18 - ±23 - ±29 µA
6 - - ±30 - ±38 - ±45 µA
PC2OUT Three-State IOZ VIL or VIH - 6 - - ±0.5 - ±5 - ±10 µA
Off-State Current
SIGIN, COMPIN Input RI VI at Self-Bias 3 - 800 - - - - - kΩ
Resistance Operation Point:
4.5 - 250 - - - - - kΩ
∆VI = 0.5V,
See Figure 8 6 - 150 - - - - - kΩ
DEMODULATOR SECTION
Resistor Range RS at RS > 300kΩ 3 10 - 300 - - - - kΩ
Leakage Current
4.5 10 - 300 - - - - kΩ
Can Influence
VDEMOUT 6 10 - 300 - - - - kΩ

8
 CD74HC7046A, CD74HCT7046A

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Offset Voltage VCOIN VOFF VI = VVCOIN = 3 - ±30 - - - - - mV
to VDEM VCC
4.5 - ±20 - - - - - mV
2
Values taken over 6 - ±10 - - - - - mV
RS Range
See Figure 15
Dynamic Output RO VDEMOUT = 3 - 25 - - - - - Ω
Resistance at VCC
4.5 - 25 - - - - - Ω
DEMOUT 2
6 - 25 - - - - - Ω
Quiescent Device ICC Pins 3, 5 and 14 6 - - 8 - 80 - 160 µA
Current at VCC Pin 9 at
GND, II at Pins 3
and 14 to be
excluded
HCT TYPES
VCO SECTION
INH High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V
Voltage 5.5
INH Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
Voltage 5.5
VCOOUT High Level VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
Output Voltage
CMOS Loads
VCOOUT High Level -4 4.5 3.98 - - 3.84 - 3.7 - V
Output Voltage
TTL Loads
VCOOUT Low Level VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Output Voltage
CMOS Loads
VCOOUT Low Level 4 4.5 - - 0.26 - 0.33 - 0.4 V
Output Voltage
TTL Loads
C1A, C1B Low Level VOL VIH or VIL 4 4.5 - - 0.40 - 0.47 - 0.54 V
Output Voltage
(Test Purposes Only)
INH VCOIN Input II Any Voltage 5.5 - ±0.1 - ±1 - ±1 µA
Leakage Current Between VCC and
GND
R1 Range (Note 4) - - - 4.5 3 - - - - - - kΩ
R2 Range (Note 4) - - - 4.5 3 - - - - - - kΩ
C1 Capacitance - - - 4.5 40 - No - - - - pF
Range Limit
VCOIN Operating - Over the range 4.5 1.1 - 3.2 - - - - V
Voltage Range specified for R1 for
Linearity See Figure
8, and 35 - 38
(Note 5)
PHASE COMPARATOR SECTION
SIGIN, COMPIN VIH - - 4.5 to 3.15 - - 3.15 - 3.15 - V
DC Coupled 5.5
High-Level Input
Voltage

9
 CD74HC7046A, CD74HCT7046A

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
SIGIN, COMPIN VIL - - 4.5 to - - 1.35 - 1.35 - 1.35 V
DC Coupled 5.5
Low-Level Input
Voltage
LD, PCnOUT High- VOH VIL or VIH - 4.5 4.4 - - 4.4 - 4.4 - V
Level Output Voltage
CMOS Loads
LD, PCnOUT High- VOH VIL or VIH - 4.5 3.98 - - 3.84 - 3.7 - V
Level Output Voltage
TTL Loads
LD, PCnOUT Low- VOL VIL or VIH - 4.5 - - 0.1 - 0.1 - 0.1 V
Level Output Voltage
CMOS Loads
LD, PCnOUT Low- VOL VIL or VIH - 4.5 - - 0.26 - 0.33 - 0.4 V
Level Output Voltage
TTL Loads
SIGIN, COMPIN Input II Any - 5.5 - - ±30 ±38 ±45 µA
Leakage Current Voltage
Between
VCC and
GND
PC2OUT Three-State IOZ VIL or VIH - 5.5 - - ±0.5 ±5 - - ±10 µA
Off-State Current
SIGIN, COMPIN Input RI VI at Self-Bias 4.5 - 250 - - - - - kΩ
Resistance Operation Point:
∆V, 0.5V,
See Figure 8
DEMODULATOR SECTION
Resistor Range RS at RS > 300kΩ 4.5 10 - 300 - - - - kΩ
Leakage Current
Can Influence
VDEMOUT
Offset Voltage VCOIN VOFF VI = VVCOIN = 4.5 - ±20 - - - - - mV
to VDEM VCC
2
Values taken over
RS Range
See Figure 15
Dynamic Output RO VDEMOUT = 4.5 - 25 - - - - - Ω
Resistance at VCC
DEMOUT 2
Quiescent Device ICC VCC or - 5.5 - - 8 - 80 - 160 µA
Current GND
Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA
Device Current Per -2.1 5.5
Input Pin: 1 Unit Load (Exclud-
Note 6 ing Pin 5)
NOTES:
4. The value for R1 and R2 in parallel should exceed 2.7kΩ; R1 and R2 values above 300kΩ may contribute to frequency shift due to leakage
currents.
5. The maximum operating voltage can be as high as VCC -0.9V, however, this may result in an increased offset voltage.
6. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

10
 CD74HC7046A, CD74HCT7046A

HCT Input Loading Table

INPUT UNIT LOADS

INH 1

NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,

360µA max at 25oC.

Switching Specifications CL = 50pF, Input tr, tf = 6ns

-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
PHASE COMPARATOR SECTION
Propagation Delay tPLH, tPHL
SIGIN, COMPIN to PC1OUT 2 - - 200 - 250 - 300 ns
4.5 - - 40 - 50 - 60 ns
6 - - 34 - 43 - 51 ns
Output Transition Time tTHL, tTLH 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Output Enable Time, SIGIN, tPZH, tPZL 2 - - 280 - 350 - 420 ns
COMPIN to PC2OUT
4.5 - - 56 - 70 - 84 ns
6 - - 48 - 60 - 71 ns
Output Disable Time, SIGIN, tPHZ, tPLZ 2 - - 325 - 405 - 490 ns
COMPIN to PC2OUT
4.5 - - 65 - 81 - 98 ns
6 - - 55 - 69 - 83 ns
AC Coupled Input Sensitivity (P- VI(P-P) 3 - 11 - - - - - mV
P) at SIGIN or COMPIN 4.5 - 15 - - - - - mV
6 - 33 - - - - - mV
VCO SECTION
Frequency Stability with ∆f R1 = 100kΩ, 3 - - - Typ 0.11 - - %/oC
Temperature Change ∆T R2 = ∞
4.5 - - - - - %/oC
6 - - - - - %/oC
Maximum Frequency fMAX C1 = 50pF 3 - - - - - - - MHz
R1 = 3.5kΩ
4.5 - 24 - - - - - MHz
R2 = ∞
6 - - - - - - - MHz
C1 = 0pF 3 - - - - - - - MHz
R1 = 9.1kΩ
4.5 - 38 - - - - - MHz
R2 = ∞
6 - - - - - - - MHz
Center Frequency fo C1 = 40pF 3 7 10 - - - - - MHz
R1 = 3kΩ
4.5 12 17 - - - - - MHz
R2 = ∞
VCOIN = VCC/2 6 14 21 - - - - - MHz
Frequency Linearity ∆fVCO R1 = 100kΩ 3 - - - - - - - %
R2 = ∞
4.5 - 0.4 - - - - - %
C1 = 100pF
6 - - - - - - - %

11
 CD74HC7046A, CD74HCT7046A

Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued)

-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Offset Frequency R2 = 220kΩ 3 - - - - - - - kHz
C1 = 1nF
4.5 - 400 - - - - - kHz
6 - - - - - - - kHz
DEMODULATOR SECTION
VOUT vs fIN R1 = 100kΩ 3 - - - - - - - mV/kHz
R2 = ∞
4.5 - 330 - - - - - mV/kHz
C1 = 100pF
R5 = 10kΩ 6 - - - - - - - mV/kHz
R3 = 100kΩ
C2 = 100pF
HCT TYPES
PHASE COMPARATOR SECTION
Propagation Delay tPLH, tPHL
SIGIN, COMPIN to PC1OUT 4.5 - - 45 - 56 - 68 ns
Output Transition Time tTHL, tTLH 4.5 - - 15 - 19 - 22 ns
Output Enable Time, SIGIN, tPZH, tPZL 4.5 - - 60 - 75 - 90 ns
COMPIN to PC2OUT
Output Disable Time, SIGIN, tPHZ, tPLZ 4.5 - - 70 - 86 - 105 ns
COMPIN to PCZOUT
AC Coupled Input Sensitivity VI(P-P) 3 - 11 - - - - - mV
(P-P) at SIGIN or COMPIN
4.5 - 15 - - - - - mV
6 - 33 - - - - - mV
VCO SECTION
Frequency Stability with ∆f R1 = 100kΩ, 4.5 - - - Typ 0.11 - - %/oC
Temperature Change ∆T R2 = ∞
Maximum Frequency fMAX C1 = 50pF 4.5 - 24 - - - - - MHz
R1 = 3.5kΩ
R2 = ∞
C1 = 0pF 4.5 - 38 - - - - - MHz
R1 = 9.1kΩ
R2 = ∞
Center Frequency fo C1 = 40pF 4.5 12 17 - - - - - MHz
R1 = 3kΩ
R2 = ∞
VCOIN = VCC/2
Frequency Linearity ∆fVCO R1 = 100kΩ 4.5 - 0.4 - - - - - %
R2 = ∞
C1 = 100pF
Offset Frequency R2 = 220kΩ 4.5 - 400 - - - - - kHz
C1 = 1nF
DEMODULATOR SECTION
VOUT vs fIN R1 = 100kΩ 4.5 - 330 - - - - - mV/kHz
R2 = ∞
C1 = 100pF
R5 = 10kΩ
R3 = 100kΩ
C2 = 100pF

12
 CD74HC7046A, CD74HCT7046A

Test Circuits and Waveforms

tr = 6ns tf = 6ns tr = 6ns tf = 6ns

VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50% 1.3V
INVERTING 10% INVERTING
10%
OUTPUT OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 10. HC TRANSITION TIMES AND PROPAGATION FIGURE 11. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

Typical Performance Curves

108
R1 = 2.2K
II R1 = 22K
107
R1 = 220K
CENTER FREQUENCY (Hz)

∆VI 106 R1 = 2.2M

R1 = 11M
105

104

103

102
VCOIN = 0.5 VCC
10 VCC = 4.5V
R2 = ∞
SELF-BIAS OPERATING POINT
1
1 10 102 103 104 105 106
CAPACITANCE, C1 (pF)
VI

FIGURE 12. TYPICAL INPUT RESISTANCE CURVE AT FIGURE 13. HC7046A TYPICAL CENTER FREQUENCY vs R1, C1
SIGIN, COMPIN

108 108
R1 = 3K R1 = 1.5K
107 R1 = 30K R1 = 15K
R1 = 330K 107 R1 = 150K
CENTER FREQUENCY (Hz)

CENTER FREQUENCY (Hz)

106 R1 = 3M R1 = 1.5M
R1 = 15M 106 R1 = 7.5M
105 105

104 104

103 103

102 102 VCOIN = 0.5 VCC

VCOIN = 0.5 VCC
10 VCC = 6.0V VCC = 3.0V
10
R2 = ∞ R2 = ∞
1 1
1 10 102 103 104 105 106 1 10 102 103 104 105 106
CAPACITANCE, C1 (pF) CAPACITANCE, C1 (pF)

FIGURE 14. HC7046A TYPICAL CENTER FREQUENCY vs R1, C1 FIGURE 15. HC7046A TYPICAL CENTER FREQUENCY vs R1, C1

13
 CD74HC7046A, CD74HCT7046A

Typical Performance Curves (Continued)

108 108
R1 = 2.2K R1 = 3K
107 R1 = 22K R1 = 30K
R1 = 220K 107
CENTER FREQUENCY (Hz)

R1 = 300K

CENTER FREQUENCY (Hz)

106 R1 = 2.2M R1 = 3M
R1 = 11M 106 R1 = 15M
105
105
104 104
103 103
102
VCOIN = 0.5 VCC 102
VCOIN = 0.5 VCC
10 VCC = 4.5V VCC = 5.5V
10
R2 = ∞ R2 = ∞
1 1
1 10 102 103 104 105 106 1 10 102 103 104 105 106
CAPACITANCE, C1 (pF) CAPACITANCE, C1 (pF)

FIGURE 16. HCT7046A TYPICAL CENTER FREQUENCY vs R1, C1 FIGURE 17. HCT7046A TYPICAL CENTER FREQUENCY vs R1, C1

140 90
C1 = 50pF C1 = 0.1µF VCC = 6V
VCC = 6V
R1 = 1.5M 80 R1 = 1.5M
120 R2 = ∞
R2 = ∞
VCO FREQUENCY (kHz)

VCO FREQUENCY (Hz)

70
100 VCC = 4.5V
VCC = 4.5V 60

80 50

40 VCC = 3V
60 VCC = 3V
30
40
20

20 10
0 1 2 3 4 5 6 0 1 2 3 4 5 6

VCOIN (V) VCOIN (V)

FIGURE 18. HC7046A TYPICAL VCO FREQUENCY vs VCOIN FIGURE 19. HC7046A TYPICAL VCO FREQUENCY vs VCOIN
(R1 = 1.5MΩ, C1 = 0.1µF)

800 18
C1 = 0.1µF VCC = 6V C1 = 0.1µF VCC = 6V
R1 = 150K 16 R1 = 5.6k
700
R2 = ∞ R2 = ∞ VCC = 4.5V
VCO FREQUENCY (kHz)
VCO FREQUENCY (Hz)

14
600
VCC = 3V
VCC = 4.5V
12
500
10
400
VCC = 3V 8
300
6

200 4

100 2
0 1 2 3 4 5 6 0 1 2 3 4 5 6

VCOIN (V) VCOIN (V)

FIGURE 20. HC7046A TYPICAL VCO FREQUENCY vs VCOIN FIGURE 21. HC7046A TYPICAL VCO FREQUENCY vs VCOIN
(R1 = 150kΩ, C1 = 0.1µF) (R1 = 5.6kΩ, C1 = 0.1µF)

14
 CD74HC7046A, CD74HCT7046A

Typical Performance Curves (Continued)

1400 24
VCC = 6V C1 = 50pF VCC = 6V
C1 = 50pF
1200 R1 = 150K R1 = 5.6K
20
R2 = ∞ R2 = ∞

VCO FREQUENCY (MHz)

VCO FREQUENCY (kHz)

1000 VCC = 4.5V VCC = 4.5V

16

800
VCC = 3V 12 VCC = 3V
600

8
400

200 4
0 1 2 3 4 5 6 0 1 2 3 4 5 6

VCOIN (V) VCOIN (V)

FIGURE 22. HC7046A TYPICAL VCO FREQUENCY vs VCOIN FIGURE 23. HC7046A TYPICAL VCO FREQUENCY vs VCOIN
(R1 = 150kΩ, C1 = 0.1µF) (R1 = 5.6kΩ, C1 = 50pF)

24
VCOIN = 0.5 VCC 20 VCOIN = 0.5 VCC
R1 = 2.2M
VCO FREQUENCY CHANGE, ∆f (%)

R1 = 1.5M
20 C1 = 50pF, VCC = 3V VCO FREQUENCY CHANGE, ∆f (%) C1 = 50pF, VCC = 4.5V
R2 = ∞
16 R2 = ∞
16
12 12
R1 = 150K
8 8 R1 = 220K

4 4
0 R1 = 3K
0
-4
-4 R1 = 2.2K
-8
-12 -8

-16 -12
-75 -50 -25 0 25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE, TA (oC) AMBIENT TEMPERATURE, TA (oC)

FIGURE 24. HC7046A TYPICAL CHANGE IN VCO FREQUENCY FIGURE 25. HC7046A TYPICAL CHANGE IN VCO FREQUENCY vs
vs AMBIENT TEMPERATURE AS A FUNCTION OF AMBIENT TEMPERATURE AS A FUNCTION OF R1
R1 (VCC = 3V)

15
 CD74HC7046A, CD74HCT7046A

Typical Performance Curves (Continued)

20
16 VCOIN = 0.5 VCC VCOIN = 0.5 VCC
R1 = 3M
VCO FREQUENCY CHANGE, ∆f (%)

C1 = 50pF, VCC = 6.0V

VCO FREQUENCY CHANGE, ∆f (%)

16 C1 = 50pF, VCC = 5.5V
12 R2 = ∞ R2 = ∞
R1 = 3M

12
8
R1 = 300K
8 R1 = 300K
4
4
0
0
-4 R1 = 3K R1 = 3K
-4
-8
-8
-12
-12
-75 -50 -25 0 25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE, TA (oC) AMBIENT TEMPERATURE, TA (oC)

FIGURE 26. HC7046A TYPICAL CHANGE IN VCO FREQUENCY vs FIGURE 27. HCT7046A TYPICAL CHANGE IN VCO
AMBIENT TEMPERATURE AS A FUNCTION OF R1 FREQUENCY vs AMBIENT TEMPERATURE AS A
FUNCTION OF R1

VCOIN = 0.5 VCC 108

20 R1 = 2.2M
VCO FREQUENCY CHANGE, ∆f (%)

C1 = 50pF, VCC = 4.5V

107
16 R2 = ∞
OFFSET FREQUENCY (Hz)

12 106
R2 = 2.2K
R1 = 220K 105
8
R2 = 22K
4 104

0 R2 = 220K
103

-4 R1 = 2.2K R2 = 2.2M
102

-8 10 VCOIN = 0.5 VCC

VCC = 4.5V R2 = 11M
-12 1
-75 -50 -25 0 25 50 75 100 125 150 1 10 102 103 104 105 106
AMBIENT TEMPERATURE, TA (oC) CAPACITANCE, C1 (pF)

FIGURE 28. HC7046A TYPICAL CHANGE IN VCO FREQUENCY vs FIGURE 29. HC7046A OFFSET FREQUENCY vs R2, C1
AMBIENT TEMPERATURE AS A FUNCTION OF R1

108 108

107 107
OFFSET FREQUENCY (Hz)

OFFSET FREQUENCY (Hz)

106 R2 = 1.5K 106

R2 = 2.2K
105 105
R2 = 22K
104 R2 = 15K 104

R2 = 150K R2 = 220K
103 103
R2 = 1.5M R2 = 2.2M
102 102

10 VCOIN = GND 10 VCOIN = GND

VCC = 3V R2 = 7.5M VCC = 4.5V R2 = 11M
1 1
1 10 102 103 104 105 106 1 10 102 103 104 105 106
CAPACITANCE, C1 (pF) CAPACITANCE, C1 (pF)

FIGURE 30. HC7046A OFFSET FREQUENCY vs R2, C1 FIGURE 31. HCT7046A OFFSET FREQUENCY vs R2, C1

16
 CD74HC7046A, CD74HCT7046A

Typical Performance Curves (Continued)

108 VCOIN = VCC - 0.9V FOR fMAX

102 VCOIN = 0V FOR fMIN
107 VCC = 3V, 4.5V, 6V
OFFSET FREQUENCY (Hz)

106
R2 = 3K
105

fMAX /fMIN
R2 = 30K
104
10
R2 = 300K
103
R2 = 3M
102
VCOIN = GND
10 HC - VCC = 6V
HCT - VCC = 5.5V R2 = 15M
1 1
1 10 102 103 104 105 106
10-2 10-1 1 10 102
CAPACITANCE, C1 (pF) R2/R1

FIGURE 32. HC7046A AND HCT7046A OFFSET FREQUENCY FIGURE 33. HC7046A fMIN/fMAX vs R2/R1
vs R2, C1

VCOIN = VCC - 0.9V FOR fMAX

102 VCOIN = 0V FOR fMIN
VCC = 4.5V TO 5.5V

f2
fMAX /fMIN

f0
∆V = 0.5V OVER THE VCC RANGE:
10 f0’ FOR VCO LINEARITY
f’o = f1 + f2
f1 2 f’o - fo
LINEARITY = f’ x 100%
o
∆V ∆V

1
MIN 1/2VCC MAX
10-2 10-1 1 10 102
R2/R1 VVCOIN

FIGURE 34. HCT7046A fMAX/fMIN vs R2/R1 FIGURE 35. DEFINITION OF VCO FREQUENCY LINEARITY

8 8
C1 = 50pF C1 = 50pF
6 VCC = 4.5V 6 VCC = 3V
R2 = ∞ R2 = ∞
4 4
VCOIN = 2.25V ± 1V
LINEARITY (%)
LINEARITY (%)

2 2 VCOIN = 1.50V ± 0.4V

0 VCOIN = 2.25V ± 0.45V 0

VCOIN = 1.50V ± 0.3V
-2 -2

-4 -4

-6 -6

-8 -8
1K 10K 100K 1M 10M 1K 10K 100K 1M 10M
R1 (OHMS) R1 (OHMS)

FIGURE 36. HC7046A VCO LINEARITY vs R1 FIGURE 37. HC7046A VCO LINEARITY vs R1

17
 CD74HC7046A, CD74HCT7046A

Typical Performance Curves (Continued)

8 8
C1 = 50pF VCC = 5.5V,
6 VCC = 6V 6 VCOIN = 2.75V ±1.3V
R2 = ∞ VCC = 4.5V,
4 4 VCOIN = 2.25V ±1.0V
VCOIN = 3V ± 1.5V
LINEARITY (%)

LINEARITY (%)
2 2

0 0

-2 -2
VCC = 5.5V,
VCOIN = 2.75V ±0.55V
-4 -4
VCC = 4.5V,
VCOIN = 3V ± 0.6V VCOIN = 2.25V ±0.45V
-6 -6 C1 = 50pF
R2 = OPEN
-8 -8
1K 10K 100K 1M 10M 1K 10K 100K 1M 10M
R1 (OHMS) R1 (OHMS)

FIGURE 38. HC7046A VCO LINEARITY vs R1 FIGURE 39. HCT7046A VCO LINEARITY vs R1

DEMODULATOR POWER DISSIPATION, PD (µW)

DEMODULATOR POWER DISSIPATION, PD (µW)

104 104
VCOIN = 0.5 VCC VCOIN = 0.5 VCC
R1 = R2 = OPEN

103 103
VCC = 6V VCC = 6V

102 102
VCC = 3V VCC = 4.5V VCC = 3V VCC = 4.5V

10 10

1 1
1K 10K 100K 1M 1K 10K 100K 1M
RS (OHMS) RS (OHMS)

FIGURE 40. HC7046A DEMODULATOR POWER DISSIPATION FIGURE 41. HCT7046A DEMODULATOR POWER DISSIPATION
vs RS (TYP) vs RS (TYP) (VCC = 3V, 4.5V, 6V)

106
106 VCOIN = 0V (AT fMIN)
R1 = RS = ∞
VCOIN = 0.5VCC VCC = 6V
VCO POWER DISSIPATION, PD (µW)
VCO POWER DISSIPATION, PD (µW)

R2 = RS = OPEN C1 = 50pF CL = 50pF

CL = 50pF
VCC = 6V 105
105 C1 = 50pF
VCC = 4.5V
VCC = 6V VCC = 4.5V
C1 = 50pF
C1 = 1µF C1 = 50pF
104 VCC = 4.5V
104 C1 = 1µF

VCC = 3V VCC = 6V
C1 = 1µF
C1 = 1µF 103
103 VCC = 3V
C1 = 50pF
VCC = 4.5V
C1 = 1µF 102
102 1K 10K 100K 1M
1K 10K 100K 1M
R2 (OHMS)
R1 (OHMS)

FIGURE 42. HC7046A VCO POWER DISSIPATION vs R1 FIGURE 43. HCT7046A VCO POWER DISSIPATION vs R2
(C1 = 50pF, 1µF) (C1 = 50pF, 1µF)

18
 CD74HC7046A, CD74HCT7046A

Typical Performance Curves (Continued)

106
VCOIN = 0.5V 106
R2 = RS = ∞
VCOIN = 0V (AT fMIN)
VCO POWER DISSIPATION, PD (µW)

VCC = 6V R1 = RS = ∞

VCO POWER DISSIPATION, PD (µW)

VCC = 5.5V
C1 = 50pF C1 = 50pF CL = 50pF
105
105 VCC = 4.5V
VCC = 4.5V C1 = 50pF
C1 = 50pF
VCC = 6V
104 C1 = 1µF
VCC = 5.5V 104
C1 = 1µF VCC = 3V
C1 = 1µF
103 VCC = 4.5V VCC = 3V
103 C1 = 50pF
C1 = 1µF

VCC = 4.5V
102 C1 = 1µF
1K 10K 100K 1M 102
1K 10K 100K 1M
R1 (OHMS)
R2 (OHMS)

FIGURE 44. HCT7046A VCO POWER DISSIPATION vs R1 FIGURE 45. HC7046A VCO POWER DISSIPATION vs R2 (C1 =
(C1 = 50pF, 1µF) 50pF, 1µF)

19
 CD74HC7046A, CD74HCT7046A

HC/HCT7046A CPD References should be made to Figures 13 through 23 and

Figures 36 through 41 as indicated in the table.
CHIP SECTION HC HCT UNIT
Comparator 1 48 50 pF
Values of the selected components should be within the fol-
lowing ranges:
Comparator 2 39 48 pF
R1 > 3kΩ;
VCO 61 53 pF
R2 > 3kΩ;
R1 || R2 parallel value > 2.7kΩ;
Application Information
C1 greater than 40pF
This information is a guide for the approximation of values of
external components to be used with the CD74HC7046A
and CD74HCT7046A in a phase-lock-loop system.

PHASE
SUBJECT COMPARATOR DESIGN CONSIDERATIONS

VCO Frequency PC1 or PC2 VCO Frequency Characteristic

Without Extra Offset The characteristics of the VCO operation are shown in Figures 13 - 23.
(R2 = ∞) fMAX

fVCO

fo 2fL

fMIN
MIN 1/2 VCC VVCOIN MAX

FIGURE 46. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITHOUT

OFFSET: fo = CENTER FREQUENCY: 2fL = FREQUENCY LOCK RANGE

PC1 Selection of R1 and C1

Given fo, determine the values of R1 and C1 using Figures 13 - 17.

PC2 Given fMAX calculate fo as fMAX/2 and determine the values of R1 and C1 using Figures 13 - 17.

To obtain 2fL: 2fL ≈ 2(∆VCOIN) where 0.9V < VCOIN < VCC - 0.9V is the range of ∆VCOIN
R1C1
VCO Frequency with PC1 or PC2 VCO Frequency Characteristic
Extra Offset The characteristics of the VCO operation are shown in Figures 29 - 32.
(R2 > 3kΩ) fMAX
fVCO
fo 2fL

fMIN

MIN 1/2 VCC VVCOIN MAX

FIGURE 47. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITH OFFSET:

fo = CENTER FREQUENCY: 2fL = FREQUENCY LOCK RANGE

PC1 or PC2 Selection of R1, R2 and C1

Given fo and fL, offset frequency, fMIN, may be calculated from fMIN ≈ fo - 1.6 fL.
Obtain the values of C1 and R2 by using Figures 29 - 32.
Calculate the values of R1 from Figures 33 - 34.

20
 PHASE
SUBJECT COMPARATOR DESIGN CONSIDERATIONS

PLL Conditions with PC1 VCO adjusts to fo with φDEMOUT = 90o and VVCOIN = 1/2 VCC (see Figure 2)
No Signal at the
PC2 VCO adjusts to fMIN with φDEMOUT = -360o and VVCOIN = 0V (see Figure 4)
SIGIN Input

PLL Frequency PC1 or PC2 Loop Filter Component Selection

Capture Range
R3 |F(jω)|

-1/τ
INPUT C2 OUTPUT

ω
(A) τ1 = R3 x C2 (B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM
A small capture range (2fc) is obtained if τ > 2fc ≈ (1/π) (2πfL/τ1.) 1/2
FIGURE 48. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET

R3
|F(jω)| R4
m=
R4 R3 + R4
INPUT OUTPUT -1/τ2 -1/τ3
C2 m

1/τ3 1/τ2 ω
(A) τ2 = R4 x C2; (B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM
τ3 = (R3 + R4) x C2

FIGURE 49. SIMPLE LOOP FILTER FOR PLL WITH OFFSET

PLL Locks on PC1 Yes

Harmonics at Center
PC2 No
Frequency
Noise Rejection at PC1 High
Signal Input
PC2 Low
AC Ripple Content PC1 fr = 2fi, large ripple content at φDEMOUT = 90o
when PLL is Locked
PC2 fr = fi, small ripple content at φDEMOUT = 0o

Lock Detector Circuit

The lock detector feature is very useful in data synchroniza-
tion, motor speed control, and demodulation. By adjusting
the value of the lock detector capacitor so that the lock out-
put will change slightly before actually losing lock, the
designer can create an “early warning” indication allowing
corrective measures to be implemented. The reverse is also
true, especially with motor speed controls, generators, and
clutches that must be set up before actual lock occurs or dis-
connected during loss of lock.
When using phase comparator 1, the detector will only indi-
cate a lock condition on the fundamental frequency and not
on the harmonics, which PC1 will lock on.

21
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