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 Eng. Res. Express 2 (2020) 016001 https://doi.org/10.1088/2631-8695/ab7b37

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Fully digital synchronous frequency doubler for FM stereo decoder

RECEIVED
29 November 2019
REVISED
Punithavathi Duraiswamy1,3 and Shankar Kumar Selvaraja2
17 February 2020 1
Department of ECE, M S Ramaiah University of Applied Sciences, India
2
ACCEPTED FOR PUBLICATION Center for Nano Science and Engineering, Indian Institute of Science, India
3
28 February 2020 Author to whom any correspondence should be addressed.
PUBLISHED E-mail: punithavathi.ec.et@msruas.ac.in and shankarks@iisc.ac.in
9 March 2020
Keywords: FM stereo, FIR, phase shifter, frequency doubler, duty cycle, FPGA

Abstract
In this paper, we present a fully digital synchronous architecture for doubling the frequency of a pilot
tone in FM stereo decoder. The proposed architecture uses two phase shifters ±45° and an X-OR gate.
A phase difference of 90° differential is obtained between the outputs of the phase shifters. The two
phase shifter outputs are edge combined by an X-OR operation to generate an output signal that has
twice the frequency of the input signal with 50% duty cycle. The phase shifters are implemented by a
pair of linear FIR filters having identical magnitude and orthogonal phase responses. Hardware
optimization of FIR filters are done to reduce the area overhead due to two filters. The frequency
doubling of pilot tone (19 KHz used in FM Stereo decoder) with 50% duty cycle is experimentally
verified using Spartan-6 FPGA. The proposed frequency doubler can be used only on receiver side of
communication system.

1. Introduction

Frequency doublers are often used in the transmitter of a communication system when the source or the signal
generator is unable to generate the signal at required operating frequency. Frequency doublers allow design of
signal generators to run at a lower frequency with the advantage of the increased frequency tuning range and
spectral purity On the receiver, it is mainly used to double the frequency of the received signal (i.e processing the
received signal). For applications such as in FM receiver, the stereo decoder is turned ON, if the pilot tone (19
KHz) is detected. In the stereo decoder, the pilot tone is doubled to generate the stereo encoding signal(38 KHz).
In digital domain, frequency doublers are implemented by delaying one of the inputs to X-OR gate. In a classic
delay X-OR gate approach, the input signal is passed through a chain of delays. The input signal and the delayed
signal are then edge combined using an X-OR logic gate [1–3]. At input of the X-OR gate, the two inputs need to
have 90° phase difference for frequency doubling as well as to obtain 50% duty cycle for the output [1]. In
FPGAs, for generating one clock pulse delay i.e, 360°, a register is required. For fractional delays that are less than
one clock pulse, asynchronous delays are used [1–3]. Use of asynchronous delays in the design results in jittery
output and does not guarantee 50% duty cycle as the process, voltage and temperature (PVT) is unstable [1–3].
In FPGA, asynchronous delays are designed using tri-state buffers. Moreover, only limited FPGA devices
support tri-state pull ups [1]. For doubling the pilot tone, phase Locked Loops (PLLs) or Delay Locked Loops
(DLLs) are used for better noise performance. However, the designs based on PLL/DLL are complex comprising
phase detector, up-down counter, oscillator and other control circuits [4–7]. Instead of using complex PLLs or
asynchronous delay element in the design of FM stereo decoder, phase shifter based frequency doublers can be
used. Phase shifters are implemented using Hilbert transform FIR or IIR filters [8–10]. One of the
implementation issues with Hilbert transform approach is that, one of the signal paths needs to be delayed by a
time equal to the processing time of the filter [11]. Moreover, passband ripples lead to amplitude errors/
mismatches between the pilot signal and its phase shifted version [10, 11]. As an alternative, we propose using
differential phase shifter to overcome the above stated implementation issue of Hilbert transform approach. The
phase shifter based frequency doubler is simple, however, itcannot be used in the transmitter as it cannot
generate frequencies more than the clock frequency as the FIR filters are limited to fs/2 clock operation. The

© 2020 IOP Publishing Ltd

Eng. Res. Express 2 (2020) 016001 P Duraiswamy and S K Selvaraja

Figure 1. Audio spectrum, decoder block diagram, and proposed frequency doubler circuit (a) Audio spectrum of stereo FM. (b) FM
stereo decoder. (c) Differential phase shifter based frequency doubler.

architectures to generate frequencies above the clock frequency in transmitter is reported in [1]. The proposed
differential phase shifter based frequency doubler is designed, optimized at hardware level and experimentally
verified on Spartan-6 FPGA and the results are presented.

2. FM stereo decoder

A frequency doubler circuit is required on the receiver side of a FM demodulator. The audio spectrum of a stereo
FM is shown in figure 1(a). The transmitter generates 38 KHz signal that is used to encode the stereo signals. It is
divided by two to generate the pilot tone of 19 KHz. The pilot tone is transmitted along with the FM signal. When
the receiver detects the pilot tone, it switches ON the stereo decoding circuit to decode the L(left) and R(right)
signals. In the stereo decoding circuit, the pilot signal has to be doubled to generate the 38KHz signal that was
used to generate the stereo signal in the transmitter. The decoder circuit uses filters, adder/subtractors and
multipliers to decode the stereo signal as shown in the figure 1(b). The frequency doubler in decoder can be
implemented using differential phase shifter. Two FIR filters are used to obtain a 90° differential shift. The
outputs I and Q from the FIR filter should be matched in amplitude and have a perfect 90° phase difference. The
two signals are then passed through an X-OR gate as shown in figure 1(c). Any mismatching/errors of I and Q
signal leads to amplitude and phase distortions resulting in noisy output. This may affect the quality of the sound
produced.

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Eng. Res. Express 2 (2020) 016001 P Duraiswamy and S K Selvaraja

Figure 2. Frequency response of a 45° in-phase FIR filter for N=26. A flat magnitude response is seen for the passband.

3. Differential phase shifter based frequency doubler

The proposed architecture for doubling the frequency of the pilot tone is shown in figure 1(c). The 19 KHz pilot
signal is passed through the two filters A(k) and B(k) that shifts the signal by +45° and -45° respectively. A
differential 90° phase difference is obtained between the two outputs I and Q. The two outputs are then passed
through the X-OR gate. The resulting output signal ( fout) would be twice (38 KHz) the input signal frequency
with 50% duty cycle. This fully digital synchronous frequency doubler can be used instead of complex PLL
circuits in an FM stereo decoder. As the filter pairs’ phase difference is key to our design, we adopt FIR filters as
they have linear phase response [11, 12]. The two FIR filters have equal magnitude response, orthogonal phases
with less phase error(0.04°) and the two filter coefficients are time reversed i.e., A(k)=B(−k). The in-phase
filter A(k) characteristics is shown in equation (1). A(k) is found by sampling (1) at time intervals equal to t=2π
(k−N−1/2).
⎧ 2 (w 2 - w1) , t = 0
⎪
⎪ a sin ⎡p 4 a + 2w 2 ⎤ - a sin ⎡p 4 a + 2w1 ⎤ , t = p
( ) ( )
⎪ ⎣ a ⎦ ⎣ a ⎦ 2a
A (t ) = ⎨ ⎡ - w 1 ⎤ ⎡ - w 2 ⎤ p (1)
⎪ a sin ⎣p 4
⎪ 2
( a
a
2
) ⎦ - a sin ⎣p 4
a
( a
2
)⎦ , t = - 2a
⎪ 2p 2cos (at )
⎩ t (4a t 2 - p 2) [sin (w1 t + p 4) - sin (w 2 t + p 4)] , otherwise

3.1. Design and FPGA implementation

To design the phase orthogonal FIR filters, the following specifications are used.

(i) Number of taps: 26 (even N is chosen)

(ii) Pass band (normalized): Centered around fs/4
(iii) Two half amplitude points ω1=0.05 and ω2=0.45
(iv) Transition region width 2a=0.1 rad/s

According to [11], specifications (1) and (2) makes the alternate coefficients value zero. The simulated frequency
response of the the in-phase filter is shown in figure 2. It is observed that the filter has flat magnitude response
without ripples. This gives a perfect matching of the amplitude of the two filter outputs (I and Q ). The proposed
differential phase shifter based frequency doubler is simulated in MATLAB and the simulation results are shown
in figure 3. A pilot frequency of 19 KHz is applied to the input of the architecture. The two filter outputs have a
phase difference of 89.9°. The X-OR output signal has a frequency of 37.03 KHz, which is twice that of the input
signal frequency. Since, alternate coefficients values of the filter is zero, the total number of constant
multiplications for the two filters reduces from 2N to N. For realizing the two filters in hardware, transposed FIR
filter structure (TDF) is used. In TDF architecture, the input is initially multiplied with all the coefficients
followed by a delay and then added. As two filters are time reversed, separate multipliers are not needed for the
second filter implementation. The multiplier outputs of first filter can be used for the second filter as well. This
further reduces the number of multipliers from N to N/2.
Figure 4 shows the proposed hardware architecture of the phase orthogonal filters of order N . Multiplier-
less architectures are used to reduce the hardware cost. The multipliers are implemented using shifters and
adders. For this, the filter coefficients are converted to powers of two using CSD algorithm [6]. In figure 4, there

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Eng. Res. Express 2 (2020) 016001 P Duraiswamy and S K Selvaraja

Figure 3. Simulation of proposed frequency doubler architecture using differential phase shifter.

Figure 4. Architecture of phase orthogonal Nth order FIR filters.

are two filters; Filter-I and Filter-Q. The shifter block and the coefficient adder/subtractor block forms the CSD
multiplier and the are common to both the filters Filter I and Filter Q. Separate tap adder block and delays are
used for the two filters. The shifter block contains 12 shifters (2−14 to 2−12). The CSD coefficient precision used is
12 bits. A 14bit representation is used for the input. The input is passed through all the shifters. The selected
shifted outputs are added or subtracted according to the coefficient value to get the CSD multiplication result.
Filter I and Q block require dedicated adders and delays to produce the right phase for the outputs. The CSD
multiplier outputs are delayed passed to the next tap adder. The proposed architecture in figure 4 is described in
VHDL and implemented on Spartan-6 FPGA. Using a clock of 80 MHz, the dual filter architecture performance
is verified with various input frequencies. Figure 5 shows the phase difference obtained from the simulation for
various input frequencies ranging between 0 and fs/2. It is seen the phase difference is exactly 90° when the input
signal is 20 MHz, i.e.fs/4 [11]. Choosing a sampling frequency in multiples of four of the input signal ensures 90°
phase shift and 50% duty cycle at the output of the frequency doubler. Table 1 compares the proposed dual filter
based approach of generating 90° phase shift with Hilbert transform approach which uses single filter. The dual
filter approach results in low phase error compared to the single filter approach. As the magnitude response of
the proposed filter is flat, the amplitude error is very less. The single filter approach is likely to give more
amplitude errors due to the ripples in the passband.

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Eng. Res. Express 2 (2020) 016001 P Duraiswamy and S K Selvaraja

Figure 5. Phase shifts obtained for various frequencies with 80 MHz clock.

Table 1. Comparison of results on FPGA platform

Design approach Magnitude response Filter order (N) Phase Error (Deg) Amplitude Error

(Dual filter This work) Flat passband 26 (always even) −0.2177(7MHZ) 0.0002

Hilbert transform (single filter) [10] Passband contains ripples 27 (always odd) 0.7(7MHz) Not reported

Figure 6. Measured pilot tone(18.94KHz) and encoding signal(37.59KHz).

4. Experimental results

To experimentally verify the frequency doubler for the use in FM stereo decoder, the architecture is
implemented on a Spartan-6 FPGA board. A19 KHz signal is given as an input to the two FIR filters. The filters
are clocked at the rate of 95 KHz. The 95 KHz clock is generated by dividing 19 MHz clock generated from Digital
Clock Manager (DCM) of Spartan-6. The two 16- bit filter outputs are edge combined using the X-OR gate. The
filter output contains multiple discrete levels and are reduced to 0 and 1 using threshold logic. Figure 6 shows a
measured 18.94 KHz pilot tone and the encoding signal of 37.59 KHz. As discussed earlier, the proposed
architecture gives 50% duty cycle. The experimental results agrees well with the simulation results. The
proposed architecture is compared with other available frequency generation/doubling methods and are shown
in table. 2. The methods are classified into asynchronous and synchronous designs. Our architecture is
synchronous and doubles the input frequency with guaranteed 50% duty cycle. Experimental results show very

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 Eng. Res. Express 2 (2020) 016001
Table 2. Comparison with the existing literature

S.No Design type Major architecture blocks Application Remarks

6

[2] Asynchronous Oscillator, delays and X-OR gate Oscillator based UWB generator PVT errors, No guaranteed 50% duty cycle

[3] Asynchronous Delays using gates and X-OR gate UWB generator PVT errors, No guaranteed 50% duty cycle

[10] Synchronous Single FIR filter 90° phase shifter Amplitude mismatches due to ripples at filter output. Requires additional delays for phase alignment

This work Synchronous Dual FIR filter and X-OR gate Frequency doubler No ripples at filter output and guaranteed 50% duty cycle. No additional delays required

P Duraiswamy and S K Selvaraja

Eng. Res. Express 2 (2020) 016001 P Duraiswamy and S K Selvaraja

less phase and amplitude distortions/error for the output of the doubler thus providing noise free sound in FM
stereo decoder.

5. Conclusion

A frequency doubler to be used on the receiver side of a communication system is proposed. The proposed
frequency doubling architecture for FM stereo decoder consists of a pair of phase orthogonal FIR phase shifters
and X-OR gate for doubling the frequency of the input signal. A synchronous delay matching of 90° differential
is generated by the FIR filters. Unlike conventional implementation, an area efficient high-speed multiplier-less
architecture is presented. The details of the filter parameters were also presented. The frequency shifts at various
frequencies within the FIR filter bandwidth is studied at the hardware level. It is confirmed that the architecture
preserves 50% duty cycle. Also, the architecture is simple, fully digital, synchronous and easily implementable in
all types of digital platform. Furthermore, the architecture is scalable to higher even-multiple frequencies by
cascading it.

ORCID iDs

Punithavathi Duraiswamy https://orcid.org/0000-0002-0786-3066

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