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82C55A FN2969
CMOS Programmable Peripheral Interface Rev 11.01
Jan 20, 2020
Ordering Information
PART NUMBERS
PART PART TEMP.
5MHz MARKING 8MHz MARKING RANGE (°C) PACKAGE PKG. DWG. #
CP82C55A-5Z (Note) CP82C55A-5Z CP82C55AZ (Note) CP82C55AZ 0 to +70 40 Ld PDIP (Pb-free) E40.6
IP82C55AZ (Note) IP82C55AZ -40 to +85 40 Ld PDIP (Pb-free)
CS82C55A-5Z* (Note) CS82C55A-5Z CS82C55AZ* (Note) CS82C55AZ 0 to +70 44 Ld PLCC (Pb-free)
N44.65
IS82C55A-5Z* (Note) IS82C55A-5Z IS82C55AZ* (Note) IS82C55AZ -40 to +85 44 Ld PLCC (Pb-free)
CQ82C55AZ (Note) CQ82C55AZ 0 to +70 44 Ld MQFP (Pb-free) Q44.10x10
IQ82C55AZ* (Note) IQ82C55AZ -40 to +85 44 Ld MQFP (Pb-free)
ID82C55A ID82C55A -40 to +85 40 Ld CERDIP F40.6
MD82C55A/B MD82C55A/B -55 to +125
8406602QA 8406602QA SMD#
8406602XA 8406602XA SMD# 44 Ld CLCC J44.A
*Add “96” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
82C55A (PDIP, CERDIP) 82C55A (CLCC)
TOP VIEW TOP VIEW
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
WR
PA3 1 40 PA4
RD
CS
PA2 2 39 PA5 6 5 4 3 2 1 44 43 42 41 40
PA1 3 38 PA6
GND 7 39 NC
PA0 4 37 PA7
NC 8 38 RESET
RD 5 36 WR
A1 9 37 D0
CS 6 35 RESET
A0 10 36 D1
GND 7 34 D0
PC7 11 35 D2
A1 8 33 D1
PC6 12 34 D3
A0 9 32 D2
PC5 13 33 D4
PC7 10 31 D3
PC4 14 32 D5
PC6 11 30 D4
PC0 15 31 D6
PC5 12 29 D5
PC1 16 30 D7
PC4 13 28 D6
PC2 17 29 NC
PC0 14 27 D7
PC1 15 26 VCC 18 19 20 21 22 23 24 25 26 27 28
PC2 PB7
PB3
PC3
PB0
PB1
PB2
PB4
PB5
PB6
PB7
16 25
NC
VCC
PC3 17 24 PB6
PB0 18 23 PB5
PB1 19 22 PB4
PB2 20 21 PB3
PA4
PA5
PA6
PA7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
WR
WR
RD
RD
NC
NC
6 5 4 3 2 1 44 43 42 41 40
CS 7 39 RESET
GND 8 38 D0 44 43 42 41 40 39 38 37 36 35 34
CS 1 33 RESET
A1 9 37 D1
A0 10 36 D2 GND 2 32 D0
PC7 11 35 D3 A1 3 31 D1
NC 12 34 NC
A0 4 30 D2
PC6 13 33 D4
PC5 14 D5 PC7 5 29 D3
32
PC4 15 31 D6 PC6 6 28 D4
PC0 16 30 D7
PC5 7 27 D5
PC1 17 29 VCC
PC4 8 26 D6
18 1920 21 22 23 24 25 26 27 28
PC0 9 25 D7
PC2
PC3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
10 24
NC
PC1 VCC
PC2 11 23 PB7
12 13 14 15 16 17 18 19 20 21 22
PC3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
NC
NC
NC
Pin Description
SYMBOL TYPE DESCRIPTION
VCC VCC: The +5V power supply pin. A 0.1F capacitor between VCC and GND is recommended for decoupling.
GND GROUND
D0-D7 I/O DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus.
RESET I RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the “Bus
Hold” circuitry turned on.
CS I CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU
communications.
RD I READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus.
WR I WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A.
A0-A1 I ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three
ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus
A0, A1.
PA0-PA7 I/O PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are present on this port.
PB0-PB7 I/O PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PC0-PC7 I/O PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
Functional Diagram
GROUP A
PORT C I/O
BIDIRECTIONAL PC7-PC4
UPPER
DATA BUS (4)
DATA BUS
D7-D0 BUFFER
8-BIT GROUP B
PORT C I/O
INTERNAL
PC3-PC0
DATA BUS LOWER
(4)
RD
READ
WR WRITE GROUP B
CONTROL CONTROL GROUP B I/O
A1
LOGIC PORT B PB7-PB0
A0 (8)
RESET
CS
the data or status information to the CPU on the data bus. In FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,
essence, it allows the CPU to “read from” the 82C55A. READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS
(WR) Write. A “low” on this input pin enables the CPU to write
data or control words into the 82C55A. Group A and Group B Controls
The functional configuration of each port is programmed by the
(A0 and A1) Port Select 0 and Port Select 1. These input
systems software. In essence, the CPU “outputs” a control
signals, in conjunction with the RD and WR inputs, control the
word to the 82C55A. The control word contains information
selection of one of the three ports or the control word register.
such as “mode”, “bit set”, “bit reset”, etc., that initializes the
They are normally connected to the least significant bits of the
functional configuration of the 82C55A.
address bus (A0 and A1).
Each of the Control blocks (Group A and Group B) accepts
82C55A BASIC OPERATION
“commands” from the Read/Write Control logic, receives
INPUT OPERATION “control words” from the internal data bus and issues the
A1 A0 RD WR CS (READ)
proper commands to its associated ports.
0 0 0 1 0 Port A Data Bus
Control Group A - Port A and Port C upper (C7 - C4)
0 1 0 1 0 Port B Data Bus
Control Group B - Port B and Port C lower (C3 - C0)
1 0 0 1 0 Port C Data Bus
The control word register can be both written and read as
1 1 0 1 0 Control Word Data Bus
shown in the “Basic Operation” table. Figure 4 shows the
OUTPUT OPERATION control word format for both Read and Write operations. When
(WRITE)
the control word is read, bit D7 will always be a logic “1”, as this
0 0 1 0 0 Data Bus Port A implies control word mode information.
0 1 1 0 0 Data Bus Port B Ports A, B, and C
1 0 1 0 0 Data Bus Port C The 82C55A contains three 8-bit ports (A, B, and C). All can be
1 1 1 0 0 Data Bus Control configured to a wide variety of functional characteristics by the
system software but each has its own special features or
DISABLE FUNCTION
“personality” to further enhance the power and flexibility of the
X X X X 1 Data Bus Three-State 82C55A.
X X 1 1 0 Data Bus Three-State Port A One 8-bit data output latch/buffer and one 8-bit data
input latch. Both “pull-up” and “pull-down” bus-hold devices are
(RESET) Reset. A “high” on this input initializes the control present on Port A. See Figure 2A.
register to 9Bh and all ports (A, B, C) are set to the input mode.
Port B One 8-bit data input/output latch/buffer and one 8-bit
“Bus hold” devices internal to the 82C55A will hold the I/O port
data input buffer. See Figure 2B.
inputs to a logic “1” state with a maximum hold current of
400A. Port C One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be divided into
two 4-bit ports under the mode control. Each 4-bit port contains
ADDRESS BUS
a 4-bit latch and it can be used for the control signal output and
status signal inputs in conjunction with ports A and B. See CONTROL BUS
Figure 2B.
DATA BUS
INPUT MODE
MASTER
RESET
OR MODE RD, WR D7-D0 A0-A1
CHANGE CS
82C55A
INTERNAL EXTERNAL
DATA IN PORT A PIN MODE 0 C
B A
INTERNAL
DATA OUT
(LATCHED) 8 I/O 4 I/O 4 I/O 8 I/O
OUTPUT MODE
PB7-PB0 PC3-PC0 PC7-PC4 PA7-PA0
FIGURE 2A. PORT A BUS-HOLD CONFIGURATION
MODE 1 C
B A
VCC
RESET
OR MODE 8 I/O 8 I/O
CHANGE P
PB7-PB0 CONTROL CONTROL PA7-PA0
OR I/O OR I/O
MODE 2 C
B A
INTERNAL EXTERNAL
DATA IN PORT B, C BI-
8 I/O DIRECTIONAL
PIN
INTERNAL
DATA OUT PB7-PB0 PA7-PA0
(LATCHED) CONTROL
OUTPUT MODE
FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE
FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION
FIGURE 2. BUS-HOLD CONFIGURATION
CONTROL WORD
Operational Description D7 D6 D5 D4 D3 D2 D1 D0
GROUP B
Mode Selection
There are three basic modes of operation than can be selected PORT C (LOWER)
1 = INPUT
by the system software: 0 = OUTPUT
Mode 0 - Basic Input/Output PORT B
1 = INPUT
Mode 1 - Strobed Input/Output 0 = OUTPUT
Mode 2 - Bidirectional Bus MODE SELECTION
0 = MODE 0
When the reset input goes “high”, all ports will be set to the 1 = MODE 1
input mode with all 24 port lines held at a logic “one” level by
internal bus hold devices. After the reset is removed, the GROUP A
82C55A can remain in the input mode with no additional PORT C (UPPER)
initialization required. This eliminates the need to pull-up or 1 = INPUT
0 = OUTPUT
pull-down resistors in all-CMOS designs. The control word
PORT A
register will contain 9Bh. During the execution of the system 1 = INPUT
program, any of the other modes may be selected using a 0 = OUTPUT
The modes for Port A and Port B can be separately defined, INTE Flip-Flop Definition
while Port C is divided into two portions as required by the Port (BIT-SET)-INTE is SET - Interrupt Enable
A and Port B definitions. All of the output registers, including
the status flip-flops, will be reset whenever the mode is (BIT-RESET)-INTE is Reset - Interrupt Disable
changed. Modes may be combined so that their functional NOTE: All Mask flip-flops are automatically reset during mode
definition can be “tailored” to almost any I/O structure. For selection and device Reset.
instance: Group B can be programmed in Mode 0 to monitor
simple switch closings or display computational results, Group Operating Modes
A could be programmed in Mode 1 to monitor a keyboard or Mode 0 (Basic Input/Output). This functional configuration
tape reader on an interrupt-driven basis. provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply written
The mode definitions and possible mode combinations may
to or read from a specific port.
seem confusing at first, but after a cursory review of the
complete device operation a simple, logical I/O approach will Mode 0 Basic Functional Definitions:
surface. The design of the 82C55A has taken into account
• Two 8-bit ports and two 4-bit ports
things such as efficient PC board layout, control signal
definition vs. PC layout and complete functional flexibility to • Any Port can be input or output
support almost any peripheral device with no external logic.
• Outputs are latched
Such design represents the maximum use of the available
pins. • Inputs are not latched
tIR tHR
INPUT
tAR tRA
CS, A1, A0
D7-D0
tRD tDF
tWD
tDW
D7-D0
tAW tWA
CS, A1, A0
OUTPUT
tWB
Mode 0 Configurations
CONTROL WORD #0 CONTROL WORD #2
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0
8 8
A PA7 - PA0 A PA7 - PA0
82C55A 82C55A
4 4
PC7 - PC4 PC7 - PC4
D7 - D0 C D7 - D0 C
4 4
PC3 - PC0 PC3 - PC0
8 8
B PB7 - PB0 B PB7 - PB0
8 8
A PA7 - PA0 A PA7 - PA0
82C55A 82C55A
4 4
PC7 - PC4 PC7 - PC4
D7 - D0 C D7 - D0 C
4 4
PC3 - PC0 PC3 - PC0
8 8
B PB7 - PB0 B PB7 - PB0
8 8
A PA7 - PA0 A PA7 - PA0
82C55A 82C55A
4 4
PC7 - PC4 PC7 - PC4
D7 - D0 C D7 - D0 C
4 4
PC3 - PC0 PC3 - PC0
8 8
B PB7 - PB0 B PB7 - PB0
8 8
A PA7 - PA0 A PA7 - PA0
82C55A 82C55A
4 4
PC7 - PC4 PC7 - PC4
D7 - D0 C D7 - D0 C
4 4
PC3 - PC0 PC3 - PC0
8 8
B PB7 - PB0 B PB7 - PB0
8 8
A PA7 - PA0 A PA7 - PA0
82C55A 82C55A
4 4
PC7 - PC4 PC7 - PC4
D7 - D0 C D7 - D0 C
4 4
PC3 - PC0 PC3 - PC0
8 8
B PB7 - PB0 B PB7 - PB0
8 8
A PA7 - PA0 A PA7 - PA0
82C55A 82C55A
4 4
PC7 - PC4 PC7 - PC4
D7 - D0 C D7 - D0 C
4 4
PC3 - PC0 PC3 - PC0
8 8
B PB7 - PB0 B PB7 - PB0
8 8
A PA7 - PA0 A PA7 - PA0
82C55A 82C55A
4 4
PC7 - PC4 PC7 - PC4
D7 - D0 C D7 - D0 C
4 4
PC3 - PC0 PC3 - PC0
8 8
B PB7 - PB0 B PB7 - PB0
8 8
A PA7 - PA0 A PA7 - PA0
82C55A 82C55A
4 4
PC7 - PC4 PC7 - PC4
D7 - D0 C D7 - D0 C
4 4
PC3 - PC0 PC3 - PC0
8 8
B PB7 - PB0 B PB7 - PB0
Operating Modes
MODE 1 (PORT A)
Mode 1 - (Strobed Input/Output). This functional configuration
provides a means for transferring I/O data to or from a PA7-PA0 8
CONTROL WORD
specified port in conjunction with strobes or “hand shaking” D7 D6 D5 D4 D3 D2 D1 D0 INTE STBA
PC4
signals. In mode 1, port A and port B use the lines on port C to A
1 0 1 1 1/0
generate or accept these “hand shaking” signals. PC6, PC7
PC5 IBFA
1 = INPUT
Mode 1 Basic Function Definitions: 0 = OUTPUT
PC3 INTRA
• Two Groups (Group A and Group B)
RD 2
• Each group contains one 8-bit port and one 4-bit control/data PC6, PC7 I/O
port
• The 8-bit data port can be either input or output. Both inputs
MODE 1 (PORT B)
and outputs are latched.
PB7-PB0 8
• The 4-bit port is used for control and status of the 8-bit port. CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0 INTE PC2
Input Control Signal Definition 1 1 1
B STBB
(Figures 6 and 7) PC1 IBFB
RD
IBF (Input Buffer Full F/F)
A “high” on this output indicates that the data has been loaded
into the input latch: in essence, an acknowledgment. IBF is set FIGURE 6. MODE 1 INPUT
by STB input being low and is reset by the rising edge of the
RD input.
tST
STB
tSIB
IBF
tSIT tRIB
INTR
tRIT
RD
tPH
INPUT FROM
PERIPHERAL
tPS
port. This does not mean valid data is sent out of the port at 1 = INPUT
0 = OUTPUT
this time since OBF can go true before data is available. Data INTRA
PC3
is guaranteed valid at the rising edge of OBF, (See Note 1).
WR 2
The OBF F/F will be set by the rising edge of the WR input and PC4, PC5
reset by ACK input being low.
WR
tWOB
WR
tAOB
OBF
INTR tWIT
ACK
tAK tAIT
OUTPUT
tWB
PA7-PA0 8 PA7-PA0 8
Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications.
FIGURE 10. COMBINATIONS OF MODE 1
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
PC3 INTRA
1 1 1/0 1/0 1/0
PA7-PA0 8
PC7 OBFA
INTE PC6
PC2-PC0 1 ACKA
1 = INPUT
0 = OUTPUT
INTE
PORT B 2 PC4 STBA
1 = INPUT
0 = OUTPUT PC5 IBFA
WR
GROUP B MODE
0 = MODE 0
1 = MODE 1 3
PC2-PC0 I/O
RD
DATA FROM
CPU TO 82C55A
WR
tAOB
OBF
tWOB
INTR
tAK
ACK
tST
STB
tSIB
IBF
tAD
tKD
tPS
PERIPHERAL
BUS
tPH tRIB
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF MASK STB RD + OBF MASK
ACK WR)
FIGURE 13. MODE 2 (BIDIRECTIONAL)
PA7-PA0 8 PA7-PA0 8
1 1 0 1 1/0 1 1 0 0 1/0
PC4 STBA PC4 STBA
PA7-PA0 8 PA7-PA0 8
PB7-PB0 8 PB7-PB0 8
1 or 2, Port C generates or accepts “hand shaking” signals with Applications of the 82C55A
the peripheral device. Reading the contents of Port C allows
The 82C55A is a very powerful tool for interfacing peripheral
the programmer to test or verify the “status” of each peripheral
equipment to the microcomputer system. It represents the
device and change the program flow accordingly.
optimum use of available pins and is flexible enough to
There is not a special instruction to read the status information interface almost any I/O device without the need for additional
from Port C. A normal read operation of Port C is executed to external logic.
perform this function.
Each peripheral device in a microcomputer system usually has
a “service routine” associated with it. The routine manages the
INTERRUPT ALTERNATE PORT C software interface between the device and the CPU. The
ENABLE FLAG POSITION PIN SIGNAL (MODE) functional definition of the 82C55A is programmed by the I/O
INTE B PC2 ACKB (Output Mode 1) service routine and becomes an extension of the system
or STBB (Input Mode 1) software. By examining the I/O devices interface
INTE A2 PC4 STBA (Input Mode 1 or Mode characteristics for both data transfer and timing, and matching
2) this information to the examples and tables in the detailed
INTE A1 PC6 ACKA (Output Mode 1 or
operational description, a control word can easily be developed
Mode 2) to initialize the 82C55A to exactly “fit” the application. Figures
18 through 24 present a few examples of typical applications of
FIGURE 17. INTERRUPT ENABLE FLAGS IN MODES 1 AND 2
the 82C55A.
INTERRUPT
REQUEST
PC3 PA0
PA1
HIGH SPEED
PA2 PRINTER
PA3
PA4
PA5
MODE 1
PA6
(OUTPUT)
PA7 HAMMER
RELAYS
PC7 DATA READY
PC6 ACK
PC5 PAPER FEED
PC4 FORWARD/REV.
82C55A
PB0
PB1
PB2
PB3
PB4
MODE 1 PB5 PAPER FEED
(OUTPUT) PB6 FORWARD/REV.
PB7 RIBBON
CARRIAGE SEN.
PC1 DATA READY
PC2 ACK
PC0
INTERRUPT
REQUEST
PC3 PA0 R0
PA1 R1
PA2 R2
FULLY
PA3 R3 DECODED INTERRUPT
PA4 R4 KEYBOARD REQUEST
PA5 R5
MODE 1 PC3 PA0 R0
(INPUT) PA6 SHIFT
PA1 R1
PA7 CONTROL
PA2 R2
FULLY
PA3 R3 DECODED
PC4 STROBE
PA4 R4 KEYBOARD
PC5 ACK
PA5 R5
MODE 1 PA6
(INPUT) SHIFT
82C55A PA7 CONTROL
PB0 B0
PC4 STROBE
PB1 B1
82C55A PC5 ACK
PB2 B2 BURROUGHS PC6 BUST LT
PB3 B3 SELF-SCAN
DISPLAY PC7 TEST LT
PB4 B4
MODE 1 PB5 B5
PB0 TERMINAL
(OUTPUT) PB6 BACKSPACE ADDRESS
PB1
PB7 CLEAR PB2
PB3
PC1 DATA READY MODE 0
(INPUT) PB4
PC2 ACK PB5
PC6 BLANKING PB6
PC7 CANCEL WORD PB7
INTERRUPT
REQUEST
FIGURE 19. KEYBOARD AND DISPLAY INTERFACE FIGURE 20. KEYBOARD AND TERMINAL ADDRESS
INTERFACE
INTERRUPT
REQUEST
FIGURE 21. DIGITAL TO ANALOG, ANALOG TO DIGITAL FIGURE 22. BASIC CRT CONTROLLER INTERFACE
INTERRUPT INTERRUPT
REQUEST REQUEST
FIGURE 23. BASIC FLOPPY DISC INTERFACE FIGURE 24. MACHINE TOOL CONTROLLER INTERFACE
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
II Input Leakage Current VIN = VCC or GND, RD, CS, A1, A0, RESET, WR -1.0 +1.0 A
TA = -55°C 50 450 A
TA = +128°C 50 400 A
ICCSB Standby Power Supply Current VCC = 5.5V, VIN = VCC or GND. Output Open - 10 A
ICCOP Operating Power Supply Current TA = +25°C, VCC = 5.0V, Typical (See Note 3) - 1 mA/MHz
NOTES:
2. No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current.
3. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0s I/O Read/Write cycle time = 1mA).
4. Tested as VOH at -2.5mA.
Capacitance TA = +25°C
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS
AC Electrical Specifications VCC = +5V 10%, GND = 0V; TA = Operating Temperature Range
82C55A-5 82C55A
TEST
SYMBOL PARAMETER MIN MAX MIN MAX UNITS CONDITIONS
READ TIMING
WRITE TIMING
OTHER TIMING
NOTE: Period of initial Reset pulse after power-on must be at least 50sec. Subsequent Reset pulses may be 500ns minimum.
Timing Waveforms
tRR (3)
RD
D7-D0
tWW (9)
WR
tWD (11)
tDW
(10)
D7-D0
OUTPUT
tWS (12)
tST (16)
STB
tSIB
IBF (23)
tSIT
(26) tRIB (24)
INTR tRIT
(25)
RD tPH
(18)
INPUT FROM
PERIPHERAL
tPS (17)
tWOB (21)
WR
tAOB (22)
OBF
INTR tWIT
(28)
ACK
tAK (15) tAIT (27)
OUTPUT
tWB (12)
DATA FROM
CPU TO 82C55A
WR
(NOTE)
tAOB
(22)
OBF
tWOB
(21)
INTR
tAK
(15)
ACK
tST
(16)
STB
(NOTE)
tSIB
IBF (23)
tAD (19)
tKD
tPS (17) (20)
PERIPHERAL
BUS
tPH (18) tRIB (24)
RD
DATA FROM DATA FROM
PERIPHERAL TO 82C55A 82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF MASK STB RD OBF MASK
ACK WR)
A0-A1,
CS A0-A1,
CS
tAW (7) tWA (8)
tAR (1) tRA (2)
DATA
BUS tRR (3)
RD
tDW (10) tWD (11)
(4) tRD tDF (5)
WR
DATA VALID
BUS
tWW (9) HIGH IMPEDANCE
Burn-In Circuits
CERDIP CLCC
F11
F12
F13
F14
F6 1 40 F11
F3
F4
F9
F8
F7
F6
F2
F7 2 39 F12
F8 3 38 F13
F9 4 37 F14
F4 5 36 F2 6 5 4 3 2 1 44 43 42 41 40
F3 6 35 F5 GND 7 39
GND 7 34 F15 8 38 F5
F0 8 33 F11 F0 9 37 F15
F1 9 32 F12 F1 10 36 F11
F10 10 31 F13 F10 11 35 F12
11 30 F6 12 34 F13
F6 F14
F7 13 33 F14
F7 12 29 F15
F8 14 32 F15
F8 13 28 F11
F9 15 31 F11
F9 14 27 F12
VCC F10 16 30 F12
F10 15 26
F6 17 29
F6 16 25 F13 C1 18 19 20 21 22 23 24 25 26 27 28
F7 17 24 F14
F8 18 23 F15
F9 19 22 F11 C1
F10 20 21 F12
F7
F8
F9
F10
F12
F15
F14
F13
F11
VCC
NOTES: NOTES:
1. VCC = 5.5V 0.5V 1. C1 = 0.01F minimum
2. VIH = 4.5V 10% 2. All resistors are 47k 5%
3. VIL = -0.2V to 0.4V 3. f0 = 100kHz 10%
4. GND = 0V 4. f1 = f0 2; f2 = f1 2; . . . ; f15 = f14 2
CS RESET
D0
GND
D1
A1 D2
A0 D3
PC7 D4
PC6 D5
PC5 D6
PC4 D7
PC0
VCC
PC1
PC2 PC3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
SECTION A-A
b1 0.014 0.023 0.36 0.58 3
bbb S C A-B S D S
b2 0.045 0.065 1.14 1.65 -
D
BASE b3 0.023 0.045 0.58 1.14 4
PLANE Q
-C- A c 0.008 0.018 0.20 0.46 2
SEATING
PLANE L c1 0.008 0.015 0.20 0.38 3
S1 D - 2.096 - 53.24 5
A A eA
b2 E 0.510 0.620 12.95 15.75 5
b e eA/2 c e 0.100 BSC 2.54 BSC -
ccc M C A-B S D S aaa M C A - B S D S eA 0.600 BSC 15.24 BSC -
eA/2 0.300 BSC 7.62 BSC -
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat- L 0.125 0.200 3.18 5.08 -
ed adjacent to pin one and shall be located within the shaded Q 0.015 0.070 0.38 1.78 6
area shown. The manufacturer’s identification shall not be used
S1 0.005 - 0.13 - 7
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be 90o 105o 90o 105o -
measured at the centroid of the finished lead surfaces, when aaa - 0.015 - 0.38 -
solder dip or tin plate lead finish is applied.
bbb - 0.030 - 0.76 -
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. ccc - 0.010 - 0.25 -
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a M - 0.0015 - 0.038 2, 3
partial lead paddle. For this configuration dimension b3 replaces N 40 40 8
dimension b2.
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
0.010 S E H S
J44.A MIL-STD-1835 CQCC1-N44 (C-5)
44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
D
INCHES MILLIMETERS
D3
SYMBOL MIN MAX MIN MAX NOTES
j x 45o
A 0.064 0.120 1.63 3.05 6, 7
A1 0.054 0.088 1.37 2.24 -
B 0.033 0.039 0.84 0.99 4
B1 0.022 0.028 0.56 0.71 2, 4
0.042 (1.07)
0.042 (1.07)
0.048 (1.22)
0.056 (1.42) 0.004 (0.10) C N44.65 (JEDEC MS-018AC ISSUE A)
PIN (1) IDENTIFIER 44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
0.050 (1.27) TP 0.025 (0.64)
R
C 0.045 (1.14) INCHES MILLIMETERS
L
SYMBOL MIN MAX MIN MAX NOTES
A 0.165 0.180 4.20 4.57 -
D2/E2 A1 0.090 0.120 2.29 3.04 -
C
L D 0.685 0.695 17.40 17.65 -
E1 E
D1 0.650 0.656 16.51 16.66 3
D2/E2 D2 0.291 0.319 7.40 8.10 4, 5
VIEW “A” E 0.685 0.695 17.40 17.65 -
E1 0.650 0.656 16.51 16.66 3
0.020 (0.51)
E2 0.291 0.319 7.40 8.10 4, 5
MIN
D1 A1 N 44 44 6
D A
SEATING Rev. 2 11/97
0.020 (0.51) MAX -C- PLANE
3 PLCS 0.026 (0.66)
0.032 (0.81) 0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
0.045 (1.14) MIN
MIN
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
D
D1 Q44.10x10 (JEDEC MS-022AB ISSUE B)
-D- 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A - 0.096 - 2.45 -
A1 0.004 0.010 0.10 0.25 -
-A- -B- A2 0.077 0.083 1.95 2.10 -
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