Journal of Electrical Engineering & Technology

https://doi.org/10.1007/s42835-019-00272-0

ORIGINAL ARTICLE

Prognostics of Power MOSFET Using Artificial Neural Network

Approach
Neeraj Khera1   · Shakeb A. Khan2

Received: 26 February 2019 / Revised: 7 July 2019 / Accepted: 24 August 2019

© The Korean Institute of Electrical Engineers 2019

Abstract
This paper presents the prognostics of in-circuit power MOSFETs in power electronic systems using artificial neural network
(ANN). Recent industrial surveys on reliability of power electronic systems shows that the switching transistors are one of
most life-limiting component and thermal stress is major cause for their parametric degradation. The on-state drain-source
resistance ­(Rds(on)) is an important fault signature parameter of power MOSFET which increases with its junction tempera-
ture rise. In this work, ANN is used to estimate variation in R
­ ds(on) of target MOSFETs at different operating conditions. The
data set for training and testing of proposed back-propagation trained artificial neural network are experimentally obtained
from the developed test bed. Using test bed, the electrical stressed based accelerated aging test is performed on target power
MOSFETs by subjecting them to repetitive unclamped inductive switching at different operating frequency and temperature.
After off-line training, the proposed ANN is implemented using National Instruments LabVIEW software to estimate real-
time ­Rds(on) values of in-circuit MOSFETs. For this purpose, voltage fed half bridge inverter circuit is designed and target
MOSFETs are taken at output section of the circuit. A low cost microcontroller is programmed for acquiring and serially
transmitting the real-time data set of target MOSFETs to the LabVIEW software. The performance of the proposed method
is evaluated in real time by comparing the ANN estimated R ­ ds(on) value with the experimental obtained value for in-circuit
target MOSFETs at test condition.

Keywords  Accelerated aging · Artificial neural network · Back-propagation · On-state drain-source resistance · Prognostics

1 Introduction of power electronic systems shows that most of the system

Power electronic systems are employed in critical applica-
tions that require the use of highly reliable components. The
whole system reliability is largely dependent on few high
failure rate components [1]. Reliability of power electronic
components is determined from their parametric degrada-
tion at the end of useful life or wear-out condition [2–4].
Accelerated aging test (ALT) are widely used in reliability
domain for power electronics and semiconductor industry
to estimate the expected lifetimes of the critical components
as well as to determine their operating conditions. Recent
industrial surveys conducted to determine the reliability
* Neeraj Khera
nkhera@amity.edu
1
Department of Electronics and Communication Engineering,
Amity University, Noida, Uttar Pradesh 201303, India
2
Department of Electrical Engineering, Jamia Millia Islamia,
Central University, Delhi 110025, India
failures occur due to the wear out of switching transistors
and the thermal stress is major cause for their parametric
degradation [5, 6]. At high power density, the power MOS-
FETs (Metal Oxide Semiconductor Field Effect Transis-
tors) are preferred switching transistors in power converter
circuits operating at the high switching frequencies due
to their low gate drive power requirement, fast switching
speed, low switching loss and superior paralleling capabil-
ity [7]. In recent studies [8–12], the accelerated aging tests
are performed to characterize the aging process of power
transistors and it has been concluded from experimental
results that their actual in-circuit life is much different than
stated by manufacturers in their datasheet. In [13], a new
precursor based on gate oxide degradation is identified for
on-line condition monitoring of power MOSFET. Thermal
stress based accelerated aging [14–16] and electrical stress
based accelerated aging [17] are performed to determine
the condition of target power MOSFETs based on the vari-
ation of ­Rds(on) value with junction temperature. In [18],

13
Vol.:(0123456789)

the dataset for junction temperature, drain-source voltage,
and drain current is experimentally monitored for the target
MOSFET. The dataset is used in Saber simulation tool to
obtain the electro-thermal model of MOSFET. The rela-
tion between R ­ ds(on) and junction temperature is obtained
which shows that R ­ ds(on) value is directly proportional to
junction temperature. To enhance the reliability of power
MOSFETs in power electronic converters, their in-circuit
condition needs to be continuously monitored. This paper
presents ANN model to determine the R ­ ds(on) value of in-cir-
cuit power MOSFETs at real-time operating conditions from
both onsite and remote location. In this paper artificial neu-
ral network (ANN) approach is presented for determining
the variation in the on-state drain-source resistance (­ Rds(on))
of target power MOSFETs at different operating frequency
and junction temperature. R ­ ds(on) value is an important fault
signature parameter in power MOSFET that increases with
the increase in its junction temperature. The input and out-
put datasets for implementing the ANN estimated ­Rds(on)
value at test conditions are experimentally obtained from
the developed test bed. Using the test bed, target power
MOSFETs are subjected to the repetitive unclamped induc-
tive switching (UIS) based accelerated aging test at differ-
ent operating frequencies. From the resulting input data sets
obtained at different test conditions, ANN is trained using
back-propagation training algorithm to estimate the R ­ ds(on)
values for target MOSFETs. Back-propagation is an exten-
sion of the least mean squares (LMS) algorithm for multi-
layer perceptron. Back-propagation training of three layers
ANN has been done by selecting different parameters like
learning rate, momentum term and number of hidden layer
neurons and their performance is evaluated to find the best
fit of ANN model for the R ­ ds(on) estimation of target MOS-
FETs. Subsequently, weights of trained ANN are used to
implement it for estimating the R ­ ds(on) of target MOSFETs in
the real-time using LabVIEW software and data acquisition
system. For this purpose a voltage fed half bridge inverter
circuit is designed [19] with overload protection and iso-
lated gate drive switching circuit. A low cost microcontroller
is programmed for acquiring and serially transmitting the
real-time operating data set of target MOSFETs at the out-
put section of half bridge inverter circuit to the LabVIEW
software installed at host computer. In order to facilitate the
web based condition monitoring of MOSFETs, the control
of running state front panel virtual instrument (VI) file hav-
ing the ANN estimated output R ­ ds(on) values is continuously
transferred from local host to the client over the internet as a
HTML file using web publishing tool of LabVIEW. Finally,
the implementation is validated in real time by comparing
the ANN estimated R ­ ds(on) with its practical in-circuit value
at test condition. The proposed ANN based scheme is very
useful for in-circuit health monitoring of power MOSFETs
in power electronics circuits from both onsite and remote
13
Journal of Electrical Engineering & Technology
locations and can be extended for health monitoring of other
critical circuit components in power electronic systems with
suitable training.
2 Parametric Degradation Failure in Power
MOSFET
The understanding of the failure mechanisms in the MOS-
FETs will aid in determining of the critical fault signature
parameter and based on its parametric degradation, their in-
circuit condition based maintenance can be performed. As
stated earlier, thermal stress is the most important factor
that causes the failure of power MOSFETs. The junction
temperature rise leads to the degradation of power MOSFET
due to the die attachment degradation. It is reported in [20]
that the die attachment degradation results in the increase
of the ­Rds(on) value. The increase of the drain source resist-
ance increases the conduction losses that produce localized
hot spots in MOSFETs causing its failure due to secondary
breakdown. Thermal stress based degradation due to con-
duction losses in power MOSFET causing the localized hot
spots is observed using the scanning-electron microscope
(SEM) [21] and the damaged chip of MOSFET is shown
in Fig. 1,
Rds(on) is therefore the critical fault signature in power
MOSFET that increases with the increase in the junction
temperature of transistor. At wear out condition of power
MOSFET, its R ­ ds(on) value becomes equal to maximum rated
value due to increase in conduction losses and hence the
junction temperature. Therefore, the variation in the on-state
drain-source resistance value from initial (pristine condi-
tion) value to the maximum rated value (weak condition)
of the MOSFET corresponds to its wear-out or degradation
failure. The experimental measurement of in-circuit R ­ ds(on)
Fig. 1  SEM photograph showing thermal damage
Journal of Electrical Engineering & Technology
value for the target MOSFETs is presented at test conditions
in Sect. 3.
3 Experimental Measurement of In‑circuit
­Rds(on) For Target MOSFETs
In this section, real-time in-circuit condition monitoring of
target MOSFETs due to electrical stress based repetitive
unclamped inductive switching test is presented. The electri-
cal stress based accelerated aging test of power MOSFETs is
performed using the microcontroller based test bed in which
the target MOSFETs are subjected to repetitive UIS [22].
Schematic diagram of developed test bed used to perform
the aging of power MOSFETs due to the repetitive UIS is
shown in the Fig. 2.
Fig. 2  Schematic diagram of Test bed
Fig. 3  Hardware Assembly of
Test Bed
Using the test bed, two samples of target power MOS-
FETs ­(D2 package of STP 7NK60Z) from ST Microelec-
tronics are subjected to the repetitive UIS at different fre-
quencies. The isolated gate drive pulses for the MOSFET
is supplied from microcontroller based variable frequency
pulse generator circuit. The variable frequency square pulses
of 2 kHz, 4 kHz, 8 kHz, 10 kHz and 15 kHz are obtained
by programming the timer of the microcontroller to obtain
desired switching frequency in accordance to the on state
of the respective frequency selector switch. The generated
switching frequency pulses are amplified using power tran-
sistor BC547 and are isolated by the opto-isolator, MCT2E.
These pulses are finally provided to the gate drive of MOS-
FET of the repetitive UIS circuit. The hardware assembly of
test bed is shown in Fig. 3.
UIS causes avalanche energy dissipation in MOSFET that
introduces thermal cycle in it resulting in the increase of its
junction temperature. The test parameters data values for
case temperature (­ Tcase), drain-to-source voltage (­ VDS) and
drain-to-source current ­(IDS) are monitored after half hour of
the aging test at different test frequencies. The thermal data
for the case temperature is acquired precisely using linear
integrated-circuit based analog temperature sensor; LM35
which is glued on metal case of target MOSFETs. LM35
is interfaced with microcontroller based data acquisition
(DAQ) card that is programmed to acquire the case tem-
perature at different frequencies after the test interval. Case
temperature value are displayed on liquid crystal display
(LCD) interfaced with DAQ card and are also stored as text
file by serially transmitting them from microcontroller to the
HyperTerminal application program of Windows installed
on host computer. The voltage and current waveforms for
the drain-source current (­ IDS) and the drain-source voltage
­(VDS) for target MOSFETs are captured at test frequencies
13

Fig. 4  Drain-source current through MOSFET for repetitive UIS test
at 4 kHz
Fig. 5  Drain-source voltage across MOSFET for repetitive UIS test at
4 kHz
on digital storage oscilloscope (DSO) that is having the
universal serial bus (USB) based external memory slot for
interfacing flash memory. The drain-source current (­ IDS)
is monitored using metal film current sense resistor of 1Ω.
Snapshots of stored waveforms for I­ DS and V­ DS waveforms
of aging test at 4 kHz and 8 kHz repetitive UIS switching
frequency are shown in Fig. 4, 5, 6 and 7,
The rise in the junction temperature due to thermal cycles
over a period of time can be obtained from the case tempera-
ture using the empirical relationship [23] given in relation
(1) as,
Tjmax = Tcase + IDS ⋅ VDS ⋅ R𝜃JC
where,
Tj = Junction to case temperature;
13
Journal of Electrical Engineering & Technology
Fig. 6  Drain-source current through MOSFET for repetitive UIS test
at 8 kHz
Fig. 7  Drain-source voltage across MOSFET for repetitive UIS test at
8 kHz
Tcase  = Case (flange) temperature of the transistor
(obtained from experiment);
RθJC = Thermal resistance for the junction-to-case of the
transistor from datasheet of STP 7NK60Z (1 °C/W for D ­ 2
and TO-220 Package);
IDS = Drain-to-source current (from experiment); and,
VDS = Drain-to-source voltage (from experiment)
The surface mount ­D2 and TO-220 Package of the target
power MOSFETs (STP 7NK60Z) is taken in this study that
have the junction-to-case thermal resistance of 1 °C/W.
Therefore the product of ­RθJC, and conduction loss in rela-
(1)
tion (1) can be neglected and the junction temperature is
approximated as case temperature for the target MOSFET.
The increase in the junction temperature causes increase
Journal of Electrical Engineering & Technology

Table 1  Variations in R
­ ds(on) Repetitive UIS Monitored parameters for STP 7NK60Z Monitored parameters for STP 7NK60Z
values due to repetitive UIS at test frequency (Sample-1) (Sample-2)
test conditions
F(in kHz) Junction tempera- On-state drain-source Junction tempera- On-state drain-source
ture ­TJ (in  °C) resistance R
­ ds(on)(Ω) ture ­TJ (in °C) resistance R
­ ds(on)(Ω)

2 99.4 2.35 97.9 2.32

4 93.6 2.25 92.7 2.24
8 91.5 2.22 89.1 2.18
10 83.7 2.10 84.2 2.11
15 77.4 2.01 76.1 1.99

in on-state drain source resistance R

­ ds(on) [24] of the MOS- where,
FET as per relation (2), T J  = Junction temperature (approximated as case
( ) temperature);
Rds(on) (25 °C) = Rds(on) at 25 °C given in datasheet; and
◦
Rds(on) Tj = Rds(on) (25 ◦ C) ⋅ (1 + 𝛼∕100)Tj −25 C (2)

Fig. 8  Flow Chart to Implement

ANN Model for determining Start
­Rds(on) of MOSFETs

Define Input and Output parameters

Normalize Input and Output data

Specify ANN Architecture

Perform LM based back-propagation training of ANN

Validate the Network with new input dataset

Modify parameters: BPNN

Learning rate; Momentum Results are
term; No. of hidden layer Satisfactory
neurons

Implementation of trained BPNN for Rds(on) calculation

of MOSFETs in LabVIEW

Stop

13
 Journal of Electrical Engineering & Technology

⎡ e11 e21 … eK1 ⎤

⎢ e12 e22 … eK2 ⎥
E=⎢ ⎥
⋮ ⋮ ⋮ (3)
⎢ ⎥
⎣ e1P e2P eKP ⎦

[K ]
∑
P
∑( )2 ( )
F(w) = dkp − okp = ET E (4)
p=1 k=1

where,
E = Cumulative error vector (for all input patterns);
dkp = Desired value of kth output and pth pattern;
okp = Actual value of kth output and pth pattern;
ekp= ­(dkp − okp); k = 1,2…K; p = 1,2…P; and,
Fig. 9  Architecture for ANN
F(w) = Sum of squares of errors.
From relation (4), the Jacobian matrix is obtained that is
further used to update the weights. Jacobian matrix is given
in (5) as,
α = Temperature coefficient calculated from sets of ­(TJ1,
­Rds(on1)) and ­(TJ2, ­Rds(on2)) from relationship curves given in
⎡ 𝜕e11 𝜕e11
⋯ ⎤
𝜕e11
datasheet of STP 7NK60Z. ⎢ 𝜕e
𝜕w1 𝜕w2
⎥
𝜕wN
𝜕e21 𝜕e21
From the junction temperature, the R ­ ds(on) values for target ⎢ 𝜕w21 𝜕w2
⋯ ⎥
𝜕wN
MOSFETs at test conditions are empirically obtained by using ⎢ 1 ⎥
⎢ 𝜕e⋮ ⋮ ⋯ ⋮ ⎥
relation (2). The value of temperature coefficient (α) for STP ⎢ K1 𝜕eK1
⋯ 𝜕w ⎥
𝜕eK1

7NK60Z is calculated from its datasheet and is obtained as 0.7 ⎢ 𝜕w1 𝜕w2 N ⎥

while its initial value of ­Rds(on) is 1.4Ω at continuous drain cur-

J=⎢ ⋮ ⋮ ⋯ ⋮ ⎥ (5)
⎢ 𝜕e1P 𝜕e1P
⋯ 𝜕w1P ⎥
𝜕e
rent of 200 mA and case temperature of 25 °C. The experimen- ⎢ 𝜕e
𝜕w1 𝜕w2 N ⎥

tal aging test results obtained for variations in R ­ ds(on) values of ⎢ 2P 𝜕e2P
⋯
𝜕e2P
⎥
⎢ 𝜕w1 𝜕w2 𝜕wN ⎥
two samples of target power MOSFETs at different switching ⎢ ⋮ ⋮ ⋯ ⋮ ⎥
frequency and the junction temperature are shown in Table 1. ⎢ 𝜕eKP 𝜕eKP
⋯ 𝜕wKP ⎥⎦
𝜕e
⎣ 𝜕w1 𝜕w2 N

4 Implementation of ANN Model for ­Rds(on)

Calculation of Target MOSFETs

In this section, the application of Levenberg–Marquardt (LM) The weights update from nth to (n + 1)th iteration is given
based back-propagation trained artificial neural network by relation (6) as,
(BPNN) model [25] for estimating the on-state drain-source [( )−1 ]
resistance of target MOSFETs at different operating frequency Wn+1 = Wn − JTn Jn + μn I JTn En (6)
and junction temperature is presented. LM algorithm mini-
mizes the sum of squares of errors with respect to weights where,
of multilayer BPNN having N hidden layer neurons, P input I = Identity matrix; and,
patterns and K outputs as per relation (3–6),

Table 2  Normalized datasets Switching frequency Normalized data for STP 7NK60Z (Sam- Normalized data for STP 7NK60Z
for Implementing BPNN to ple-1) (Sample-2)
estimate ­Rds(on) of MOSFETs
[F]i {F}i [T]i {T}i {Rds(on)}o [T]i {T}i {Rds(on)}o

2 0.02 99.4 0.66 0.71 97.9 0.65 0.70

4 0.04 93.6 0.62 0.68 92.7 0.61 0.67
8 0.08 91.5 0.61 0.67 89.1 0.59 0.66
10 0.10 83.7 0.55 0.63 84.2 0.56 0.64
15 0.15 77.4 0.51 0.60 76.1 0.50 0.60

13
Journal of Electrical Engineering & Technology
µ = Learning parameter that is modified after the iteration
according to the sum of square of errors.
For small value of µ, the LM algorithm becomes
Gauss–Newton method and for large value, it becomes steep
gradient method. Hence, LM based back-propagation algo-
rithm combines the speed of Newton algorithm and stability
of steepest descent algorithm to train small artificial neural
network.
Due to fast convergence capability, the proposed BPNN
model uses few datasets to correctly map arbitrary inputs
to the output. The inputs to the BPNN model for obtaining
failure signature parameter of MOSFETs are the switching
frequency (F)i in kHz and junction temperature (T)i in °C
that are mapped to the output that is on-state drain-source
resistance ­(Rds(on))o. The flowchart for implementation of
proposed BPNN model is shown in Fig. 8. In Sect. 5, the
trained BPNN is implemented in LabVIEW to determine the
on-state drain-source resistance of target MOSFETs.
The data set for off-line training and testing of proposed
back-propagation trained artificial neural network are experi-
mentally obtained using the developed test bed and are
shown in Table 1. The input and output data is normalized
using Linear scaling or Minimum–Maximum (Min–Max)
normalization method. Min–Max method transforms each
input/output data value (D) in the range of [0, 1] as per the
relation (7),
Fig. 10  BPNN model for ­Rds(on) estimation of target MOSFET at α = 0 and η = 0.9
[D]current − [D]minimum
{D}normalized[0,1] = (7)
[D]maximum − [D]minimum
The input and output data set are normalized with
respect to their maximum rated values (switching fre-
quency of 100 kHz; junction temperature of 150 °C and
­Rds(on) of 3.3Ω at 150 °C of ­Tj) given in the datasheet of
target MOSFET (STP 7NK60Z). The normalized input
data matrix for the switching frequency ­[ F] i in (kHz)
is {F}i. Similarly, normalized input data matrix for the
junction temperature [­ T]i in (°C) is {T}i. The normalized
output data matrix for [­ Rds(on)]o in (Ω) is {Rds(on)}o. The
normalized training pairs are shown in Table 2. Normal-
ized switching frequency and normalized junction temper-
ature are inputs and the corresponding normalized value of
­Rds(on) is desired output. Using the normalized input and
output data set, the BPNN is implemented for estimating
the on-state drain-source resistance of target MOSFETs
at test conditions.
The training parameters for BPNN like number of hid-
den layer neurons (H), learning rate (η) and momentum
term (α) are selected in such a manner that the optimum
speed of learning is achieved without causing output
oscillations due to movements of weights changes. It is
reported in [26] that if the number of input nodes is L than,
H should be in a range of L < H < 2L. Therefore, H is taken
13
 Journal of Electrical Engineering & Technology

Fig. 11  BPNN model for ­Rds(on) estimation of target MOSFET at α = 0.1 and η = 0.9

as 3. The architecture for the proposed neural network is

shown in Fig. 9.
The tolerance value of error rate is selected as 0.1%
and optimum value for momentum term and learning rate
is obtained from the training results of BPNN. The simu-
lated BPNN model to estimate the ­Rds(on) of sample-1 of
target MOSFET (STP 7NK60Z) is shown in Fig. 10. Ini-
tially the momentum term, α is taken as 0 and the learning
rate is varied from η = 0.5 to increase the speed of learn-
ing. The number of epochs required for error rate conver-
gence reduces from total 51 epochs at η = 0.5–28 epochs
Fig. 12  BPNN training result for ­Rds(on) estimation of target MOS-
at η = 0.9 without much updates in the weights. Therefore
FET at α = 0 and η = 0.9
η = 0.9 is selected for training the artificial neural network.
After adjusting learning rate, momentum term (α) is
slowly increased in order to adjust the weights for improv-
ing the response of trained network by smoothing the error
surface. At η = 0.9, number of epochs for error rate conver-
gence reduces from 28 epochs to 21 epochs by increasing
(α) from 0 to 0.1 as shown in Fig. 11.
The effect of slowly increasing (α) from 0 to 0.1 on the
slope of error rate and learning speed of BPNN is shown
in Fig. 12 and 13 respectively.
From simulation result, further increase of momen-
tum term causes shifting of updated weights, so value of
α as 0.1 and η = 0.9 is selected that gives the best fit of Fig. 13  BPNN training result for ­Rds(on) estimation of target MOS-
FET at α = 0.1 and η = 0.9

13
Journal of Electrical Engineering & Technology

5 Real‑Time Implementation of ANN

for Prognostics of MOSFET

The proposed scheme for obtaining ANN estimated on-state

Fig. 14  Schematic diagram of Test Circuit
proposed ANN model for estimating the on-state drain-
source resistance of target MOSFET. In similar manner
as above, updated weights (­ Wi, ­V k) of ANN model for
sample-2 of target MOSFET is obtained.
drain-source resistance of target MOSFETs is implemented
in real-time using National Instruments LabVIEW software
[27]. For this purpose a voltage fed half bridge inverter cir-
cuit is designed with overload protection and isolated gate
drive switching circuit. The basic schematic diagram of test
circuit is shown in Fig. 14.
Using the test circuit, the accelerated aging test (ALT) of
upper (M1) and lower (M2) leg target MOSFETs (TO-220
package of STP 7NK60Z) at high power stress condition
is done using variable resistive load. The resistive load is
reduced till both the MOSFETs in the circuit are subjected to
high power stress (at maximum rated current of 5.2 Ampere
and blocking voltage of 600 Volts) at switching frequency
of 85 kHz. A low cost microcontroller is programmed for
acquiring and serially transmitting the real-time operating
data set of in-circuit target MOSFETs to the LabVIEW
software installed at host computer. The case temperatures
for M1 and M2 are continuously acquired from the LM35
sensors glued to flange of MOSFETs and interfaced with
microcontroller board as discussed above. The real-time
input datasets for acquired case temperature and switching

Fig. 15  System Block diagram

Microcontroller
Case Temperature board programmed Test Frequency
Input Data as DAQ card Input Data

Serial Communication

Host Computer
(Internet Connected)

Input data set Normalization and ANN

model Implementation for calculating
Rds(on) of MOSFETs in LabVIEW

Client Computer
Real-time data
Web based Front panel array acquisition
control of Rds(on) in Front
Condition
transfer to panel at Test
monitoring Client Conditions
of MOSFET

13

Fig. 16  Hardware Assembly
frequency are fed to the trained BPNN using microcontroller
based DAQ card and the VISA driver of LabVIEW software.
The block diagram for BPNN based R ­ ds(on) estimation of
target MOSFETs is shown in Fig. 15.
The hardware assembly for implementing the proposed
scheme is shown in Fig. 16.
Block diagram and front panel VI for obtaining ANN
estimated ­Rds(on) of target MOSFETs are shown in Figs. 17
and 18 respectively. The data values are stored on hard disk
of host computer in MS Excel file and control of Front Panel
VI is also transferred to the remote user using web publish-
ing tool of LabVIEW.
Fig. 17  Block Diagram VI
13
Journal of Electrical Engineering & Technology
6 Results and Discussions
Performance of proposed ANN estimated ­Rds(on) is evaluated
by comparing the results with the hardware implementa-
tion of in-circuit operation of target MOSFETs at the test
condition. At the power stress condition of the MOSFETs,
snapshot of current and voltage waveforms for upper (M1)
and lower (M2) leg STP 7NK60Z MOSFET at output sec-
tion of inverter circuit is shown in Fig. 19.
At the above power stressed condition, the case tempera-
ture after half hour of in-circuit operation of MOSFETs M1
and M2 are 129.8 °C and 133.5 °C respectively at 85 kHz
switching frequency. From the relation (2), the ­Rds(on) values
for MOSFETs M1 and M2 are 2.90 Ω and 2.98 Ω respec-
tively. In order to validate the proposed scheme, resulting
ANN estimated ­Rds(on) values for two samples of target
MOSFETs are compared with their in-circuit R ­ ds(on) values
at test conditions. Finally, the Comparative results for the
ANN estimated and in-circuit monitored ­Rds(on) values of
target MOSFETs is shown in Table 3.
From Table 3, the comparative result of ANN estimated
­Rds(on) values for MOSFETs with their practically obtained
in-circuit monitored values shows a low percentage of
relative error which verifies accuracy of proposed method.
Therefore, the proposed ANN based scheme is very useful
Journal of Electrical Engineering & Technology
Fig. 18  Front panel VI
for in-circuit health monitoring of MOSFETs in power elec-
tronics circuits.
7 Conclusions
This paper presents online condition monitoring of power
MOSFETs using ANN approach. Proposed ANN model is
successfully trained off-line with experimental dataset using
LM based back propagation learning algorithm. Further,
the ANN model is implemented using National Instruments
LabVIEW software to determine real-time ­Rds(on) value
of target MOSFETs at the operating conditions. To evalu-
ate the performance of proposed method, ANN estimated
­Rds(on) values of target MOSFETs are compared with their
in-circuit monitored ­Rds(on) at the test conditions. The result
obtained shows a low percentage of relative error which
verifies validity of proposed method. The data values for
ANN estimated ­Rds(on) is also stored on hard disk of host
computer as MS Excel file and the front panel information
is continuously transferred to the remote user as an html file
using web publishing tool of LabVIEW for further analysis.
Therefore, using the proposed method the forecast on aging
condition of in-circuit target MOSFETs can be done in real
time from both onsite and remote location. Proposed ANN
based scheme is useful for in-circuit health monitoring of
MOSFETs in power electronics circuits.
13
 Journal of Electrical Engineering & Technology

Fig. 19  Snapshot of current and voltage waveforms for upper and lower MOSFET

2. Xiong Y et al (2008) Prognostic and warning system for power-

Table 3  Comparative Results of ANN estimated and in-circuit moni-
electronic modules in electric hybrid electric and fuel-cell vehi-
tored ­Rds(on)
cles. IEEE Trans. Ind. Electron. 55(6):2268–2276
Upper MOSFET (M1) Lower MOSFET (M2) 3. Khan S, Khera N, Islam T, Agarwala A (2012) On-line condi-
tion monitoring and maintenance of power electronic converters.
In-circuit moni- ANN estimated In-circuit moni- ANN estimated J Electron Test 30(6):701–709
tored ­Rds(on)(Ω) ­Rds(on)(Ω) tored ­Rds(on)(Ω) ­Rds(on)(Ω) 4. Alghassi A, Perinpanayagam S, Samie M, Sreenuch T (2015)
Computationally-efficient, real-time and embeddable prognostic
2.90 2.83 2.98 2.95 techniques for power electronics. IEEE Trans. Power Electron
30(5):2623–2634
5. Yang S et  al (2011) An industry-based survey of reliabil-
Funding  No funding is received. ity in power electronic converters. IEEE Trans. Ind Appl.
47(3):1441–1451
6. Song Y, Wang B (2013) Survey on reliability of power electronic
Compliance with Ethical Standards  systems. IEEE Trans Power Electron 28(1):591–604
7. Liou J, Ortiz-Conde A, Gracia-Sanchez F (1998) MOSFET phys-
Conflict of interest  The authors have no conflict of interest. ics and modeling. Analysis and design of MOSFETs. Springer,
Boston
Ethical approval  This article does not contain any studies with human 8. Dusmez S, Akin B (2015) Remaining useful lifetime estimation
participants or animals performed by any of the authors. for degraded power MOSFETs under cyclic thermal stress. In:
Proceedings of IEEE conference on energy conversion congress
Informed consent  Informed consent was obtained from all individual and exposition. pp 3846–3851
participants included in the study. 9. Patil N, Das D, Pecht M (2012) A prognostic approach for
non-punch through and field stop IGBTs. Microelectron Reliab
52(3):482–488
10. Celaya J, Saxena A, Saha S, Goebel K (2011) Prognostics of
power MOSFETs under thermal stress accelerated aging using
References data-driven and model-based methodologies. In: Proceedings of
annual conference of the prognostics and health management soci-
ety. pp 1–10
1. Wang H et al (2014) Transitioning to physics-of-failure as a reli-
11. Chen H, Ji B, Pickert V, Cao W (2014) Real-time temperature
ability driver in power electronics. IEEE J Emerg Sel Top Power
estimation for power MOSFETs considering thermal aging effects.
Electron 2(1):97–114

13
Journal of Electrical Engineering & Technology
In: IEEE transactions on device and materials reliability 14(1):
220–228
12. Habchi R, Salame C, Mialhe P, Khoury A (2007) Switching times
variation of power MOSFET devices after electrical stress. Micro-
electron Reliab 47:1296–1299
13. Ye X, Chen C, Wang Y, Zhai G, Vachtsevanos G (2017) Online
condition monitoring of power MOSFET gate oxide degradation
based on miller platform voltage. IEEE Trans Power Electron
32(6):4776–4784
14. Dusmez S, Bhardwaj M, Sun L, Akin B (2016) In situ condition
monitoring of high-voltage discrete power MOSFET in boost con-
verter through software frequency response analysis. IEEE Trans
Ind Electron. 63(12):7693–7702
15. Dusmez S, Duran H, Akin B (2016) Remaining useful lifetime
estimation for thermally stressed power MOSFETs based on on-
state resistance variation. IEEE Trans Ind Appl. 53(3):2554–2563
16. Zhang H, Kang R, Luo M, Pecht M (2009) Precursor parameter
identification for power supply prognostics and health manage-
ment. In: Proceedings of IEEE conference on reliability, main-
tainability and safety. pp 883–887
17. Erturk F, Akin, B (2017) A method for online ageing detection
in SiC MOSFETs. In: Proceedings of applied power electronics
conference and exposition. pp 3576–3581
18. Zhou W, Zhong X, Sheng K (2014) High temperature stability
and the performance degradation of SiC MOSFETs. IEEE Trans
Power Electron 29(5):2329–2337
19. Rashid M (2004) Power electronics circuits, devices, and appli-
cations, 3rd edn. Prentice-Hall, New Delhi
20. Celaya J, Saxena A, Wysocki P, Saha S, and Goebel K (2010)
Towards prognostics of power MOSFETs: accelerated aging and
precursors of failure. In: Proceedings of annual conference of
the prognostics and health management society. pp 1–10
21. Kibushi R, Hatakeyama T, Nakagawa S, Ishizuka M (2013)
Analysis of hot spot temperature in power Si MOSFET with
electro-thermal analysis. In: Proceedings of IEEE conference
on microsystems, packaging, assembly and circuits technology.
pp 211–213
22. Khera N, Tiwari S (2016) Prognostics of power MOSFET due
to unclamped inductive switching. In: Proceedings of IEEE
conference on power electronics, intelligent control and energy
systems. pp 1–4
23. Sattar A (2010) Power MOSFET basics, IXYS Corporation,
IXAN0061. http://www.ixys.com/Docum​ents/AppNo​tes/IXAN0​
061.pdf. Accessed 15 June 2018
24. Graovac D, Pűrschel M, Kiep A (2006) MOSFET power
losses calculation using the data-sheet parameter, Infineon
Technologies, pp 1–22. http://appli ​ c atio ​ n -notes ​ . digch​
ip.com/070/70-41484​.pdf. Accessed 22 July 2018
25. Hagan M, Menhaj M (1994) Training feedforward networks with
the Marquardt algorithm. IEEE Trans Neural Netw 5(6):989–993
26. Huang S, Huang Y (1991) Bounds on the number of hidden
neurons in multilayer perceptrons. IEEE Trans Neural Netw
2(1):47–55
27. Khera N, Khan S (2018) Prognostics of aluminum electrolytic
capacitors using artificial neural network approach. J Microelec-
tron Reliab 81:328–336
Publisher’s Note Springer Nature remains neutral with regard to
jurisdictional claims in published maps and institutional affiliations.
Dr. Neeraj Khera  has received B.Tech. in Electrical Engineering from
Kurukshetra University in 2000 and Masters of Engg. in Electronics
Product Design and Technology from P.E.C Chandigarh in 2005. He
received the Ph.D. degree in Electrical Engineering from the Jamia
Millia Islamia, Delhi, India, in 2015. He is currently Associate Profes-
sor in Department of Electronics & Communication Amity University,
NOIDA. His research and teaching interests include Intelligent Instru-
mentation, Embedded System Design, Fault diagnosis and condition-
based maintenance and Power Electronics.
Dr. Shakeb A. Khan  has received B.Sc. Engg. degree in Electrical
Engineering and M.Sc. Engg. Degree in Instrumentation and Control
from Aligarh Muslim University, Aligarh, India, in 1992 and 1994,
respectively. He received the Ph.D. degree in Instrumentation from
the Indian Institute of Technology, Delhi, India, in 2005. He has been
with Jamia Millia Islamia (A Central University), New Delhi, India,
since 1995, where he is currently Professor in the Department of Elec-
trical Engineering. He has received grants from DST (Department of
Science and Technology), New Delhi, and KACST (King Abdul Aziz
City for Science & Technology), Riyadh, KSA to pursue research on
“Thin Film Sensor & Signal Conditioning”. His research and teaching
interests include Electronics Instrumentation, Thin Film Sensors, ANN
applications, and Sensor Signal Conditioning.
13