From Sand to Silicon “An Eagle view of chip making”

Introduction

The industrial economy may someday run out of one of its essential natural
resources, oil, but at least the chip making technology is safe in its supply of silicon, the
element that is the key ingredient in every computer processor. Its oxide form, known as
silica or quartz, is dirt-common. In fact, it is dirt: Almost all kinds of sand, clay and rock
contain silica in one form or another, and overall more than half the Earth's crust is made
of silica. The first integrated circuits contained only a few transistors. Called "Small-
Scale Integration" (SSI), digital circuits containing transistors numbering in the tens
provided a few logic gates. The next step in the development of integrated circuits, taken
in the late 1960s, introduced devices which contained hundreds of transistors on each
chip, called "Medium-Scale Integration" (MSI). Further development, driven by the same
economic factors, led to "Large-Scale Integration" (LSI) in the mid 1970s, with tens of
thousands of transistors per chip. The final step in the development process, starting in
the 1980s and continuing through the present, was "very large-scale integration" (VLSI).
The development started with hundreds of thousands of transistors in the early 1980s, and
continues beyond several billion transistors as of 2009.

What is VLSI?
VLSI stands for "Very Large Scale Integration". This is the field, which involves
packing more and more logic devices into smaller and smaller areas. Thanks to VLSI,
circuits that would have taken boardfuls of space can now be put into a small space few
millimeters across! This has opened up a big opportunity to do things that were not
possible before. VLSI circuits are everywhere ... your computer, your car, your brand
new state-of-the-art digital camera, the cell-phones, and what have you. All this involves
a lot of expertise on many fronts within the same field, which we will look at in later
sections. VLSI has been around for a long time, there is nothing new about it ... but as a
side effect of advances in the world of computers, there has been a dramatic proliferation
of tools that can be used to design VLSI circuits. Alongside, obeying Moore's law, the
capability of an IC has increased exponentially over the years, in terms of computation
power, utilization of available area, yield. The combined effect of these two advances is
that people can now put diverse functionality into the IC's, opening up new frontiers.
Examples are embedded systems, where intelligent devices are put inside everyday
objects, and ubiquitous computing where small computing devices proliferate to such an
extent that even the shoes you wear may actually do something useful like monitoring
your heartbeats! These two fields are related, and getting into their description can easily
lead to another article.

VLSI DESIGNS ARE CLASSIFIED INTO FOUR CATEGORIES:  

1. Analog: Small transistor count precision circuits such as Amplifiers, Data

converters, filters, Phase Locked Loops, Sensors etc.
2. ASICS or Application Specific Integrated Circuits: Progress in the fabrication of
IC's has enabled us to create fast and powerful circuits in smaller and smaller

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 devices. This also means that we can pack a lot more of functionality into the
same area. The biggest application of this ability is found in the design of ASIC's.
These are IC's that are created for specific purposes - each device is created to do
a particular job, and do it well. The most common application area for this is DSP
- signal filters, image compression, etc. To go to extremes, consider the fact that
the digital wristwatch normally consists of a single IC doing all the time-keeping
jobs as well as extra features like games, calendar, etc.
3. SoC or Systems on a chip: These are highly complex mixed signal circuits (digital
and analog all on the same chip). A network processor chip or a wireless radio
chip is an example of an SoC.
4. FPGA: Field Programmable Gate Arrays (FPGAs) are programmable
semiconductor devices that are based around a matrix of configurable logic blocks
(CLBs) connected via programmable interconnect. As opposed to Application
Specific Integrated Circuits (ASICs) where the device is custom built for the
particular design, FPGAs can be programmed to the desired application or
functionality requirements. Although one-time programmable (OTP) FPGAs are
available, the dominant type are SRAM based which can be reprogrammed as the
design evolves.

Analog IC Design Flow/Conception of the Idea

The objective of analog circuit design is to transform specifications into circuits that
satisfy those specifications. It is a challenging activity because the problem has many
variables and many decisions must be made to achieve a successful design. Depending on
their individual experience and background, different designers may use different
approaches to implement the same set of specifications. Until recently, the really creative
analog circuit designs were relegated to the domain of a few "gifted" designers. However,
as the complexity of analog circuit design has grown, it has become necessary to use the
concepts of regularity, partitioning, and design hierarchy. These concepts, supported by
cleverly designed computer tools, have begun to open the design of analog circuits to a
much wider group.Integrated-circuit design is separated into two major categories: analog
and digital. To characterize these two design methods we must first define analog and
digital signals. A signal will be considered to be any detectable value of voltage, current,
or charge. A signal should convey information about the state or behavior of a physical
system. An analog signal is a signal that is defined over a continuous range of time and a
continuous range of amplitudes. Fig. 1 (a) illustrates an analog signal. A digital signal is a
signal that is defined only at discrete values of time and amplitude. Typically, the digital
signal is a binary weighted sum of signals having only two defined values of amplitude as
illustrated in Fig. 1 (b) and shown in Eq. (1).

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Figure-1 Signals.(a) Analog or continuous time (b) Digital.(c) Analog sampled data or
discrete time.T is the period of the digital or sampled signals.

The individual binary numbers, bi have a value of either zero or one.

Consequently, it is possible to implement digital circuits using circuits with only two
denned states. This leads to a great deal of regularity and to an algebra that can be used to
describe the function of the circuit. As a result, digital circuit designers have been able to
adapt readily to the design of more complex integrated circuits.

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Another type of signal encountered in analog integrated-circuit design is an analog
sampled-data signal. An analog sampled-data signal is a signal that is defined over a
continuous range of amplitudes but only at discrete values of time. Switched-capacitor
techniques result in this type of signal. Often the sampled analog signal is held at the
value of the beginning of the period, resulting in a sampled-and-held signal. Figure 1 (c)
illustrates an analog sampled-data signal and a sampled-and-held analog sampled-data
signal.Circuit design is the creative process of developing a solution to a problem. Design
can be better understood by comparing it to analysis. The analysis of a circuit is the
process by which one starts with the circuit and finds its properties. An important
characteristic of the analysis process is that the solution or properties are unique. On the
other hand, the synthesis or design of a circuit is the process by which one starts with a
desired set of properties and finds a circuit which satisfies them. In a design problem the
solution is not unique. This lets the designer be creative. Consider the design or synthesis
of a 1.5 ohm resistance as a simple example. This resistance could be realized as the
cascade of three 0.5 ohm resistors, the combination of a 1 ohm resistor cascaded with two
1 ohm resistors in parallel, and so on. All would satisfy the requirement of 1.5 ohms
resistance although some might exhibit other properties that would favor their use.

The differences between integrated and discrete analog circuit design are
important. Discrete circuits use active and passive components that are not on the same
substrate, whereas all of the components of an integrated circuit are on the same
substrate. The most obvious difference between the two design methods is that the
geometry of the active devices and passive components in integrated circuit design are
under the control of the designer. This gives the designer an entirely new degree of
freedom in the design process. A second difference is that it is not feasible to breadboard
the integrated-circuit design. Consequently, the designer must turn to simulation methods
to confirm the design's performance. Another difference is that the integrated circuit
designer is restricted to a limited class of components which are compatible with
integrated-circuit technology.

The task of designing an analog integrated circuit includes many steps.. The major
steps in the design process are:

1. Definition
2. Synthesis or implementation
3. Simulation or modeling
4. Geometrical description
5. Simulation including the geometrical parasitics
6. Fabrication
7. Testing and verification

The designer is responsible for all of these steps except fabrication. The first
major task is to define and synthesize the design. This step is crucial since it determines
the performance capability of the design. When this task is completed, the designer must
be able to confirm his (or her) design before it is fabricated. This leads to the second
major task - using' simulation methods to predict the performance of the circuit. At this

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point, the designer may iterate using the simulation results to improve the circuit's
performance. Once satisfied with this performance, the designer can attack the third
major task - a geometrical description (layout) of the circuit. This geometrical description
typically consists of a computer database of variously shaped rectangles or polygons (in
the x-y plane) at different levels (in the z-direction); it is intimately connected with the
electrical performance of the circuit.

Once the layout is finished, it is necessary to include the geometrical effects in a

second simulation. If the results are satisfactory, the circuit is ready for fabrication. Then
the designer is faced with the last major task-determining whether the fabricated circuit
meets the design specifications. If the designer has not carefully considered this step in
the overall design process, it is often impossible to test the circuit and determine whether
or not the specifications have been met.

SOC/ASIC Design flow

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all

components of a computer or other electronic system into a single integrated circuit
(chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions –
all on one chip. A typical application is in the area of embedded systems.

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 Step 1:Prepare an Requirement
Specification
Step 2: Create an Micro-Architecture
Document.
Step 3: RTL Design & Development of
IP's.
Step 4: Functional verification all the
IP's/Check whether the RTL is free from
Linting Errors/Analyze whether the RTL
is Synthesis friendly.
Step 4a: Perform Cycle-based
verification(Functional) to verify the
protocol behaviour of the RTL
Step 4b: Perform Property Checking , to
verify the RTL implementation and the
specification understanding is matching.
Step 5: Prepare the Design Constraints
file (clock
definitions(frequency/uncertainity/jitter),
I/O delay definitions, Output pad load
definition, Design False/Multicycle-
paths) to perform Synthesis, usually
called as an SDC synopsys_constraints,
specific to synopsys synthesis Tool
(design-compiler)
Step 6: To Perform Synthesis for the IP,
the inputs to the tool are (library file(for
which synthesis needs to be targeted for,
which has the functional/timing
information available for the standard-
cell library and the wire-load models for
the wires based on the fanout length of
the connectivity), RTL files and the
Design Constraint files, So that the
Synthesis tool can perform the synthesis
of the RTL files and map and optimize
to meet the design-constraints
requirements. After performing
synthesis, as a part of the synthesis flow,
need to build scan-chain connectivity
based on the DFT(Design for Test)
requirement, the synthesis tool (Test-
compiler), builds the scan-chain.
7: Check whether the Design is meeting
the requirements

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(Functional/Timing/Area/Power/DFT) after synthesis.
Step 7a: Perform the Netlist-level Power Analysis, to know whether the design is meeting
the power targets.
Step 7b: Perform Gate-level Simulation with the Synthesized Netlist to check whether the
design is meeting the functional requirements.
Step 7c: Perform Formal-verification between RTL vs Synthesized Netlist to confirm that
the synthesis Tool has not altered the functionality.
Step 7d: Perform STA(Static Timing Analysis) with the SDF(Standard Delay Format)
file and synthesized netlist file, to check whether the Design is meeting the timing-
requirements.
Step 7e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is built
based on the DFT requirement.
Step 8: Once the synthesis is performed the synthesized netlist file(VHDL/Verilog
format) and the SDC (constraints file) is passed as input files to the Placement and
Routing Tool to perform the back-end Actitivities.
Step 9: The next step is the Floor-planning, which means placing the IP's based on the
connectivity,placing the memories, Create the Pad-ring, placing the
Pads(Signal/power/transfer-cells(to switch voltage domains/Corner pads(proper
accessibility for Package routing), meeting the SSN requirements(Simultaneous
Switching Noise) that when the high-speed bus is switching that it doesn't create any
noise related acitivities, creating an optimised floorplan, where the design meets the
utilization targets of the chip.
Step 9a : Release the floor-planned information to the package team, to perform the
package feasibility analysis for the pad-ring .
Step 9b: To the placement tool, rows are cut, blockages are created where the tool is
prevented from placing the cells, then the physical placement of the cells is performed
based on the timing/area requirements.The power-grid is built to meet the power-target's
of the Chip .
Step 10: The next step is to perform the Routing., at first the Global routing and Detailed
routing, meeting the DRC(Design Rule Check) requirement as per the fabrication
requirement.
Step 11: After performing Routing then the routed Verilog netlist, standard-cells
LEF/DEF file is taken to the Extraction tool (to extract the parasitics(RLC) values of the
chip in the SPEF format(Standard parasitics Exchange Format), and the SPEF file is
generated.
Step 12: Check whether the Design is meeting the requirements
(Functional/Timing/Area/Power/DFT/DRC/LVS/ERC/ESD/SI/IR-Drop) after Placement
and Routing step.
Step 12a: Perform the Routed Netlist-level Power Analysis, to know whether the design
has met the power targets.
Step 12b: Perform Gate-level Simulation with the routed Netlist to check whether the
design is meeting the functional requirement .
Step 12c: Perform Formal-verification between RTL vs routed Netlist to confirm that the
place & route Tool has not altered the functionality.

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Step 12d: Perform STA(Static Timing Analysis) with the SPEF file and routed netlist file,
to check whether the Design is meeting the timing-requirements.
Step 12e: Perform Scan-Tracing , in the DFT tool, to check whether the scan-chain is
built based on the DFT requirement, Peform the Fault-coverage with the DFT tool and
Generate the ATPG test-vectors.
Step 12f: Convert the ATPG test-vector to a tester understandable format(WGL).
Step 12g: Perform DRC(Design Rule Check) verfication called as Physical-verification,
to confirm that the design is meeting the Fabrication requirements.
Step 12h: Perform LVS(layout vs Spice) check, a part of the verification which takes a
routed netlist converts to spice (call it SPICE-R) and convert the Synthesized netlist(call
it SPICE-S) and compare that the two are matching.
Step 12i : Perform the ERC(Electrical Rule Checking) check, to know that the design is
meeting the ERC requirement.
Step 12j: Perform the ESD Check, so that the proper back-to-back diodes are placed and
proper guarding is there in case if we have both analog and digital portions in our Chip.
We have seperate Power and Grounds for both Digital and Analog Portions, to reduce the
Substrate-noise.
Step 12k: Perform seperate STA(Static Timing Analysis) , to verify that the Signal-
integrity of our Chip. To perform this to the STA tool, the routed netlist and SPEF
file(parasitics including coupling capacitances values), are fed to the tool. This check is
important as the signal-integrity effect can cause cross-talk delay and cross-talk noise
effects, and hinder in the functionality/timing aspects of the design.
Step 12l: Perform IR Drop analysis, that the Power-grid is so robust enough to with-stand
the static and dynamic power-drops with in the design and the IR-drop is with-in the
target limits.
Step 13: Once the routed design is verified for the design constraints, then now the next
step is chip-finishing activities (like metal-slotting, placing de-coupling caps).
Step 14: Now the Chip Design is ready to go to the Fabrication unit, release files which
the fab can understand, GDS file.
Step 15: After the GDS file is released , perform the LAPO check so that the database
released to the fab is correct.
Step 16: Perform the Package wire-bonding, which connects the chip to the Package.

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FPGA DESIGN FLOW
A field-programmable gate array is a semiconductor device containing
programmable logic components called "logic blocks", and programmable
interconnects. Logic blocks can be programmed to perform the function of basic
logic gates such as AND, and XOR, or more complex combinational functions such
as decoders or mathematical functions. In FPGAs, the logic blocks also include
memory elements, which may be simple flip-flops or more complete blocks of
memory.

A hierarchy of programmable interconnects allows logic blocks to be

interconnected as needed by the system designer, somewhat like a one-chip
programmable breadboard. Logic blocks and interconnects can be programmed by
the customer or designer, after the FPGA is manufactured, to implement any logical
function—hence the name "field-programmable".

FPGAs are usually slower than their application-specific integrated circuit (ASIC)
counterparts, cannot handle as complex a design, and draw more power (for any
given semiconductor process). But their advantages include a shorter time to
market, ability to re-program in the field to fix bugs, and lower non-recurring
engineering costs. Vendors can sell cheaper, less flexible versions of their FPGAs
which cannot be modified after the design is committed. The designs are developed
on regular FPGAs and then migrated into a fixed version that more resembles an The major
ASIC. steps in this
technology
include film
"Complex Programmable Logic Device" (CPLDs) are an alternative for simpler growth,
designs. They also retain their programming over power downs. doping,
To configure ("program") an FPGA or CPLD you specify how you want the chip to lithography,
work with a logic circuit diagram or a source code using a hardware description etching,
language (HDL). The HDL form might be easier to work with when handling large dicing, and
structures because it's possible to just specify them numerically rather than having packaging
to draw every piece by hand. On the other hand, schematic entry can allow for (see Fig).
easier visualisation of a design. Devices are
Going from schematic/HDL source files to actual configuration: The source files usually
are fed to a software suite from the FPGA/CPLD vendor that through different steps fabricated on
will produce a file. This file is then transferred to the FPGA/CPLD via a serial Si substrates,
interface (JTAG) interface or to external memory device like an EEPROM. which are
grown in
History boules, sliced
into wafers,
The historical roots of FPGAs are in complex programmable logic devices (CPLDs) and polished.
of the early to mid 1980s. A Xilinx co-founder, Ross Freeman, invented the field Thin films are
programmable gate array in 1984. CPLDs and FPGAs include a relatively large grown on
number of programmable logic elements. CPLD logic gate densities range from the these
equivalent of several thousand to tens of thousands of logic gates, while FPGAs substrates and
typically range from tens of thousands to several million. are used to
build active
components,
The primary differences between CPLDs and FPGAs are architectural. A CPLD has passive
a somewhat restrictive structure consisting of one or more programmable sum-of- components,
products logic arrays feeding a relatively small number of clocked registers. The and
result of this is less flexibility, with the advantage of more predictable timing delays
and a higher logic-to-interconnect ratio. The FPGA architectures, on the other hand,
are dominated by interconnect. This makes them far more flexible (in terms of the
range of designs that are practical for implementation within them) but also far
more complex to design for.Another notable difference between CPLDs and FPGAs
interconnections between circuits. These films include: (1) epitaxial Si, (2) SiO2, (3) silicon nitride
(Si3N4), (4) polycrystalline Si (polysilicon), and (5) metal films. To modify electrical or mechanical
properties, films are doped with impurities by thermal diffusion or ion implantation. Lithography is
used to transfer a pattern from a mask to a film via a photosensitive chemical called a photoresist.
The film is then selectively etched away, leaving the desired pattern in the film. This cycle is
repeated until fabrication is complete. The wafers are then probed for yield, diced into chips, and
packaged as final devices.

DEVELOPMENTS IN THE FIELD OF VLSI  

There are a number of directions a person can take in VLSI, and they are all closely related to each
other. Together, these developments are going to make possible the visions of embedded systems
and ubiquitous computing.    

1. Reconfigurable computing: Reconfigurable computing is a very interesting and pretty

recent development in microelectronics. It involves fabricating circuits that can be
reprogrammed on the fly! And no, we are not talking about microcontrollers running with
EEPROM inside. Reconfigurable computing involves specially fabricated devices called
FPGA's, that when programmed act just like normal electronic circuits. They are so
 designed that by changing or "reprogramming" the connections between numerous sub
modules, the FPGA's can be made to behave like any circuit we wish. This fantastic ability
to create modifiable circuits again opens up new possibilities in microelectronics. Consider
for example, microprocessors, which are partly reconfigurable. We know that running
complex programs can benefit greatly if support was built into the hardware itself. We
could have a microprocessor that could optimize itself for every task that it tackled! Or then
consider a system that is too big to implement on hardware that may be limited by cost, or
other constraints. If we use a reconfigurable platform, we could design the system so that
parts of it are mapped onto the same hardware, at different times. One could think of many
such applications, not the least of which is prototyping - using an FPGA to try out a new
design before it is actually fabricated. This can drastically reduce development cycles, and
also save some money that would have been spent in fabricating prototype IC's .

2. Software Engineers taking over hardware design? ASIC's provide the path to creating
miniature devices that can do a lot of diverse functions. But with the impending boom in
this kind of technology, what we need is a large number of people who can design these
IC's. This is where we realize that we cross the threshold between a chip designer and a
systems designer at a higher level. Does a person designing a chip really need to know
every minute detail of the IC manufacturing process? Can there be tools that allow a
designer to simply create design specifications that get translated into hardware
specifications? The solution to this is rather simple - hardware compilers or silicon
compilers as they are called. We know by now, that there exist languages like VHDL which
can be used to specify the design of a chip. What if we had a compiler that converts a high
level language into a VHDL specification? The potential of this technology is tremendous -
in simple manner, we can convert all the software programmers into hardware designers!  

3. The need for hardware compilers: Before we go further let us look at why we need this kind
of technology that can convert high-level languages into hardware definitions. We see a set
of needs, which actually lead from one to the other in a series.

A. Rapid development cycles. The traditional method of designing hardware is a long

and winding process, going through many stages with special effort spent in design
verification at every stage. This means that the time from drawing board to market
is very long. This proves to be rather undesirable in case of large expanding market,
with many competitors trying to grab a share. We need alternatives to cut down on
this time so that new ideas reach the market faster, where the first person to get in
normally gains a large advantage.  

B. Large number of designers. With embedded systems becoming more and more
popular, there is a need for a large number of chip designers, who can churn out
chips designed for specific applications. It's impractical to think of training so many
people in the intricacies of VLSI design.  

C. Specialized training. A person who wishes to design ASIC's will require extensive
training in the field of VLSI design. But we cannot possibly expect to find a large
number of people who would wish to undergo such training. Also, the process of
training these people will itself entail large investments in time and money. This
means there has to be system which can abstract out all the details of VLSI, and
which allows the user to think in simple system-level terms. There are quite a few
tools available for using high-level languages in circuit design. But this area has
 started showing fruits only recently. For example, there is a language called Handel-
C, that looks just like good old C. But it has some special extensions that make it
usable for defining circuits. A program written in Handel-C, can be represented
block-by-block by hardware equivalents. And in doing all this, the compiler takes
care of all low-level issues like clock-frequency, layout, etc. The biggest selling
point is that the user does not really have to learn anything new, except for the few
extensions made to C, so that it may be conveniently used for circuit design.
Another quite different language that is still under development is Lava. This is
based on an esoteric branch of computer science, called "functional programming".
FP itself is pretty old, and is radically different from the normal way we write
programs. This is because it assumes parallel execution as a part of its structure - its
not based on the normal idea of "sequence of instructions". This parallel nature is
something very suitable for hardware since the logic circuits are is inherently
parallel in nature. Preliminary studies have shown that Lava can actually create
better circuits than VHDL itself, since it affords a high-level view of the system,
without losing sight of low-level features.

  

WHAT SORTS OF JOBS DOES AN ELECTRONICS ENGINEER DO?

As mentioned above, the main job functions in this industry are Design, Product, Test,
Applications and Process Engineering. For the sake of clarity, product engineering and test
engineering functions are described separately, but it is most efficient to combine these two
functions into one engineer because of the interdependency and overlap of skills, tasks and job
functions.   

1. Design Engineer: Takes specifications, defines architecture, does circuit design, runs
simulations, supervises layout, tapes out the chip to the foundry, evaluates the prototype
once the chip comes back from the fab.

2. Product Engineer: Gets involved in the project during the design phase, ensures
manufacturability, develops characterization plan, assembly guidelines, develops quality
and reliability plan, evaluates the chip with the design engineer, evaluates the chip through
characterization, reliability qualification and manufacturing yield point of view (statistical
data analysis). He is responsible for production release and is therefore regarded as a team
leader on the project. Post production, he is responsible for customer returns, failure
analysis, and corrective actions including design changes.  

3. Test Engineer: Develops test plan for the chip based on specifications and data sheet,
creates characterization and production program for the bench test or the ATE (Automatic
Test Equipment), designs test board hardware, correlates ATE results with the bench results
to validate silicon to compare with simulation results. He works closely with the product
engineer to ensure smooth release to production and post release support.  

4. Applications Engineer: Defines new products from system point of view at the customer's
end, based on marketing input. His mission is to ensure the chip works in the system
designed or used by the customers, and complies with appropriate standards (such as
Ethernet, SONET, WiFi etc.). He is responsible for all customer technical support,
firmware development, evaluation boards, data sheets and all product documentation such
 as application notes, trade shows, magazine articles, evaluation reports, software drives and
so on.  

5. Process Engineer: This is a highly specialized function which involves new wafer process
development, device modeling, and lots of research and development projects. There are no
quick rewards on this job! If you are R&D oriented, highly trained in semiconductor device
physics area, do not mind wearing bunny suits (the clean room uniforms used in all fabs),
willing to experiment, this job is for you.  

6. Packaging Engineer: This is another highly specialized job function. He develops precision
packaging technology, new package designs for the chips, does the characterization of new
packages, and does electrical modeling of the new designs.  

7. CAD Engineer: This is an engineering function that supports the design engineering
function. He is responsible for acquiring, maintaining or developing all CAD tools used by
a design engineer. Most companies buy commercially available CAD tools for schematic
capture, simulation, synthesis, test vector generation, layout, parametric extraction, power
estimation, and timing closure; but in several cases, these tools need some type of
customization. A CAD engineer needs to be highly skilled in the use of these tools, be able
to write software routines to automate as many functions as possible and have a clear
understanding of the entire design flow.  

FPGA & ASIC Design Advantages

FPGA Design Advantages ASIC Design Advantages
Faster time-to-market - no layout, masks or Full custom capability - for design since device
other manufacturing steps are needed is manufactured to design specs
No upfront NRE (non recurring expenses) -
Lower unit costs - for very high volume designs
costs typically associated with an ASIC design
Simpler design cycle - due to software that
Smaller form factor - since device is
handles much of the routing, placement, and
manufactured to design specs
timing
More predictable project cycle - due to
elimination of potential re-spins, wafer Higher raw internal clock speeds
capacities, etc.
Field reprogramability - a new bitstream can
 
be uploaded remotely

While FPGAs used to be selected for lower speed/complexity/volume designs in the past, today’s
FPGAs easily push the 500 MHz performance barrier. With unprecedented logic density increases
and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed
serial at ever lower price points, FPGAs are a compelling proposition for almost any type of
design.

FPGA vs. ASIC Design Flow Comparison

The FPGA design flow eliminates the complex and time-consuming floorplanning, place and route,
timing analysis, and mask / re-spin stages of the project since the design logic is already
synthesized to be placed onto an already verified, characterized FPGA device.

However, when needed, Xilinx provides the advanced floorplanning, hierarchical design, and
timing tools to allow users to maximize performance for the most demanding designs.

Verilog and Xilinx ISE

5.1 Introduction
The purpose of this experiment is to introduce you to a hardware description language
(HDL) in particular, Verilog. An HDL is a method to describe hardware, by using
software. An HDL representation of any hardware block is a software file, which
adheres to a specific syntactical format. We will also use a tool called Xilinx Integrated
Software Environment (Xilinx ISE) which will help us to convert the code in Verilog to
a fully functional design on the Xilinx series of Field Programmable Gate Arrays
(FPGAs). In this lab, we will design a simple 8-bit ripple carry order using Verilog, on a
Spartan 3E FPGA. We will also use most of the I/Os on the Xilinx Spartan 3E starter
Board (Figure 5.1) to read in our input patterns and display the output of our design.

5.2 Background

5.2.1 Verilog
Verilog is a hardware description language (HDL) used to model digital systems. The
language supports the design, verification, and implementation of digital circuits at various
levels of abstraction. The language differs from a conventional programming language in
that the execution of statements is not strictly sequential. A Verilog design can consist of a
hierarchy of modules. Modules are defined with a set of input, output, and bidirectional
ports. Internally, a module contains a list of wires and registers. Concurrent and
Sequential statements define the behaviour of the module by defining the relationships
between the ports, wires, and registers. Sequential statements are placed inside a begin/end
block and executed in sequential order within the block. But all Concurrent statements and
all begin/end blocks in the design are executed in parallel. This is the key difference
between Verilog and any software programming language. A module can also contain one
or more instances of another module to define hierarchy.
Only a subset of statements in the language is synthesizable. If the modules in a
design contain only synthesizable statements, software like Xilinx ISE can be used to
transform or synthesize the design into a gate level net-list that describes the basic
components and connections to be implemented in hardware. The synthesized net-
list may then be transformed into a bit-stream for any programmable logic devices
like Field Programmable Gate Arrays. Note that this enables a significant
improvement in designer productivity- A designer writes their hardware behaviour
in synthesizable Verilog and the ISE (or similar) tool realizes this hardware on a
hardware platform such as an FPGA. Verilog designs can be written in two forms:
1) Structural Verilog: This is a Verilog coding style in which an exact gate level
net-list is used to describe explicit connections between various components,
which are explicitly declared (instantiated) in the Verilog code.
2) Behavioral Verilog: In this format, Verilog is written to describe the function of the
hardware. The Verilog code in this case describes the behavior of the hardware
 without making explicit references to connections and components. A logic
synthesis tool is required in this case to convert this Verilog code into gate-
level net-lists. Usually, a combined coding style is used where part of the
hardware is described in structural format and part of the hardware is
described in behavioral format according to convenience.

5.2.2 Field Programmable Gate Arrays (FPGA)

A field-programmable gate array is a semiconductor device containing programmable
logic components called "logic blocks", and programmable interconnects. Logic blocks
can be programmed to perform the function of basic logic gates such as AND, and
XOR, or more complex combinational functions such as decoders or mathematical
functions. In most FPGAs, the logic blocks also include memory elements like flip-flops.
A hierarchy of programmable interconnects allows logic blocks to be interconnected
as needed by the system designer, somewhat like a one-chip programmable
breadboard. Logic blocks and interconnects can be programmed in the field by the
customer or designer (after the FPGA is manufactured) to implement any logical
function as and when required hence the name "field-programmable logic arrays".
Realizing a design on an FPGA consists of five steps, which are implemented in a
software tool like the ISE:
1) Synthesis: This is the process of converting a Verilog description into a gate
level net-list.
2) Mapping: This maps the above gate level net-list to the technology specific
components on the FPGA.
3) Placing: This step places the mapped components in a manner that minimizes
wiring, delay etc.
4) Routing: This step configures the programmable interconnects (wires) so as
to wire the components in the design.
5) Programming the FPGA: In this step, the placed and routed design is converted
to a bit-stream using the Xilinx ISE tool. The bit-stream generated by the tool is
loaded (as a .bit file) on to the FPGA. This bit-stream file programs the logic and
interconnects of the FPGA in such a way that the design gets implemented.

5.2.3 Xilinx Spartan 3E starter Board

The Spartan 3E starter board is built around the Xilinx Spartan 3E series of FPGA.
The board has the facility to program the FPGA using a USB connection to your
PC. The board provides programmable interfaces to a global reset, four push
buttons, a rotational knob, four on/off switches, eight LEDs, clock, memories and
the LCD Display, as shown in Figure 5.1.

5.2.4 Xilinx Integrated Software Environment (ISE)

Xilinx Integrated Software Environment is a tool from Xilinx which integrates various
stages of the FPGA design cycle into one software tool. Xilinx ISE provides processes

for logic synthesis, mapping, placing and routing. It also integrates various simulation
tools which are necessary to validate our design at various stages in the design cycle.
 Figure 5.1: Components on Xilinx Spartan 3E starter board

5.3 Pre-Lab

5.3.1 Design 1
In this lab, you will use Verilog to implement an 8 bit adder on the Xilinx Spartan 3E
FPGA. The Verilog used to describe the adder will be in structural format, containing
the exact gate level net-list of the design. Please take a look at the Verilog files provided
to know how to write structural Verilog. For using the I/O’s on the board we need some
other Verilog files which will interface our adder hardware with the I/Os on the board.
The functionality of each Verilog file is described in the section 1.3.2. The complete
block diagram of this design is provided in Figure 5.2 below.
 Figure 5.2: Top Level Block Diagram of Lab 5

In the design above, CLK port is connected to the system clock net. RESET is
connected to one of the push buttons provided on the board. The design provided to
you uses asynchronous reset with the push button to the east of the rotational
switch. ROT_A and ROT_C are two internal switches in the rotational knob. We
will learn more about them in the next lab. ROT_C is port connected to the push-
button of the rotational switch. SF_D [3:0] is the four bit data bus which
communicated with the LCD Display. The other three ports are control ports for the
display. We will learn more about the display in the next lab as well.
In this lab, you will be provided all the Verilog code that interprets the rotational motion of
the rotational knob (via ROT_A and ROT_B), as well as the LCD Display signals.

5.3.2 Using the Integrated Software Environment

The aim of this section is to get you familiar with the FGPA Design Flow using
Xilinx’s Integrated Software Environment (ISE). A complete step by step procedure
to design the simple 8-bit adder is described below:

a) Launch the ISE Project Navigator and create a new design project.
Select Start → Programs → Xilinx ISE Design Suite 10.1
→→ISE→→Project 5avigator.
Alternatively, double click on the ‘Xilinx ISE 10.1’ icon on the
desktop. In the Project Navigator, select File → 5ew Project.
The ‘5ew Project’ Wizard opens as shown in Figure 5.3.
Open a Project Location, say ECE5248Lab in your home directory (H directory).

If there is no folder by that name in the ‘H’ directory, then create a new folder
by that name. All projects done in this lab should be saved to this folder. Don’t
save anything to the default ‘C’ directory because once the machine restarts
 you will lose all your files and won’t be able to use it in the future.

Type a Project Name, say lab5 as shown in Figure 5.3

Chose HDL as the Top-Level Source Type and click 5ext >

Figure 5.3: 5ew Project Wizard

b) The ‘Device and Design Flow’ Dialog appears as shown in Figure

5.4. Select the following options and click 5ext >

Product Category: All

Device Family: Spartan 3E
Device: XC3S500E
Package: FG320
Speed Grade: –5
Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISE Simulator
Preferred Language: Verilog

In this step, we are instructing ISE to implement our design on the FPGA that is
present on our Spartan 3E started board. Please check the device code on the
FPGA for your board and match it to the device name given above. The package

type is also available on the FPGA chip. Check your package type for the
 FPGA on your board.

c) In this lab, you are provided with all the Verilog files that you only required to
use. So, we need not create any new Verilog source files. So, you may skip this
step for this lab. This step (step c) is only necessary in subsequent labs when
you need to type in your own Verilog files to describe your design. Therefore,
when ‘Create 5ew Source’ Dialog appears as shown in Figure 5.5, click on
‘5ext’ to skip this step.
In subsequent labs you may need to perform this step, so when the ‘Create
5ew Source’ Dialog appears as shown in Figure 5.5. Click on ‘5ew Source’ to
add a new source (Verilog) file associated with this project. This will open the
‘5ew Source Wizard – Select Source Type’ window as shown in Figure 5.6.
Now, the ‘5ew Source Wizard – Define Module’ window will open, as shown
in Figure 5.7. This wizard is used to define your I/Os prior to describing your
hardware. You have to specify I/O names, bus widths and the type of bus for
the particular design module. The next window will show a summary of the
design created, click ‘Finish’.
You can add new source files anytime in your design cycle by right clicking
on the project name in the ‘Sources’ tab and by clicking on ‘5ew Source File’.

Figure 5.4: Device Properties

Figure 5.5: Create 5ew Source Wizard
 Figure 5.6: Select Source Type Window

Figure 5.7: Define Module Window

d) This will open ‘5ew Project Wizard – add existing sources’. For this lab, we
need to skip this step too. So, click ‘5ext’ and ‘Finish’.

e) Now you need to add the Verilog files given to you for this lab to the project.
First download the zipped folder for Lab 5 from your lab website. Contact
your TA or your course instructor for the exact URL of your lab. Unzip the
folder on your machine and ‘copy’ (CTRL+C) all files inside it. Now go to
your local ‘ECE5248Lab’ (usually on the H drive of your computer) and find
the folder named ‘lab5’. ‘Paste’ (CTRL+V) all your Verilog files into this
folder. This folder serves as the local folder for current project. It is usually
convenient to place all the Verilog files required in the project in a particular
project-specific folder.

Now you are ready to add the ISE Verilog files to the current project. Go to the
‘Sources’ window to the left, right click on the project name (say lab5) and click
on ‘Add Source’. Press the CTRL key and select the Verilog files that you need
to add to the project and click on ‘Open’. The ‘Adding Files’ pop-up window
appears click on ‘Ok'. These files will now show up on the ‘Sources’ window.

You can add source files at any time in the design cycle by right clicking on
the project name in the ‘Sources’ tab and by clicking on ‘Add Source’.
f) From the Sources window, open any Verilog file by double clicking on it. This will
make the Verilog code appear on the top right hand side of the ISE project
navigator window. If required, you can edit any file after opening it. After
editing, click on File > Save to save all the changes that you made to your design.
In the ‘Sources’ window, all the Verilog files get displayed in hierarchical order.
Here is a brief summary of the functionality of these Verilog files:

1) rot_intfc.v: This module interfaces the rotational switch, reset switch etc
with the adder module.

2) rot_switch1.v: This is the Verilog module which reads in data from the
rotational knob and provides it to the rot_intfc module. You can re-use
this file in later labs for reading in data from the rotational knob.

3) FA.V: This is the structural Verilog net-list of the full adder block which is
going to be used in building the 8-bit ripple carry adder block.

//Verilog Module for Full Adder

`timescale 1ns / 1ps
module FA(C,S,A,B,Cin);
input A,B,Cin;
output C,S;
wire ab,ca,bc;

xor(S,A,B,Cin);
and(ab,A,B);
and(ca,A,Cin);
and(bc,B,Cin);
or(C,ab,ca,bc);

endmodule

4) adder_8bit.v: This is the adder module which takes in two operands as input
from the rot_intfc module, adds them using a ripple carry adder and outputs
the sum of the operands which is provided to the adder_lcd module below.

5) hex_dec.v: This module is used by the adder_lcd module. This module decodes
hexadecimal nibbles to an eight bit output which corresponds to the bit
combination that is required to display that particular digit on the display.
For example if you want to display hexadecimal value ‘A’ on the display
(corresponding to the nibble 1010), the decoded value for the LCD display
is ‘01000001’. This eight bit binary value causes ‘A’ to appear on the LCD
Display. A part of this Verilog code is given below. The bold part of this
code shows how a nibble having hexadecimal value ‘A’ (‘1010’) is decoded
to hexadecimal (‘41’) or binary (‘01000001’).

//Structural Verilog Module

// for 8-bit Ripple Carry Adder Block

`timescale 1ns / 1ps

module adder_8bit(A,B,Sum);
input [7:0] A,B;
output [8:0] Sum;

wire C1,C2,C3,C4,C5,C6,C7;

FA U1 (C1,Sum[0],A[0],B[0],1'b0);
FA U2 (C2,Sum[1],A[1],B[1],C1);
FA U3 (C3,Sum[2],A[2],B[2],C2);
FA U4 (C4,Sum[3],A[3],B[3],C3);
FA U5 (C5,Sum[4],A[4],B[4],C4);
FA U6 (C6,Sum[5],A[5],B[5],C5);
FA U7 (C7,Sum[6],A[6],B[6],C6);
FA U8 (Sum[8],Sum[7],A[7],B[7],C7);
endmodule

always @
(*) begin
case (in)
…
//Decoded value for hexadecimal
‘9’ 4'b1001: out=8'h39;
//Decoded Value for hexadecimal ‘A’
4'b1010: out=8'h41;
…
endcase
end

Parts of the Verilog file: hex_dec.v

6) adder_lcd.v: This module is specific to the adder design of Lab 5. It
outputs the 32 character string to be displayed on the LCD display. For
other labs and designs, you have to write such an interface file which
provides data to the lcd_disp module.

//Module lcd_display is instantiated here

lcd_disp U_lcd_disp ( clk, reset, display, SF_D, LCD_E,
LCD_RS, LCD_RW);

/*All empty spaces on the LCD display not required for our
adder is filled with the code (h’20) which print blank spaces. */
assign temp_line1=96'h202020202020202020202020;
assign temp_line2=104'h20202020202020202020202020;

/*Hexadecimal data is encoded to bits using hex_dec

module which the LCD will understand. */
hex_dec u_hex1 ({3'b000,data[24]},temp1);
…
…
/*Line 1 and Line2 of LCD Display is assigned here with all
the required bits to set the display for our adder. */
assign line1={temp4,temp5,temp_line1,temp6,temp7};
assign line2={temp1,temp2,temp3,temp_line2}; assign
display={line1,line2};
Parts of the Verilog file: adder_lcd.v

7) lcd_disp.v: This is a generic Verilog module which generates the required

timing and control signals to display the 32 characters on the LCD screen.
You may re-use this module along with a design specific interface file (such as
adder_lcd.v above) to configure your LCD for a particular design.

8) counter.v: This module counts up by one on the positive edge of its own
clock input port. It is used by the rotational knob interface to count up
with every turn of the knob.

9) push_butt.v: This module de-bounces the signal from a mechanical switch

to generate a clean pulse which might be used as inputs to some parts of
the design. In this lab, it is used to clean the bounces of the rotational knob
push button, by sampling the output of the mechanical switch.
10)sr.v: This module describes a set-reset flip-flop which is used to
clean up the bounces from ROT_A and ROT_B of the rotational
knob. You will study these techniques in further detail in the next
lab.

11) adder_test.v: This is the test bench file (also called test-fixture file)
for this design. A test bench is a Verilog file which contains input
patterns to test the functionality of the hardware at various stages of
the design cycle. For simulation purposes, this test is generally
performed on the top module in the circuit. Remember the test
bench is not synthesized into any hardware; it is used for simulation
purposes only. This file only shows up on the ‘Sources’ window when
Simulation options are selected as we will see subsequently in this
lab. Parts of the Verilog test bench for the adder is given below
showing the input patterns that are being used to test the adder
design.

i
n
i
t
i
a
l

b
e
g
i
n
// Initialize Inputs
//Begin of Simulation Period
A = 0;B = 0;
// Add Input Patterns here
#2 A=8'h12;B=8'h13;
#2 A=8'h20;B=8'h30;
…
#2 A=8'h11;B=8'h10;
#2 A=8'h08;B=8'h09;
//End of
 Simulation
Period end
Parts of the Verilog test bench file: adder_test.v

g) Now we need instruct the ISE about the top module of our design. The
top-most module in our design is in rot_intfc.v. To do this, go to
sources window and find the file named rot_intfc.v. Now, right click
on this file and click on ‘Set as Top Module’ as shown in Figure 5.8.

h) Now we need to check the syntax of our Verilog files. In the ‘Sources’
window, click on any Verilog file in the design. Now the ‘Process’
window appears showing various operations that need to be performed
to download the design into the Xilinx FPGA. First of all, check the
syntax of your code by clicking on
‘Check Syntax’ under ‘Synthesize’ process. An icon should appear next
to Check Syntax once syntax checking is complete. If you get any
compilation errors,

please correct them before continuing. Check all your Verilog files
for correct syntax before proceeding to the next step.

Figure 5.8: Setting Top Module of the Design

i) The design should be simulated by using the test patterns written in the
test bench to validate the functionality of the Verilog Code. To perform
simulation before synthesis, go to the ‘Source for’ tab on top of the
‘Sources’ window and select ‘Behavioral Simulation’ from the drop-
down menu. You will see the test bench file ‘adder_test.v’ in the
‘Sources’ window. Click on the ‘adder_test.v’ file and go to the
‘Process’ window and click on ‘Xilinx ISE Simulator’ > ‘Simulate
Behavioral Model’ as shown in Figure 5.9. This will launch the
integrated Xilinx ISE Simulator, and show the simulation results in a
black waveform window as shown in Figure 5.10. This window will
show all the tested input patterns and output of our design at various
instances in time. Notice that all signals in the module being tested
shows up in the waveform window. For continuing on Synthesis and
Implementation, go to the ‘Source for’ tab in the Sources window and
select ‘Synthesis and Implementation’ from the drop down menu.

Figure 5.9: Selecting Behavioral Simulation

 Figure 5.10: Waveform window of Xilinx ISE Simulator

j) Now we need to create and add the User Constraints File (.ucf) to the
project. This contains the location of FPGA I/Os on the board. This file will
be used to connect the design I/O signals (ports in the top level Verilog file)
physically to the FPGA I/O pins through which we feed our data from the
Spartan 3E board and display results to the LCD in the Spartan 3E board.
To create a user constraints file, go to ‘User Constraints’ in the ‘Process’
window and click on ‘Edit Constraints (Text)’. Click ‘Yes’ on the pop up
which appears asking for permission to create and add a constraint file
automatically. For this lab, the constraints file necessary (adder.ucf) is
given in the zipped folder along with the Verilog files. You can

copy and paste the content of this constraint file in the blank .ucf
automatically generated in the above step and ‘Save’ it.

Alternately, you can also enter user constraints by using the Xilinx
PACE editor. For designs to be done in other labs, a standard user
constraints file for the Xilinx Spartan 3E starter board is given in
Appendix B. You need to modify the entries in this file depending on
your own requirement of I/O ports in the design.
 Figure 5.11: Choose Configuration Options

k) Now you need to implement the complete design and program the FPGA.
In the Process window, double click on ‘Generate Programming File’.
This will run all the steps necessary to create the bit-stream that can be
downloaded on to the board to program the FPGA. Running these
processes may take several minutes;
progress is indicated by the spinning icon and output to the console.
When a process completes, an icon appears next to the Generate
Programming File text. The steps that are run before the
Programming File is created are: synthesis of the Verilog, mapping of
the result to the FPGA hardware, placement of the mapped
hardware, and routing of the placed hardware and generation of
the .bit bit-stream file required to program the FPGA.

For designs in other labs, you may want to do these steps separately.
All these steps can be done separately one at a time by clicking
individually on the
‘Synthesize’, ‘Map’ and ‘Place and Route’ buttons in the ‘Process’
window. You can also simulate your design after each of these
operations to check the functionality of your design at each step of the
design cycle. Xilinx ISE provides facility for post-synthesis, post-map
and post-place and route simulations. Each of these processes also have
several properties that you can set by right clicking on it and clicking on
‘Properties’. These properties are generally used to optimize the design
 in a specific way i.e. to optimize timing or area or power.

Figure 5.12: Device Programming Properties Window

l) We now need to download the bit-stream to the FPGA on the Spartan 3E

board. Turn on the power to the Spartan 3E starter Board. In Processes
window, under the
‘Configure Target Device’ tab, double click on “Manage Configuration
Project (iMPACT)”. This will open iMPACT (the tool which performs the
bit-stream download to the FPGA, also referred to as device
configuration). The above command will cause a pop-up to appear which
asks you for a method of configuration. Choose ‘Configuration device
using Boundary-Scan (JTAG)’ as shown in Figure 5.11 and click on
‘Finish’. After scanning the board, iMPACT finds three devices. The first,
"XC3s500E", is the FPGA that we need to program.

Double Click on the appropriate bit-stream file (say ‘rot_intfc.bit’ in

our case) with which you need to program the FPGA and click on
‘Bypass’ for the other two devices.
m) Now the “Device Programming Properties” window appears on the
screen. Click on ‘Ok’.

Figure 5.13: Programming the FPGA through Boundary Scan

(JTAG)

n) Select XC3S500E from the device list shown in Figure 5.13. Click on
‘Boundary Scan> ‘H:/ECE5248Lab/lab5/rot_intfc.bit’ (Assuming the .bit
file of your design was named rot_intfc.bit) from the Sources window on
the top left corner of your screen. Then click on ‘Program’ in the
‘Processes’ window to program the FPGA as shown in Figure 5.12. When
the FPGA is programmed successfully, you should see a ‘Program
Succeeded’ sign on the programming window else you will see a ‘Program
Failed’ sign. If you encounter ‘Program Failed’ sign, then check whether
you have done all the steps mentioned in the manual correctly.
If you have successfully programmed your design on to the FPGA, then
you can now test whether the design functions correctly by proceeding on
to the next step.
 o) Use the rotational knob to enter the first operand starting from least
significant nibble (4 bits) to the most significant nibble and press the knob
to freeze the value. As you are entering data, you will see it on the LCD
display. Once the first operand is set, the cursor automatically moves to the
second operand. Now, enter the second operand nibble by nibble. On
entering the last nibble of the second operand, the FPGA based adder adds
the two operands and displays the result on

the second row of the LCD display. All the data displayed on the
LCD is in hexadecimal format. An example, which adds ‘A5’ and ‘E6
’to produce ‘18B’ is shown in Figure 5.13 below.

If you have any more queries regarding the use of ISE, contact your TA. You
should understand all the steps described above in detail. Please ask the TA if
don’t understand any specific terminology or steps. Please clarify all your doubts
before you proceed. Alternatively, you can also use the ‘Help’ option on the Xilinx
ISE Project navigator and click on ‘Tutorials’ for more detailed descriptions of
various options on the Xilinx ISE.

5.3.3 Pre-Lab Deliverables

None

5.4 Lab Procedure

Complete Experiments 1-4 listed below.

5.4.1 Experiment 1
Apart from the test patterns already in the test bench file (adder_test.v), add at
least 5 more patterns to your test bench. Perform behavioral simulations of the
adder block using the test bench provided as described in Section 5.3.2.
Demonstrate the results to your TA.

5.4.2 Experiment 2
Synthesize your Verilog code for the adder using Xilinx ISE and perform post-
synthesis simulation as described in Section 5.3.2 above. To do post-synthesis
simulations, first synthesize your design by setting the adder module
(adder_8bit.v) as your top module as discussed in part ‘g’ of section 5.3.2 of this
manual & running the ‘Synthesize-XST’ process by double-clicking on it. After
synthesis process ends, go to the ‘Sources for’ tab, select ‘Post-Synthesis
Simulation’ from the drop-down menu and double-click on ‘Simulate Post-
Synthesis Model’. Demonstrate the results to your TA.
5.4.3 Experiment 3
Map your synthesized net-list for the adder using Xilinx ISE and perform
post-map simulation as described in Section 5.3.2 above. To do post-map
simulations, first map your synthesized net-list by clicking on ‘Implement
Design’ and double clicking on ‘Map’. After the mapping process ends, go
to the ‘Sources for’ tab, select ‘Post-Map Simulation’ from the drop-down
menu and double-click on ‘Simulate Post-Map Model’. Demonstrate the
results to your TA.

5.4.4 Experiment 4
Place and Route your mapped net-list for the adder using Xilinx ISE and
perform post-place and route simulations as described in Section 5.3.2 above.
To do post-place and route simulations, first place and route your design by
clicking on ‘Implement Design’

and double clicking on ‘Place and Route’. After the place and route process
ends, go to the ‘Sources for’ tab, select ‘Post-Route Simulation’ from the
drop-down menu and double-click on ‘Simulate Post-Place and Route
Model’. Demonstrate the results to your TA.

5.4.5 Experiment 5
Now set rot_intfc.v as the top module of your design and implement the
complete design (synthesize, map and Place & Route). Program the FPGA
using the bit-stream file which is generated in the process. Demonstrate at
least one addition operation to your TA from the patterns you have used in
the test bench. Show that your simulation results above matches the output
on the LCD Display.

5.5 Post-Lab Deliverables

a) Submit the waveforms (similar to Figure 5.10) for the
Experiments 1, 2, 3, and 4. Attach the waveforms (in separate
sheets) in your lab report. What difference do you notice in the
four waveforms and why?
b) Now instead of the structural Verilog net-list provided to you for the
adder. Write a behavioral Verilog module for the 8 bit adder. Do
behavioral simulation to validate the code. Use the test bench
provided to you above for the same. Submit your Verilog file for the
adder in your lab report.
c) Based on the standard .ucf file for the Spartan 3E starter Board
(given in Appendix B), modify the design 1 specific .ucf file
provided to you such that the reset push button is to the ‘West’ of
the rotational knob (instead of the original ‘East’ position).
Provide the modified design specific .ucf file in your lab report.