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Chapter 3: Thyristors
Chapter 3: Thyristors
+
n
19
10
-3
cm
+
n
19
10 cm
-3
10m
J3 - 17 -3
p 10 cm 30-100m
J2
–
n
13
10 -5 x 10
14
cm
-3 50-1000m
J1
p
+
17
10 cm
-3
30-50m
19 -3
p 10 cm
Anode
QUALITATIVE ANALYSIS
When the anode is made positive with respect the
cathode junctions j1 and j3 are forward biased
and junction j2 is reverse biased.
With anode to cathode voltage being small, only
leakage current flows through the device. The
SCR is then said to be in the forward blocking
state.
If VAK is further increased to a large value, the
reverse biased junction will breakdown due to
avalanche effect resulting in a large current
through the device.
The voltage at which this phenomenon occurs is
called the forward breakdown voltage (VBO)
Once the SCR is switched on, the voltage drop
across it is very small, typically 1 to 1.5V.
V-I Characteristics of SCR
Effects on gate current on forward
blocking voltage
LATCHING CURRENT (IL)
After the SCR has switched on, there is a
minimum current required to sustain conduction
even if the gate supply is removed. This current is
called the latching current. associated with turn
on and is usually greater than holding current.
HOLDING CURRENT (IH)
After an SCR has been switched to the on state
a certain minimum value of anode current is
required to maintain the Thyristor in ON state. If
the anode current is reduced below the critical
holding current value, the Thyristor cannot
maintain the current through it and turns OFF.
QUANTITATIVE ANALYSIS
TWO TRANSISTOR MODEL
Derivation for anode current
General transistor equation is
IC= αIE + ICBO
For transistor 1
I C2 I B1
2 I g I CBO1 I CBO 2
IA
1 1 2
THYRISTOR TURN ON
di VS
dt LS
dv/dt protection
The dv/dt across the Thyristor is limited by using
snubber circuit as shown in figure (a) below. If
switch is closed at t=0 , the rate of rise of
voltage across the Thyristor is limited by the
capacitor . When Thyristor is turned on, the
discharge current of the capacitor is limited by the
resistor as shown in figure (b) below.
Fig. (a)
Fig. (b)
The voltage across the Thyristor will rise
exponentially as shown in fig above.
1
VS i t RS i t dt Vc 0 for t 0
C
Assuming Vc(0)=0
Now applying Laplace transform
OR
Where s RS CS
GATE TRIGGERING METHODS
R-triggering.
RC triggering.
UJT triggering.
RESISTANCE TRIGGERING
vO
a b
LOAD
i R1
R2
vS=Vmsint
D VT
R Vg
A simple resistance triggering circuit is as shown.
3 4 3 4 3 4
2 t 2 t 2 t
Vg Vgt Vg Vg Vgp>Vgt
Vgp=Vgt
t 0 t t
270
VT VT VT
3 4
t 2 t t
0 0
0 =90 <90
90
LOAD
+
R
D2 VT
-
vS=Vmsint
D1
VC C
Capacitor ‘C’ in the circuit is connected to shift the
phase of the gate voltage.
Diode D1 is used to prevent negative voltage from
reaching the gate cathode of SCR.
In the negative half cycle, the capacitor charges to
the peak negative voltage of the supply (-Vm)
through the diode D2 .
The capacitor maintains this voltage across it, till
the supply voltage crosses zero. As the supply
becomes positive, the capacitor charges through
resistor ‘R’ from initial voltage of (-Vm) , to a
positive value.
When the capacitor voltage is equal to the gate
trigger voltage of the SCR, the SCR is fired and the
capacitor voltage is clamped to a small positive
Waveform
Vmsint Vmsint
vs vs
V gt Vgt
-/2 0 -/2 0
0 t 0 t
vc vc
vc vc
a a a a
vo vo
Vm Vm
0
t t
vT vT
Vm
0 t
-Vm t
-Vm
(2+)
(a) (b)
Case 1: R Large.
When the resistor ‘R’ is large, the time taken for the
capacitance to charge from (-Vm) to Vgt is large,
resulting in larger firing angle and lower load voltage.
Case 2: R Small
When ‘R’ is set to a smaller value, the capacitor
charges at a faster rate towards Vgt resulting in early
triggering of SCR and hence VL is more.
When the SCR triggers, the voltage drop across it
falls to 1 – 1.5V. This in turn lowers, the voltage
across R & C. Low voltage across the SCR during
conduction period keeps the capacitor discharge
during the positive half cycle.
RC FULL WAVE
vO
LOAD
+
+
D1 D3 R
VT
vd -
C
vS=Vmsint
D4 D2
-
Waveform
vs Vmsint vs Vmsint
t t
vd
vd vd
vc vc vgt vc t vgt t
vo vo
t t
vT vT
t
(a) (b)
UNI-JUNCTION TRANSISTOR (UJT)
B2 B2
Eta-point +
B2
RB2
Eta-point
RB2
p-type
E
E A A VBB
E +
RB1
n-type RB1
Ve Ie VBB
- -
B1 B1 B1
(a) (b) (c)
UJT is an n-type silicon bar in which p-type
emitter is embedded. It has three terminals
base1, base2 and emitter ‘E’.
Between B1 and B2 UJT behaves like ordinary
resistor and the internal resistances are given as
RB1 and RB2 with emitter open RBB=RB1+RB2 .
When VBB is applied across B1 and B2 , we find
that potential at A is
VBB RB1 RB1
VAB1 VBB
RB1 RB 2 RB1 RB2
is intrinsic stand off ratio of UJT and ranges
between 0.51 and 0.82. Resistor RB2 is between 5
Negative Resistance
to 10K. Region
V
Cutoff e Saturation
region region
VBB
R load line
Vp
Peak Point
Valley Point
Vv
0 Ip Iv Ie
UJT RELAXATION OSCILLATOR
T t
C B1
Ve R1 v
o Vo
1
t
(a) (b)
SYNCHRONIZED UJT
OSCILLATOR
R1
+ +
i1 R R2
D1 D3
B2
Pulse Transf
+ E
Vdc Z VZ
B1 G1
C1 To SCR
vc C Gates
G2
D4 D2
C2
- - -
DIGITAL FIRING CIRCUIT
A A
Preset
(’N’ no. of counting bits)
Logic circuit
Clk B +
Fixed frequency max G1
n-bit Flip - Flop Modulator
Oscillator
Counter min S (F / F) B +
(ff) G2
Driver stage
En R
Reset Reset
Load
fC y(’1’ or ‘0’)
Sync Carrier
Signal (~6V) Frequency
ZCD Oscillator
C ( 10KHz)
D.C. 5V
supply
A A