NATIONAL UNIVERSITY OF HO CHI MINH CITY

UNIVERSITY OF INFORMATION TECHNOLOGY

COMPUTER ENGINEERING FACILITIES

FINAL PROJECT
TOPIC: DELAY CIRCUIT 4NS-IRC

INSTRUCTION TEACHER: THẦY NGUYỄN TRẦN SƠN

STUDENT: NGUYỄN VĂN PHƯỚC –18521263
NGUYỄN DUY THỊNH – 18521443

TP. HỒ CHÍ MINH, 5/2021

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 I. INTRODUCTION
- It’s an electronic simulation device for reproduction of a signal with a delay
equal to a predetermined time interval τ. Delay circuits are used in the
simulation of technological processes associated with matter transfer or the
channeling of power, in the approximation of equations describing complex
objects, and as a component of certain automatic control and monitoring
systems. For example, using a delay circuit connected to an electrical network
it is possible to record not only a breakdown of the network but also the
process preceding the occurrence of the breakdown. In actual practice τ can
vary from fractions of a second to dozens of minutes. The operation of a delay
circuit is based on the use of magnetic recording, the capability of electrical
capacitors of retaining a charge, and an approximation of the transfer function
in an ideal delay component.
II. SPECIFICATION
1. Spects:
- Model: 90nm_synopsys.
- VDD: 1.2V.
- Temperater (C degree): -10, 25, 60.
- Library: PDK90reference.
- Tool: Custom Design – Synopsys.
- Current: 1uA.
2. Schematic:
a. Schematic 1 (2 Caps)

Hình 1 Schematic of Delay IRC

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 Specifications Table
DEVICES WIDTH (um) LENGTH (um)
P1 10 5
P2 1.8 0.18
P3 1.8 0.18
P4 1.8 0.18
N1 0.18 0.18
N2* 8 5
N3* 7 4.5
N4 0.18 0.18
*N2, N3 acts as a capacitor to put delay to the circuit.
b. Schematic 2 (1 Cap)

Hình 2 Schematic of Delay IRC

Specifications Table
DEVICES WIDTH (um) LENGTH (um)
P1 10 5
P2 18 1.5
P3 1.8 0.36
P4 1.8 0.36
N1 0.36 0.36
N2* 8.22 8.22
N3 0.36 0.36
* N2 acts as a capacitor to put delay to the circuit.

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III. IMPLEMENTATION AND SIMULATION RESULT
1. Implementation
- We have designed the project with Custom Design so it will have serveral task:
Schematic, Symbol, PreSimulation, Layout, Parameter Extraction, Post Layout
Simulation (for Schematic 1).
a. SCHEMATIC
- The idea is we will take the current bias (I) to control the precision control of
the delay time and create the delay circuit with current bias as input (in
testbench). The delay circuit looks like VRC which have 2 inverter acts as a
buffer but it has a capacitor (NMOS) to increase/decrease delay time.
Schematic 1

Hình 3 Schematic of Delay IRC 4ns - Custom Design

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 Schematic 2

Hình 4 Schematic of Delay IRC 4ns - Custom Design

Hình 5 Symbol of Delay IRC 4ns

b. PreSimulation
- At the first time, our team tried with the current 1uA (at 25 C degree) but the
result wave of output isn’t nice as we expect so we changed the current value
into 0.1nA (at 25 C degree) which has a better result.

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- Despite of 2 testbenches below seem difference but they’re not, they’re the
same function and parameter
Schematic 1

Hình 6 PreSimulation Delay IRC 4ns

Schematic 2

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 Hình 7 PreSimulation Delay IRC 4ns

- We will simulation at 3 temperture: -10, 25, 60 C degree to see the different.

- Vpulse which we take for testbench is 1.2V, Risetime = 0.1ps, Falltime =
0.1ps, Pulse = 14ns, Period = 40ns and currenct bias (I) – IDC = 1uA.
- And I mesure the delay when the voltage = VDD/2 = 0.6V.
Schematic 1

Hình 8 PreSimulation Result (Delay:4ns) at 25 C degree

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 Hình 9 Rise/Fall time Result at 25 C degree

Hình 10 PreSimulation Result IRC Delay at 60C degree

Hình 11 Rise/Fall time PreSimulation at 60 C degree

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 Hình 12 PreSimulation Result Delay time at -10 C degree

Hình 13 Rise/Fall time Simulation at -10 C degree

DELAY DEGREE ( C ) RISE/FALL TIME (ns)

4.03ns 25 1.6/0.924
4.85ns 60 2.35/2.85
3.64ns -10 1.4/0.806
*All the result on the table is the avarage result.
Schematic 2

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Hình 14 PreSimulation Result (Delay:4ns) at 25 C degree

Hình 15 Rise/Fall time Result at 25 C degree

Hình 16 PreSimulation Result IRC Delay at 60C degree

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 Hình 17 Rise/Fall time PreSimulation at 60 C degree

Hình 18 PreSimulation Result Delay time at -10 C degree

Hình 19 Rise/Fall time Simulation at -10 C degree

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 DELAY DEGREE ( C ) RISE/FALL TIME (ns)
4.01ns 25 1.49/1.16
4.66ns 60 1.95/2.35
3.69ns -10 1.25/0.88
*All the result on the table is the avarage result.
c. Layout
Schematic 1

Hình 20 Layout of Delay IDC 4ns

Schematic 2

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 Hình 21 Layout of Delay IDC 4ns

d. Parameter Extration
- With Custom Design, we have 3 steps to comfirm our layout are correct:
• DRC (Design Rules Check): This step uses the DRC function to check
that the design conforms to the design rules are not.
• LVS (Layout Versus Schematic): This step checks if the layout is
properly designed with the design (schematic).
• LPE (Layout Parasitic Extraction): This step estimates and displays
the amounts of parasites on the circuit including capacitors and resistors.
- So Parameter Extraction is LPE step in Custom Design.

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Schematic 1

Hình 22 Parameter Extraction (1)

Schematic 2

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 Hình 23 Parameter Extraction (1)

- It looks like layout but look closely we will see the circuit including capacitors
and resistors.

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 Hình 24 Parameter Extraction (2)

e. Post Layout Simulation

- Post layout use the same testbench like PreSimulation. The difference here is
when we click at Symbol in PreSimulation it will show us the schematic, but
when we click at Symbol in Post Layout Simulation it will show us the
Parameter Extraction.

Hình 25 Post Layout Simulation Testbench

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- Same with the PreSimution, we will simulation the post layout with 3
temperatures: -10, 25, 60 C degree.
Schematic 1

Hình 26 Post Layout Simulation Delay time at 25 C degree

Hình 27 Rise/Fall time Post Layout Simulation at 25 C degree

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Hình 28 Post Layout Simulation Delay Result at 60 C degree

Hình 29 Rise/Fall time Post Layout at 60 C degree

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 Hình 30 Post Layout Simulation Delay time at -10 C degree

Hình 31 Rise/Fall time Post Layout at - 10 C degree

DELAY DEGREE ( C ) RISE/FALL TIME (ns)

3.84ns 25 1.76/1.1
4.71ns 60 2.7/3.15
3.52ns -10 1.48/0.887
*All the result on the table is the avarage result.
Schematic 2

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 Hình 32 Post Layout Simulation Delay time at 25 C degree

Hình 33 Rise/Fall time Post Layout Simulation at 25 C degree

Hình 34 Post Layout Simulation Delay Result at 60 C degree

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 Hình 35 Rise/Fall time Post Layout at 60 C degree

Hình 36 Post Layout Simulation Delay time at -10 C degree

Hình 37 Rise/Fall time Post Layout at - 10 C degree

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 DELAY DEGREE ( C ) RISE/FALL TIME (ns)
3.6ns 25 1.23/1.28
4.54ns 60 1.96/2.63
3.4ns -10 1.23/0.93
*All the result on the table is the avarage result.
COMPARE BETWEEN PRESIMULATION AND POST LAYOUT SIMULATION
a. Schematic 1:
PreSimulation
DELAY DEGREE ( C ) RISE/FALL TIME (ns)
4.03ns 25 1.6/0.924
4.85ns 60 2.35/2.85
3.64ns -10 1.4/0.806
Post layout simulation
DELAY DEGREE ( C ) RISE/FALL TIME (ns)
3.84ns 25 1.76/1.1
4.71ns 60 2.7/3.15
3.52ns -10 1.48/0.887
b. Schematic 2:
PreSimulation
DELAY DEGREE ( C ) RISE/FALL TIME (ns)
4.01ns 25 1.49/1.16
4.66ns 60 1.95/2.35
3.69ns -10 1.25/0.88
Post layout simulation
DELAY DEGREE ( C ) RISE/FALL TIME (ns)
3.6ns 25 1.23/1.28
4.54ns 60 1.96/2.63
3.4ns -10 1.23/0.93
c. Comment:
- In Schematic 2, Rise/Fall Time are quite stability in PreSimulation and in
PostLayout Simulation and the current bias wave is clearly than Schematic 1.
But Delay time in PostLayout not as expected, it just has 3.6ns/4ns (in
Schematic 1 is 3.84ns/4ns).
- Despite of 2 testbenches above seem difference but they’re not, they’re the
same function and parameter so it takes 2 results with 2 Schematic.
- In my conclusion, Schematic 2 is the best case for 4ns because it delays time
in PostLayout is acceptable with 3.84ns/4ns and the difference of Rise/Fall
time between two Schematic are not large.

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IV. SUMMARY AND FUTURE RESEARCH/CONCLUSION
- After doing this project, I have gained the following experience:
• W/L of PMOS, NMOS make an important contribution in creating
delay timing in this circuit also the current bias (I) too.
• At previous project, we have done the VRC dealy circuit so this IRC
delayc circuit help us know more about delay circuit in general.
- We hope to have access to more designs to learn more.
-------------------------------------------The end----------------------------------------

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