International Journal of Pure and Applied Mathematics

Volume 118 No. 14 2018, 261-266

ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version)
url: http://www.ijpam.eu
Special Issue
ijpam.eu

65 YEARS JOURNEY OF LOGARITHM MULTIPLIER

Durgesh Nandan1, Jitendra Kanungo2, Anurag Mahajan3

1,2
Department of Electronics and Communication Engineering, J.U.E.T, Guna, India
3
Department of Electronics and Telecommunication Engineering, S.I.T, Pune, India
prof.durgeshnandan@gmail.com1, jitendra.kanungo@juet.ac.in2, anurag.mahajan@sitpune.edu.in3

Abstract: Real time computing with low power is the of multiplication based on logarithm involves three
basic need for various application areas like Digital steps: (1) logarithmic conversion of binary numbers for
Signal Processing, image processing, internet of things logarithmic representations, (2) then, arithmetic
and neural networks. 86 % of the data processing time in operations are performed in the logarithmic domain, and
a real-time three-dimensional graphics system is due to (3) then, antilogarithmic conversion [5]. Block diagram
multiplication and division operations only. Logarithm for a computation of LNS based multiplication is shown
multiplier is the possible solution for hardware efficient in Figure 1.
and fast multiplication operation. In the last 65 years, the
logarithm multiplier becomes an important arithmetic Input X Input Y
component for various applications. But, there is absence
of systematic literature on complete development history
Logarithmic Logarithmic
and proc-corns of logarithm multiplier at one place. Converter Converter
Hence, this paper outlines the evolution and
developments of the logarithm multiplier architecture
design and highlights the potential research areas for Arithmetic Circuit
further improvements. This comprehensive study
includes the techniques used by researchers to improve Antilogarithmic
Converter
the design of logarithm multiplier and given advantage
over other reported multiplier that is also highlighted.
Z

Keywords: Arithmetic circuits, Antilogarithm

conversion, DSP, Improved operand decomposition
logarithm conversion, Logarithmic multiplication,
Mitchell method, Operand decomposition.
I. INTRODUCTION
The rapid growth of integrated circuit technology has
become the key motivation for real time signal
processing to be performed in digital domain. As, it
known that Digital Signal Processing (DSP) has lot of
arithmetic operations (such as multiplication, division,
addition, subtraction, square root and power) used. 86 %
of the data processing time in a three-dimensional
graphics system is due to multiplication and division
operations only [1]. Multiplication is broadly used
arithmetic operation in the field of DSP and image
processing [2]. It is known that multiplier is thirsty
resource and its speed has always been a limiting factor.
Logarithmic number systems (LNS) based multipliers
provide major advantages over fixed point (FXP)
number system and floating point (FLP) number system
multipliers [3]. Logarithmic multiplier converts
multiplication and division operation into addition and
subtraction operation respectively [4]. The computation
Figure 1: Block diagram of computation of arithmetic
based on LNS
In this paper an investigation of LNS multiplication is
carried out. The brief overview of LNS is described in
Section 2. Reported literature has been explored further
in Section 3. Section 4 explores the comparison of
results. Section 5 explores the logarithm multiplier
design application in real life scenario. Finally, the
finding of the logarithm multiplier design is concluded
in Section 6.
II. LOGARITHIM NUMBER SYSTEM
Binary number system has given issues of large area,
delay and large power consumption in an operation of
multiplication, division, root and power performed in a
DSP application. But, DSP applications have a primary
goal to process an operation fast with efficient hardware
which may not be full-filled due to the above mentioned
issues of binary number system. The LNS addresses to
these issues and overcomes the technical gaps. LNS
provide a new approach to speed up the multiplication
and division with conventional weighted numbers.

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International Journal of Pure and Applied Mathematics
Mathematicians have used logarithms to simplify
mathematical operations like multiplication, division etc.
because these operations can be performed by using
addition and subtraction. LNS multipliers are
advantageous in terms of speed and accuracy over the
Fixed Point (FXP) multipliers and Floating Point (FLP)
multipliers [5-6]. LNS multiplier supports the two
families of native data-types: integer or fixed-point data
and floating-point data. Fixed point multiplication is
frequently used in general purpose digital processing
applications due to the reasons of an easier algorithm,
faster implementation, and a clear understanding. But,
the floating point representation is a suitable choice at
the place where decimal notations have essential criteria
to represent the non-integer number. In 1985, floating-
point was standardized by “IEEE 754 standard” with two
sizes, 32 bits and 64 bits. IEEE 754 standard sets two
formats for LNS: single and double precision [7].
The primary LNS arithmetic operations of two binary
numbers A and B are shown in Table 1. Variable Log Z,
Log A and Log B represent the logarithm values of Z, A,
and B, respectively [7-8].
Table 1: Logarithmic arithmetic operations
Binary Logarithmic operation
operation
Z=A×B Log Z= Log A + Log B
Z=A÷B Log Z= Log A - Log B
Z=A+B Log Z= Log A +
Log2(1+2(Log B- Log A))
Z=A-B Log Z= Log A +Log2(1-2(
Log B- Log A)
) Logarithmic multiplication
III. LITERATURE REVIEW ON LOGARITHM
MULTIPLICATION
General classification of Logarithmic Multiplication is
shown in Figure 2. LNS multipliers can be divided into
two categories, (1) lookup tables and interpolations
based [9-10] and (2) Mitchell’s algorithm based [4].
Early LNS based works [5-6] [11-19] were on
interpolation schemes. Interpolation schemes based LNS
multipliers require Read Only Memory (ROM) to store
the necessary coefficients. Research work has applied to
digit-recurrence methods to perform the conversion
which save hardware costs but at cost of speed [5] [7]
[20]. However, ‘shift-and-add’ based schemes have been
used to have suitable design tradeoffs among of delay,
area and accuracy [4, 21]. Mitchell’s algorithm based
logarithm multiplication was divided into four sub-
categories. As (1) Divided Approximation (2) Correction
term based (3) Operand decomposition and (4) MA-
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Special Issue
based iterative algorithm. In 1962, Mitchell reported an
algorithm that was based on simple add and shift
operation of computer multiplication and division [4]. In
Mitchell's method, the Average Percentage Error (APE)
was 3.85%, and the error percentage was in between 0%
to 11.11%. Hall's algorithm has been implemented but
the drawback was the accuracy at the cost of speed,
power consumption and hardware complexity [22]. In
1975, Swartzlander et al. have suggested [23] the sign
logarithm number system and fast algorithms for basic
arithmetic operations. In 1988, Taylor et al. have
reported [12] an architecture design of the 20-bit
logarithmic arithmetic processor. In 1991, Yu and Lewis
have reported [24] an architecture design of the 30-bit
logarithmic arithmetic processor. In 1999, SanGregory's
correcting algorithm was implemented that was simple
and fast in operation [21]. In 2003, Abed and Siferd have
developed the correction algorithm that suggests the
trade-off among the accuracy, speed and complexity
[25]. In 2006, V. Mahalingam et.al has given the
Operand Decomposition (OD) as an independent
approach to minimize the error [26]. In 2008, Johansson
et al. [7] have reported the approximation method. In
2010, Fu reported et al. [17] have reported the
polynomial approximation approach. During 2010 to
2013, the iterative logarithmic approximation was
introduced which was based on the correction terms with
the high-level of parallelism [27-29]. In 2017, Durgesh
Nandan et.al has given the Improved Operand
Decomposition (IOD) as an approach to minimize the
error and has applied to previous logarithmic
multiplication approaches [30].
Look up Table based
Mitchell’s
Algorithm(MA) based
Improving MA Accuracy
Divided Approximation
MA based Iterative
Algorithm
Correction Term based Operand Decomposition
Figure 2: General classification of the Logarithmic
Multiplication operation.
IV. RESULTS AND DISCUSSION
For proper understanding of systematic design trend and
accuracy improvement, we study five latest designs
which are proposed by V. Mahalingam et al. in 2006,
Bulic et al. in 2010, R. Agrawal et al. in 2013 and
International Journal of Pure and Applied Mathematics Special Issue

Durgesh Nandan et al. in 2017. Analysis has been done technique to carry-out the research areas like image
in terms of accuracy as well as hardware complexity. processing, video-signal processing and transmission
The error analysis can be performed with the equal [26]. LNS are broadly applicable in video compression,
interval input vectors for Mitchell’s algorithm, OD- especially in motion vector [33]. Multiplication circuits
Mitchell’s, iterative algorithm and IOD-Mitchell’s consume a lot of areas, time and power. To overcome
multiplication. Results are implemented and applied with these issues various LNS techniques are may be used.
the same input patterns for fair error analysis, which is Various research fields like astronomy, geography,
shown in Table 2. medicine etc. have frequently applied the concepts of
digital image processing [34]. Due to numerous
Table 2: Comparison for Average Error Percentage and applications of logarithm multiplier, it motivates
Maximum Possible Error researchers to come forefront to study the existing work
and to contribute research efforts.
METHOD AEP (%) MPE
4-bit 8-bit 16-bit (%) VI. CONCLUSION
MA4 --- 3.77 3.83 ~12
OD-MA26 1.441 1.449 2.170 11.11 In 2016, Akhter et al. have tried to conclude all
Iterative27,28,29 8.913 9.412 25 logarithm multiplier literature in one place but they were
(ECCs =0) ---
Iterative27,28,29 --- --- 6.25 partial concluded [35]. In this paper we discuss about the
(ECCs =1) --- LNS, how LNS represent, systematic development in
Iterative27,28,29 --- --- 1.56 field of logarithmic multiplier and its applications. This
(ECCs =1) --- comprehensive study includes the techniques used by
IOD-MA30 1.6279 1.678 2.064 11.11 researchers to improve the design of logarithm
multiplication. Based on this analysis conclude that the
The table shows the AEP for 4-bit, 8-bit, and 16-bit iterative logarithmic multiplier is the best choice for
multiplicand widths and MPE for Mitchell’s algorithm, designers if accuracy is the main concern. But, the IOD
OD-Mitchell’s, Iterative and IOD-Mitchell’s based logarithm multiplication is the most efficient
multiplication. IOD-Mitchell’s multiplication gives design in terms of area, speed, latency, accuracy.
1.627% APE for 4-bit, 1.678 % for 8-bit, and 2.064 % However, if logarithm multiplier is implement by
for 16-bit, whereas OD- Mitchell’s multiplication gives logarithm converter and antilogarithm converter with
1.441% APE for 4-bit, 1.449 % for 8-bit, and 2.170 % advanced correction circuit which was suggested in
for 16-bit. In logarithmic multiplier with iterative literature, it must become the most efficient design with
pipelined architecture gives 8.913 % for 8-bits and best performance [36-37]. This enhancement is hoped to
9.41% for 16 bits. MPE is same of 11.11% for OD-MA contribute significant improvements in digital signal
and IOD-MA, ~12 % for Mitchell’s algorithm and 25% processing systems and image processing area.
for logarithmic multiplier with the iterative pipelined
architecture for zero error correction circuit.
Table 3: Synthesis results for the proposed IOD based
We have synthesized all three design logarithmic logarithmic multiplication architecture and reported
multiplier architecture for 8, 16, and 32 bits by using at structures [26-30].
90 nm CMOS technology node. The area, power, Area-
Delay Product (ADP), timing constraints and energy are
compared for all structures [26], [27], [28], [29] and [30]
are as listed in Tables 3. The IOD based logarithmic
multiplier with pipelining gives 20.17%, 20.69% and
21.72% less ADP, 42.47%, 39.91% and 13.74% less
Energy for 8-bits, 16-bits, and 32-bits architecture
respectively than of iterative pipeline based logarithmic
multiplier [27-28].
V. APPLICATIONS

The real world is full of applications of logarithm References

multiplier few of these applications are briefly discussed
[1] K. Yoshida, T. Sakamoto, and T. Hase, “A 3D
here. The approximate computing has been an applicable
graphics library for 32-bit microprocessors for

263
International Journal of Pure and Applied Mathematics
embedded systems,” IEEE Trans. Consum.
Electron, vol. 44, no. 3, pp. 1107–1114, Aug.
1998.
[2] Klinefelter, J. Ryan, J.Tschanz and B.H.
Calhoun, “Error-Energy Analysis of Hardware
Logarithmic Approximation Methods for Low
Power Applications” IEEE International
Symposium on Circuits and Systems (ISCAS),
pp.2361-2364, 24-27 May 2015.
[3] T. Stouraitis and V. Paliouras, “Considering the
alternatives in low power design,” IEEE Circuits
Dev. Mag., Vol. 17, No. 4, pp. 22–29, Jul. 2001.
[4] J.N. Mitchell, "Computer Multiplication and
Division using Binary Logarithms," IRE Trans.
Electronic Computers, Vol. 11, No. 6, pp. 512-
517, Aug. 1962.
[5] Paul, S., N. Jayakumar, and S. P. Khatri, “A Fast
Hardware Approach for Approximate, Efficient
Logarithm and Antilogarithm Computations.”
IEEE Transactions on Very Large Scale
Integration Systems, Vol. 17, No.2, pp. 269–277,
Feb. 2009.
[6] D. K. Kostopoulos, “An Algorithm for the
Computation of Binary Logarithms.” IEEE
Transaction on Computers, Vol. 40, No.11, pp.
1267–1270, Nov. 1991.
[7] K. Johansson, O. Gustafsson and L. Wanhammar,
“Implementation of Elementary Functions for
Logarithmic Number Systems,” IET Computer &
Digital Techniques, Vol. 2, No. 4, pp. 295–304,
April 2008.
[8] D. Das Sarma and D. Matula, “Faithful bipartite
ROM reciprocal tables,” Comput. Arith., pp.17–
28, 1995.
[9] T.A. Brubaker and J.C. Becker, "Multiplication
Using Logarithms Implemented with Read-Only-
Memory," IEEE Trans. Computers, pp. 761-766,
1975.
[10] M. Arnold, T. Bailey and J. Cowles, "Error
Analysis of the Kmetz / Maenner Algorithm," J.
VLSI Signal Processing, pp. 37-53, 2003.
I. Kouretas, C. Basetas, and V. Paliouras., “Low-
power Logarithmic Number System
Addition/Subtraction and their Impact on Digital
Filters,” IEEE Transactions on Computers, Vol.
62, No. 11, pp. 2196–2209, Nov. 2013.
[11] F.J. Taylor, R. Gill and J. Joseph, "A 20 Bit
Logarithmic Number System Processor," IEEE
264
Special Issue
Trans. Computers, Vol. 37, No. 2, pp. 190-200,
Feb. 1988.
[12] P. T. P. Tang, “Table-Lookup Algorithms for
Elementary Functions and Their Error Analysis.”
IEEE 10th Symposium on Computer Arithmetic,
Grenoble, New York, pp. 232–236, 26–28 June
1991.
[13] M. J. Schulte, and E. E. Swartzlander, “Hardware
Designs for Exactly Rounded Elementary
Functions.” IEEE Transactions on Computers,
Vol. 43, No. 8, pp. 964–973, Aug. 1994.
[14] J. E. Stine, and M. J. Schulte, “The Symmetric
Table Addition Method for Accurate Function
Approximation,” Journal of VLSI Signal
Processing Systems, Vol. 21, No. 2, pp. 167–177,
Feb.1999.
[15] J. A. Pineiro, M. D. Ercegovac, and J. D.
Bruguera, “Algorithm and Architecture for
Logarithm, Exponential, and Powering
Computation.” IEEE Transaction on Computers,
Vol. 53, No. 9, pp. 1085–1096, Sep. 2004.
[16] H. Fu, O. Mencer, and W. Luk, “FPGA Designs
with Optimized Logarithmic Arithmetic.” IEEE
Transactions on Computers, Vol. 59, No. 7, pp.
1000–1006, July 2010.
[17] R. C. Ismail, and J. N. Coleman. 2011. “ROM-
Less LNS.” In Proceedings of IEEE Symposium
on Computer Arithmetic,Tubingen, New York,
pp. 43–51, 25–27 July 2011.
[18] M. G. Arnold, and S. Collange, “A Real/Complex
Logarithmic Number System ALU,” IEEE
Transactions on Computers, Vol. 60, No.2, pp.
202–213, Feb. 2011.
[19] M. J. Schulte, and J. E. Stine, “Approximating
Elementary Functions with Symmetric Bipartite
Tables,” IEEE Transactions on Computers, Vol.
48, No. 8, pp. 842–847, Aug. 1991.
[20] S.L. San Gregory, R.E. Siferd, C. Brother and D.
Gallagher, "Low-Power Logarithm
Approximation with CMOS VLSI
Implementation," Proc. IEEE Midwest Symp.
Circuits and Systems, Aug. 1999.
[21] E.L. Hall, D.D. Lynch, and S.J. Dwyer III,
“Generation of Products and Quotients Using
Approximate Binary Logarithms for Digital
Filtering Applications,” IEEE Trans. Computers,
vol. 19, no. 2, pp. 97-105, 1970.
International Journal of Pure and Applied Mathematics Special Issue

[22] E. Swartzlander and A. Alexopoulos, “The [33] F. Cabello, J. Leon, Y. Lana, and R. Arthur,
sign/logarithm number system,” IEEE Trans. “Implementation of a Fixed-Point 2D Gaussian
Comput., vol. C, pp. 1238–1242, 1975. Filter for Image Processing based on FPGA,”
IEEE Signal Processing: Algorithms,
[23] L. K. Yu, and D. M. Lewis., “A 30-b Integrated
Architectures, Arrangements, and Applications,
Logarithmic Number System Processor.” IEEE
pp. 28-33, 2015.
Journal of Solid State Circuits, Vol. 26, No. 10,
pp. 1433–1440,Oct. 1991. [34] P. Akhter, S. Bandewar, Durgesh Nandan,
“Logarithmic Multiplier: An Analytical Review”
[24] K.H. Abed, R.E. Sifred, “CMOS VLSI
International Journal of Engineering Research,
Implementation of a Low- Power Logarithmic
Volume No.5, Issue No.8, pp: 721-723, 2016.
Converter,” IEEE Transactions on Computers,
Vol. 52, No. 11, pp. 1421-1433, November 2003. [35] Durgesh Nandan, J. Kanungo and A. Mahajan,
“An Efficient VLSI architecture design for
[25] V. Mahalingam and N. Rangantathan, Improving
antilogarithmic converter by using the error
Accuracy in Mitchell's Logarithmic Multiplication
correction scheme,” IETE International
Using Operand Decomposition, IEEE
conference on signal processing (ICSP), SATI,
Transactions on Computers, Vol. 55, No. 2, pp.
India, 11-13 Nov. 2016.
1523-1535, December 2006.
[36] Durgesh Nandan, Anurag Mahajan and Jitendra
[26] P. Bulic, Z. Babic and A. Avramovic, “A simple
Kanungo, “An Efficient antilogarithmic converter
pipelined logarithmic multiplier”, IEEE
by using 11-regions error correction scheme,”
International Conference on Computer Design
IEEE 4th International Conference on Signal
(ICCD), pp.235-240 (2010).
Processing, Computing and Control (ISPCC
[27] R. K Agrawal and H. M. Kittur, “ASIC based 2017), JUIT, Waknaghat, 21-23 Sep.2017.
logarithmic multiplier using iterative pipelined
architecture,” IEEE Conference on Information &
Communication Technologies (ICT), pp.362-366,
2013.
[28] Durgesh Nandan, J. Kanungo and A. Mahajan,
“An efficient VLSI architecture for Iterative
Logarithmic Multiplier,” IEEE 4th International
conference on signal processing and integrated
networks (SPIN), pp.419-423, Amity University,
India, 2017.
[29] Durgesh Nandan, J.Kanungo and A. Mahajan,
“An efficient VLSI architecture design for
logarithmic multiplication by using the improved
operand decomposition,” Integration, the VLSI
Journal, vol. 58, pp. 134–141, 2017.
[30] M.J. Duncan, “Improved Mitchell Based
Logarithmic Multiplier for Low Power DSP
Applications,” IEEE Int’l System on a Chip Conf.
(SOCC), pp. 17-20, 2003.
[31] Y. Sun, and M.S. Kim, “A High-Performance 8-
Tap FIR Filter Using Logarithmic Number
System, IEEE ICC, 2011.
[32] Z. Babic, A. Avramovic, and P. Bulic, “An
iterative logarithmic multiplier, Microprocessors
and Microsystems,” vol. 35, no. 1, pp. 23-33,
2011.

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