Second Year – 2nd Semester Digital Systems Design Lab. Assist. Lect.

Eman Karim

Experiment 1 - Introduction to Quartus Prime Lite

Objective:

To get familiar with Quartus Prime Lite.

Procedure:

1. Install Quartus Prime Lite 17.1 Edition.

2. Create a new project by following these steps:
Open Quartus Prime Lite File New Project Wizard Next
Directory, Name Next Empty project Next Next
Device (family: Cyclone V), Board (DE1-SoC Board) Next EDA tools
(Simulation: ModelSim-Altera , VHDL) Next Finish
3. Create a new file by following these steps:
File New VHDL File OK
4. Write VHDL code.

Lab1a: Create (Lab1a) project to run the VHDL file of AND circuit (F=AB)
using Quartus Prime Lite.

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Second Year – 2nd Semester Digital Systems Design Lab. Assist. Lect. Eman Karim

Run the Compile Design then go to:

1. Analysis & Synthesis Netlist Viewers RTL Viewer

2. Tools Options EDA Tool Options ModelSim-Altera :

(C:\intelFPGA_lite\17.1\modelsim_ase\win32aloem)
3. Tools Run Simulation Tools RTL Simulation
4. Layout Reset
5. rtl_work lab1a
6. Select all objects (A, B and F) and from right click choose Add Wave
7. Modify the clock of (A) by right click to be (100) and First Edge (Falling)
8. Modify the clock of (B) by right click to be (50) and First Edge (Falling)
9. Write run in the Transcript
10. Select both A and B then choose Combine Signals (Name: Inputs)

The run of this project is: