Embedded Systems Lab

(17CS. 6th Semester)

Lab – 11 Section 1

Lab Experiment No. 11

Name: Roll No:

Score: Signature: Date: _

To Designing of basic Sequential logic circuits (Flip-Flops)

PERFORMANCE OBJECTIVE:
After the successful completion of this lab, students will be able to:
 Design & Synthesize of basic D flip flop and JK flip flop using Xilinx ISE Software.
 Simulation of Flip Flops using ISIM Simulator.
 Implementation of Counter with NEXYS2 Spartan 3E Kit using Xilinx ISE &
Adept Software.
LAB REQUIREMENTS:
 PC with Windows XP/2007 Operating System.
 Xilinx ISE Design Suite 12.3 Software installed.
 Digilent Adept Software.
 NEXYS2 Spartan 3E Kit.

DISCUSSION:
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state
information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals
applied to one or more control inputs and will have one or two outputs. It is the basic storage element
in sequential logic. Flip-flops and latches are fundamental building blocks of digital
electronics systems used in computers, communications, and many other types of systems.

JK FLIP-FLOP: For purpose of counting, the JK flip-flop is the ideal element to use. The variable
J and K are called control I/Ps because they determine what the flip- flop does when a positive edge
arrives. When J and K are both 0s, both AND gates are disabled and Q retains its last value.

Figure 12.1 JK flip flop

D FLIP –FLOP: This kind of flip flop prevents the value of D from reaching the Q output until
clock pulses occur. When the clock is low, both AND gates are disabled D can change value without
affecting the value of Q. On the other hand, when the clock is high, both AND gates are enabled. In
this case, Q is forced to equal the value of D. When the clock again goes low, Q retains or stores the
last value of D. a D flip flop is a biostable circuit whose D input is transferred to the output after a
clock pulse is received.

Figure 12.1 D-flip flop

DESIGNING PROCEDURE:

DESIGN ENTRY

1. Invoke Xilinx ISE Design Suite 12.3 Software.

“Select File > New Project”

2. Enter the Project name DFF in the Name field. Verify that HDL is selected as the Top-Level
Source Type, and click on NEXT again click on NEXT and Click on Finish.

3. Now Create a New Source file; Go to Project > New Source.

 Select VHDL Module and Enter the source file name DFF.
 Click on Next. Enter the Input and output Ports name and click NEXT and click
Finish.

VHDL Code for the DFF is

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff IS
PORT (d, clk, rst: IN STD_LOGIC;
Q, Qinv: OUT STD_LOGIC);
END dff;
ARCHITECTURE behavior OF dff IS
signal slow_clk : std_logic;
signal clk_divider : std_logic_vector(25 downto 0);
BEGIN
frequency_divider : process (clk,
clk_divider) begin
if (clk'event and clk=„1‟) then
clk_divider <= clk_divider + 1;
end if;
slow_clk <= clk_divider(25);
end process;
PROCESS (clk, rst)
BEGIN
 IF (rst='1') THEN
Q <= '0'; Qinv <= „1‟;
ELSIF (slow_clk'EVENT AND clk='1') THEN
Q <= d; Qinv <= not d;
END IF;
END PROCESS;
END behavior;

SIMULATION:
After Creating project and new Source File now it is ready to simulate the Design. To
simulate the counter follow the following steps.

1. In the Design Panel, select the Simulation radio button.

2. Select counter Behavioral file and double click on Simulator Behavioral Model in the
Process window.

3. Select the Simulation from the menu bar and click on Restart.

4. force the input signal (clk, reset, d).

5. Select the Simulation from the menu bar and click on Run. Verify the Simulation result.

SYNTHESIS:
1. To synthesize the design, double click on the Synthesize Design option in the Processes
window.

2. Now you can view the schematic diagram of the DFF can be viewed by double clicking View
RTL Schematic under Synthesize-XST menu in the Process Window.

3. Similarly you can view the Technology Schematic Symbol by double clicking View
Technology Schematic under Synthesize-XST menu in the Process Window.

Implementation:
1. Before implement the design you must create the User Constraint File UCF.

2. After creating the UCF file Single Click on counter.ucf file from within Project Navigator,
and then Select “Edit Constraints (Text)” from the Process window.

3. Assigning the pins to inputs and outputs of counter as following and save Ucf file.
 UCF file for DFF is

NET "clk" LOC = "B8" ;

NET "Q" LOC = "J14" ;
NET "Qinv" LOC = "J15" ;
NET "reset" LOC = "H13";

4. After assigning the Pins double click on “Implement Design” option in the Processes
window. It will go through steps like Translate, Map and Place & Route.

5. Now create a programming file (bit stream file) of the design. This is done by clicking once
on your top-level design in the Sources Pane, followed by a double click on “Generate
Programming File” in the process window.

6. Once the programming file (bit stream file) is generated, the file has to be downloaded to the
NEXYS2 Spartan3E device, using Digilent Adept Software.

Once the programming file (bit stream file) is generated, the file has to be downloaded to the
NEXYS2 Spartan3E device. This is done by using another application Adept Software
provided by Digilent.

Final Assignment:

1. Design the VHDL code for JK flip flop and attach the simulation results.

VHDL code:

OUTPUT: