UNIVERSITY OF ENGINEERING AND

TECHNOLOGY, TAXILA

Lab Report 14
Digital Logic Design Lab
Name: Alina Gulzar

Reg No.: 21-CP-06

Section: Omega

Department: Computer Engineering

Due Date: 14th August 2022

EXPERIMENT #14
BEHAVIORAL MODELING
Objective:
To understand and write Verilog code for small modules using Behavioral Modeling.
Apparatus List:

• Icarus Verilog installed on PC

LAB Tasks:
1. Write Verilog Code for D and T Flip Flop using behavioral modeling along with Test Bench
and simulate it on Icarus Verilog
2. Write Verilog Code for Counter using behavioral modeling along with Test Bench and
simulate it on Icarus Verilog

Design Methodology:
• First of all, we have to create a folder so that all the related files are in the same folder.
• Open Notepad, and write the Verilog code, save that notepad file in [module_name.v]
extension. The name of file and name of module must be same. As Verilog HDL is the case
sensitive Language so, a smallest mistake will cause an error.
• Again open notepad and write a test bench for the code file and save this file as syntax:
[module_nametb.v].
• Now, copy both files and open Local Disk: C → iverilog → bin → Paste the files.
• Click on the address bar.

• Write cmd in the bar and press enter key.

• A new interphase is opened…

• Now we have to write the commands, write → iverilog → -o → design name → test
bench file name (tb.v) → verilog code file name (.v) → Press Enter key.
• If there is no error present in the file, then write → vvp → design name → Press enter key.
• Now the vcd file is ready for the output.
• Copy the vcd file, and open Local Disk: C → iverilog → gtkwave → Paste the files.
• Click on the address bar.

• Write cmd in the address bar.

• Write → gtkwave → design name → Press Enter.

• The see the output on the gtkwave analyser.

Truth Table, assumptions, conventions, definitions, Karnaugh Map(s), algebraic simplification

steps, etc.
• D - Flipflop
Verilog Code:
module DFF1( Q, Qbar, D, Clk, Reset);

output reg Q;
output Qbar;
input D, Clk, Reset;
assign Qbar = ~Q;

always @(posedge Clk)

begin
if (Reset == 1'b1) //If not at reset
Q = 1'b0;
else
Q = D;
end
endmodule

Test Bench:
`timescale 1ns / 1ps
module DFF1tb;
reg D, Clk, Reset;
wire Q, Qbar;

DFF1 DUT ( .Q(Q), .Qbar(Qbar), .D(D), .Clk(Clk), .Reset(Reset));

initial begin

D = 1'b0;
Clk = 1'b0;
Reset = 1'b1;
#100;
Reset = 1'b0;
#20;
forever #40 D = ~ D;
end
always #10 Clk = ~Clk;

initial
begin
$dumpfile ("DFF1tb.vcd");
$dumpvars (0, DFF1tb);
end
endmodule
Simulation:
 • T - Flipflop
Verilog Code:
module TFF( Q, Qbar, T, Clk, Reset);

output reg Q;
output Qbar;
input T, Clk, Reset;

always @(posedge Clk)

begin
if (!Reset )
Q <=0;
else
if (T)
Q <= ~Q;
else
Q <= Q;
end
endmodule
Test Bench:
`timescale 1ns / 1ps

module TFFtb;

reg T, Clk, Reset;

wire Q;

TFF DUT ( .Q(Q), .T(T), .Clk(Clk), .Reset(Reset));

initial begin

T = 1'b0;
Clk = 1'b0;
Reset = 1'b1;
#100;
Reset = 1'b0;
#20;

forever #40 T = ~ T;
end

always #10 Clk = ~Clk;

initial
begin
$dumpfile ("TFFtb.vcd");
$dumpvars (0, TFFtb);
end
endmodule
Simulation:
• Counter
Verilog Code:
module udcounter(input clk, reset,up_down, output[3:0] counter );
reg [3:0] counter_up_down;
always @(posedge clk or posedge reset)
begin
if(reset)
counter_up_down <= 4'h0;
else if(~up_down)
counter_up_down <= counter_up_down + 4'd1;
else
counter_up_down <= counter_up_down - 4'd1;
end
assign counter = counter_up_down;
endmodule
Test Bench:
module udcountertb();
reg clk, reset,up_down;
wire [3:0] counter;

udcounter DUT(clk, reset,up_down, counter);

initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
up_down=0;
#20;
reset=0;
#200;
up_down=1;
end

initial
begin
$dumpfile ("udcountertb.vcd");
$dumpvars (0, udcountertb);
end
endmodule
Simulation:
Results:
We have verified the truth table of D and T Flipflop and Counter. Their outputs are correct.

Conclusion:
The behavioral modeling describes how the circuit should behave. Due to these factors,
structural or data-flow models are regarded as having a lower abstraction level than behavioural
models. The actual implementation of the circuit is determined by the VHDL synthesiser tool.
Results are more accurate by using behavioral modeling. Instead of theories, it concentrates on
how a system behaves.