What is “datapath”?

Memory
Processor

Instructions Datapath
(Machine Code)

Datapath: The way instructions are being

executed inside a processor
Six different datapath architectures

(1) General-Purpose CISC/special-purpose RISC Processors:

 Scalar Processors (i8086)
 Pipeline Processors (i80486)
 Super-Scalar Processors
 Super-Pipeline Processors (i80586 – P54)
(2) Super Computers/Mainframes:
 Vector Processors
 VLIW Processors
1. Scalar Datapath Processors

• The datapath includes the five circuit units

• All five units are implemented as single monolithic unit
• When an instruction is being executed, no other instruction can
enter the datapath
Processor

IF ID EX ME WB
Datapath

IF: Instruction Fetch ID: Instruction Decode EX: Execution

ME: Memory access WB: Write Back to registers
1. Scalar Datapath Processors (continued)

Representative processors in this generation

i4004, i8080, i8086, i80816, Z80, MC68000

IF ID EX ME WB CPI = 5.0
IF ID EX ME WB
IF ID EX ME WB

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Clock Cycles
2. Pipeline Datapath Processors

• All five units are implemented as independent units

• When an instruction is completed in a unit, the instruction can be
forwarded to the next unit
• All five units can be occupied by different instructions

Processor

IF ID EX ME WB

Datapath
2. Pipeline Datapath Processors (continued)

Representative processors in this generation

CPI for these only for
i80386, i40846, MC68040, ….
these four instructions

8 cycles / 4 instructions
IF ID EX ME WB
IF ID EX ME WB
CPI =2.0
IF ID EX ME WB
IF ID EX ME WB

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Clock Cycles
3. Super-Scalar Datapath Processors

• Multiple Scalar Datapath

Processor

IF ID EX ME WB
Datapath #1

IF ID EX ME WB
Datapath #2
3. Super-Scalar Datapath Processors (continued)

15 cycles / 6 instructions
IF ID EX ME WB
IF ID EX ME WB
CPI =2.5
IF ID EX ME WB
IF ID EX ME WB
IF ID EX ME WB
IF ID EX ME WB

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Clock Cycles
4. Super-Pipeline Datapath Processors

• A combination of super-scalar and pipeline

Processor

IF ID EX ME WB

Datapath #1

IF ID EX ME WB

Datapath #2
4. Super-Pipeline Datapath Processors (continued)

Representative processors in this generation

Pentiums (54, P55C), MIPS CPI

R10000, …. only for
for these
these six instructions
IF ID EX ME WB
7 cycles / 6 instructions
IF ID EX ME WB
IF ID EX ME WB
IF ID EX ME WB CPI =1.16
IF ID EX ME WB
IF ID EX ME WB

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Clock Cycles
5. Vector Datapath Processors (continued)

Representative processors in this generation

C-90 and Y-MP (Cray), VAX 9000 (Digital), …

IF ID EX1 ME WB
EX2 IF ID EX1 ME WB
EX3 EX2 IF ID EX1 ME WB
EX4 EX3 EX2
EX5 EX4 EX3
EX6 EX5 EX4

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Clock Cycles
6. VLIW Datapath Processors (continued)

• An extension of scalar datapath architecture

• Multiple execution units
Processor

EX1

EX2

IF ID EX3 ME WB

EX4 Datapath

EX5
6. VLIW Datapath Processors (continued)

• Each instruction has to have multiple operations in it

256 bits in Transmeta Crusoe TM8000

OP OP OP
EX1
P11 P12
EX2
P21 P22  P51 P52
EX5

Operator 1 Operator 2 Operator 5

• Each operator corresponds to an instruction in scalar machine

6. VLIW Datapath Processors (continued)

Representative processors in this generation

TI TMS320C6200, Philips TM1000, Transmeta Crusoe, …

IF ID EX1 ME WB
EX2 IF ID EX1 ME WB
EX3 EX2 IF ID EX1 ME WB
EX4 EX3 EX2
EX5 EX4 EX3
EX6 EX5 EX4

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6. VLIW Datapath Processors (continued)

VLIW can be pipelined ….

IF ID EX1 ME WB Very low CPI (< 1.0) possible

IF EX
ID2 EX1 ME WB
EX
IF3 EX
ID2 EX1 ME WB
EX4 EX3 EX2
EX5 EX4 EX3 • Processor resources are very efficiently used
EX6 EX5 EX4 • Only if most of the execution units are used

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Who should make sure this?