A B C D E

1 1

Compal Confidential
Schematics Document
2 2

NIWE1
Arrandale
3 with Intel IBEX PEAK-M core logic 3

REV:0.3

4 4

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 1 of 51
A B C D E
 A B C D E

Compal confidential POWER BD: CAP SENSOR BD: CARD READER BD:
File Name : POWER BTN VOLUME UP ENE UB6250/52
ZZZ1 NOVO BTN VOLUME DOWN HP JACK
POWER MANAGE BTN MUTE MIC JACK
14W_PCB_LA5751P VRAM 64*16 Intel AUDIO ENHANCE
DDR3*4 Arrandale BUTTON & LED
1 ZZZ page23 Clock Generator 1

HYN@ PCI-E X16 (UMA/DIS) RTM890N

page12
X76_H512
NVidia N11M-GE1 Socket-rPGA989
page19~23
37.5mm*37.5mm DDR3-SO-DIMM X2
level shift IC BANK 0, 1, 2, 3 page 10,11
page5~9
HDMI Dual Channel
CONN ASM1442 100MHz DDR3-800(1.5V) UP TO 8G
page25
2.7GT/s FDI *8 DMI *4 DDR3-1066(1.5V)
page24

CRT Connector 2Channel Speaker

page33
page26
2

LVDS Intel Ibex Peak M AZALIA Audio Codec Analog MIC_Int

2

page33
Connector page27 CONEXTAN
FCBGA 951 CX20671 page33
PCI Express
6*PCI-E BUS 25mm*25mm
Mini card Slot 1 14*USB2.0 CMOS Camera
page28
page27

PCI Express 6*SATA serial BlueTooth CONN

Mini card Slot 2 page 13~18 page37
page28

SPI ROM USB CONN X1(Right)

page37
BIOS page13 LPC BUS

3
SIM Card USB PORT X1(Left) 3
page37
page28 USB(WWAN)
RTL8103EL/8111DL
EC New Card X1
ENE KB926D Card Reader/Audio Jack SB
page28
10/100/1G LAN page34
page29 CONN
WWAN ENE UB6250/52 HP X 1+
page28 MS/MS MIC_Ext X1
pro/SD/SD
RJ45 CONN Int.KBD pro/mmc/XD
page30 page35 page38

EMC1403 SPI ROM ESATA HDD AND USB CONN

Thermal Sensor EC page36
SATA HDD CONN page37
page31
page32

4 Touch Pad SATA ODD CONN 4

page32
page35

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/03/24 Deciphered Date 2008/04/ Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 2 of 51
A B C D E
 A B C D E

DDR3 Voltage Rails

SMBUS Control Table
N10x NEW
WLAN Thermal Cap sensor CARD PCH
SOURCE RAM M2 BATT KE926 SODIMM CLK CHIP WWAN N10x board
+5VS Sensor
+3VS SMB_EC_CK1
power
+1.5VS SMB_EC_DA1
KB926 X V
+3VALW
X X X X X X X X X
plane +3VALW
+VCCP SMB_EC_CK2
1
+5VALW +1.5V +CPU_CORE SMB_EC_DA2
KB926 X X X X X X X X X X V 1
+3VALW +3VALW
+B +VGA_CORE SMBCLK
+3VALW +1.8VS SMBDATA
PCH V X X V V X X X X V X
+3VALW +3VALW +3VS +3VS +3VS
+0.75VS SML0CLK
State +1.05VS SML0DATA
PCH
+3VALW
X X X X X X X X X X X
SML1CLK
SML1DATA
PCH
+3VALW
X X V X X X +3VS
V X V
+3VS
X X
+3VALW

S0
O O O O

I2C / SMBUS ADDRESSING

S3
O O O X
2
S5 S4/AC DEVICE HEX ADDRESS 2
O O X X
DDR SO-DIMM 0 A0 10100000
S5 S4/ Battery only
O X X X DDR SO-DIMM 1 A4 10100100
CLOCK GENERATOR (EXT.) D2 11010010
S5 S4/AC & Battery
don't exist X X X X

@ FUNCTION
Structure Description NON-USE
45@ 45 BOM
BT@ Blue Tooth function
3G@ 3G function (WWAN)
CAP@ CAP Sensor function
CMOS@ CMOS CAMERA function PCIE PORT LIST USB PORT LIST
3
ESATA@ E-SATA function PORT DEVICE PORT DEVICE 3
HDMI@ HDMI function (UMA or DIS)
UMA_HDMI@ HDMI function (UMA only) 1 0 RIGHT SIDE
X76@ X76 BOM 2 WLAN 1 LEFT SIDE
100@ 10/100 LAN function 3 LAN 2 CMOS
GIGA@ GIGA LAN function 4 3G 3 LEFT SIDE
UMA@ UMA only (Arrandale) 5 NEW CARD 4 RIGHT SIDE
DIS@ DIS only (Arrandale) 6 5 CARD READER
7 6
8 7
8 WIRELESS
9
10 NEW CARD
11 BT
SKU 12
13 3G
Arrandale(dGPU) DIS@
4 4
DIS only
Arrandale(iGPU) UMA@
UMA only
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/03/24 Deciphered Date 2008/04/ Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 3 of 51
A B C D E
 A B C D E

VGA and DDR3 Voltage Rails (N11x GPIO) Performance Mode P0 TDP at Tj = 102 C* (DDR3)
FBVDDQ PCI Express I/O and I/O and Other
GPIO I/O ACTIVE Function Description GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.5V) (1.5V) (6) (1.8V) (1.05V) (3.3V)
GPIO0 N/A N/A Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)

GPIO1 IN - Hot plug detect for IFP link C N11M-GE1

64bit 14.02 2.16 TBD TBD 12.9 12.26 0.66 0.99 1.3 1.95 530 0.56 84 0.15 140 0.15 38 0.13
512MB
GPIO2 OUT H Panel Back-Light brightness(PWM capable) DDR3
1 1

GPIO3 OUT H Panel Power Enable

GPIO5 GPIO6
GPIO4 OUT H Panel Back-Light On/Off (PWM)
GPU_VID0 GPU_VID1 VGA_CORE P-State
Device ID
GPIO5 OUT - GPU VID0 0 0 0.8V Deep P12
N11M-GE1/LP1 0 1 0.85V P8
GPIO6 OUT - GPU VID1 (40nm) 0x0A7D
1 1 1.03V P0
GPIO7 OUT N/A

GPIO8 I/O N/A

GPIO9 OUT N/A

GPIO10 OUT N/A

GPIO11 I/O - Reserve 10K pull low.

GPIO12 IN N/A

2
GPIO13 OUT N/A 2

GPIO14 OUT - Reserve 10K pull low.

GPIO15 IN N/A

GPIO16 OUT N/A

GPIO17 IN - PAD The ramp time for any rail must be more than 40us
Power Sequence
GPIO18 IN N/A

GPIO19 IN N/A

(+3VS) VDD33

PEX_VDD can ramp up any time

(1.05VS)PEX_VDD
tNVVDD
3 3

(+VGA_CORE) NVVDD
tNV-IFPAB_IOVDD

(1.8VS)IFPAB_IOVDD
tNV-FBVDDQ

(1.5VS) FBVDDQ

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/03/16 Deciphered Date 2010/03/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 4 of 51
A B C D E
 5 4 3 2 1

DDR3 Compensation Signals

SM_RCOMP0 1 2
R567 100_0402_1%
SM_RCOMP1 1 2
R566 24.9_0402_1%
SM_RCOMP2 1 2
R565 130_0402_1%

Layout Note:Please these

D
Layout rule：10mil width trace resistors near Processor D

length < 0.5", spacing 20mil

JCPU1B
20_0402_1% 1 R560 2COMP3 AT23 COMP3 CLK_CPU_BCLK
BCLK A16 CLK_CPU_BCLK <16> +VCCP

MISC
20_0402_1% 1 R558 2COMP2 AT24 COMP2 BCLK# B16 CLK_CPU_BCLK#
CLK_CPU_BCLK# <16>
49.9_0402_1% 1 R548 2COMP1 CLK_CPU_ITP PM_EXTTS#0

CLOCKS
G16 COMP1 BCLK_ITP AR30 T17 PAD 1 2
AT30 CLK_CPU_ITP# T18 PAD R561 10K_0402_5%
49.9_0402_1% BCLK_ITP#
1 R557 2COMP0 AT26 COMP0
PM_EXTTS#1 1 2
E16 CLK_EXP R562 10K_0402_5%
PEG_CLK CLK_EXP <14>
D16 CLK_EXP#
PEG_CLK# CLK_EXP# <14>
TP_SKTOCC# AH24 SKTOCC#
DPLL_REF_SSCLK A18 pins unused by
A17
+VCCP 2 1 H_CATERR# AK14
DPLL_REF_SSCLK# Clarksfield on the XDP_PREQ# R136 1 @ 2 51_0402_1%
CATERR#

THERMAL
49.9_0402_1% R163 rPGA989 Package
XDP_TMS R138 1 @ 2 51_0402_1%

<16> H_PECI
R564
1
0_0402_5%
2 H_PECI_ISO AT15 PECI
SM_DRAMRST# F6 SM_DRAMRST# 3 XDP_TDI R556 1 @ 2 51_0402_1%
AL1 SM_RCOMP0
SM_RCOMP[0]
+VCCP 2 R569 1 68_0402_5% SM_RCOMP[1] AM1 SM_RCOMP1 XDP_TDO R134 1 2 51_0402_5%
AN1 SM_RCOMP2
H_PROCHOT# SM_RCOMP[2]
<34,48> H_PROCHOT# AN26 PROCHOT#
AN15 PM_EXTTS#0 XDP_TCK R57 1 @ 2 51_0402_1%
PM_EXT_TS#[0]

DDR3
MISC
AP15 PM_EXTTS#1 1 2
PM_EXT_TS#[1] PM_EXTTS#1_R <10,11>
R563 0_0402_5% XDP_TRST# R133 1 2 51_0402_5%
H_THERMTRIP# AK15
<16> H_THERMTRIP# THERMTRIP#

AT28 XDP_PRDY# T19 PAD R137

C PRDY# XDP_PREQ# XDP_DBRESET# @ C
PREQ# AP27 1 2 1K_0402_5% +3VS

AN28 XDP_TCK
TCK
1 H_CPURST#_R XDP_TMS
+VCCP 2 AP26 RESET_OBS# TMS AP28
CHECK INTEL DOCUMENT #385422

PWR MANAGEMENT
68_0402_5% R135 AT27 XDP_TRST#
TRST#
Debug Port Design Guide Rev1.3

JTAG & BPM

<15> H_PM_SYNC 1 R187 2 H_PM_SYNC_R AL15 PM_SYNC TDI AT29 XDP_TDI
0_0402_5% AR27 XDP_TDO
TDO
TDI_M AR29
1 R190 2 VCCPWRGOOD_1 AN14 VCCPWRGOOD_1 TDO_M AP29 R555 2 1 0_0402_5%
0_0402_5%
AN25 XDP_DBRESET#
DBR#
<16> H_CPUPWRGD 1 R139 2 VCCPWRGOOD_0 AN27 VCCPWRGOOD_0
0_0402_5%
AJ22 XDP_BPM#0
BPM#[0]
<15> PM_DRAM_PWRGD 1 R191 2 VDDPWRGOOD_R AK13 SM_DRAMPWROK BPM#[1] AK22 XDP_BPM#1
0_0402_5% AK24 XDP_BPM#2
BPM#[2] XDP_BPM#3
BPM#[3] AJ24
<46> VCCP_POK 2 1 VTT_POK AM15 AJ25 XDP_BPM#4
R184 VTTPWRGOOD BPM#[4] XDP_BPM#5
BPM#[5] AH22
FROM POWER VTT 1K_0402_1% AK23 XDP_BPM#6
BPM#[6]
2

AM26 AH23 XDP_BPM#7

POWER GOOD SIGNAL R183 TAPPWRGOOD BPM#[7]
R185
560_0402_5%
<16,19,28,29> BUF_PLT_RST# 1 2 PLT_RST#_R AL14 RSTIN#
1

1.5K_0402_5%
1

R186 IC,AUB_CFD_rPGA,R1P0
750_0402_1% ME@
2

B B

+1.5V
For Intel S3 Power Reduction. For Intel S3 Power Reduction.
5 +1.5V 3

2
1

+3VALW @ R301
R193 1K_0402_1%
1.1K_0402_1% @
1 2

1
5

U8 0_0402_5% R300
2

2 R195
P

B DRAM_PWRGD VDDPWRGOOD_R
<46> VCCP_POK Y 4 1 2 DDR3 CONNECTER DRAMRST# SM_DRAMRST#

S
1 A <10,11> DRAMRST# 1 3
G

1.5K_0402_1%
1

MC74VHC1G08DFT2G SC70 5P @ Q27

3

R194 R192 2N7002_SOT23 2 1

G
2
R283 100K_0402_5%
750_0402_1%
3K_0402_1% PCH GPIO CONTROL 1 2 DRAMRST_CNTRL_R
<16> DRAMRST_CNTRL_PCH
R281 0_0402_5%
2

+5VALW 1 2
<34> DRAMRST_CNTRL_EC
R282 @ 0_0402_5%
EC GPIO CONTROL 1
1

0.01U_0402_16V7K
R610 C338
10K_0402_5%
2
A
6 A
2

S3_0.75V_EN
S3_0.75V_EN <44>
1

D
VCCP_POK 2
G
Q42 S
Security Classification
Classification Compal Secret Data Compal Electronics, Inc.
3

2N7002_SOT23 2008/10/31 2009/10/31 Title

Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Arrandale(1/5)-Thermal/XDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 5 of 51
5 4 3 2 1
 5 4 3 2 1

Layout rule：trace
length < 0.5"

JCPU1A JCPU1E
B26 EXP_ICOMPI 1 R544 2 49.9_0402_1%
PEG_ICOMPI
PEG_ICOMPO A26 RSVD32 AJ13
<15> DMI_CRX_PTX_N0 A24 DMI_RX#[0] PEG_RCOMPO B27 RSVD33 AJ12
<15> DMI_CRX_PTX_N1 C23 A25 EXP_RBIAS 1 R545 2 750_0402_1%
DMI_RX#[1] PEG_RBIAS
<15> DMI_CRX_PTX_N2 B22 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] <19> AP25 RSVD1
<15> DMI_CRX_PTX_N3 A21 K35 PCIE_CRX_GTX_N15 AL25 AH25
DMI_RX#[3] PEG_RX#[0] PCIE_CRX_GTX_N14 RSVD2 RSVD34
PEG_RX#[1] J34 AL24 RSVD3 RSVD35 AK26
<15> DMI_CRX_PTX_P0 B24 J33 PCIE_CRX_GTX_N13 AL22
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N12 RSVD4
<15> DMI_CRX_PTX_P1 D23 DMI_RX[1] PEG_RX#[3] G35 AJ33 RSVD5 RSVD36 AL26

DMI
D B23 G32 PCIE_CRX_GTX_N11 AG9 AR2 D
<15> DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4] RSVD6 RSVD_NCTF_37
<15> DMI_CRX_PTX_P3 A22 F34 PCIE_CRX_GTX_N10 M27
DMI_RX[3] PEG_RX#[5] PCIE_CRX_GTX_N9 RSVD7
PEG_RX#[6] F31 L28 RSVD8 RSVD38 AJ26
D24 D35 PCIE_CRX_GTX_N8 J17 AJ27
<15> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] SA_DIMM_VREF RSVD39
G24 E33 PCIE_CRX_GTX_N7 H17
<15> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] SB_DIMM_VREF
F23 C33 PCIE_CRX_GTX_N6 G25
<15> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9] RSVD11
H23 D32 PCIE_CRX_GTX_N5 G17
<15> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] RSVD12
B32 PCIE_CRX_GTX_N4 E31 AP1
PEG_RX#[11] PCIE_CRX_GTX_N3 RSVD13 RSVD_NCTF_40
<15> DMI_CTX_PRX_P0 D25 DMI_TX[0] PEG_RX#[12] C31 E30 RSVD14 RSVD_NCTF_41 AT2
F24 B28 PCIE_CRX_GTX_N2
<15> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
E23 B30 PCIE_CRX_GTX_N1 AT3
<15> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] RSVD_NCTF_42
G23 A31 PCIE_CRX_GTX_N0 AR1
<15> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] RSVD_NCTF_43
PCIE_CRX_GTX_P[0..15] <19>
J35 PCIE_CRX_GTX_P15
PEG_RX[0] PCIE_CRX_GTX_P14
PEG_RX[1] H34
H33 PCIE_CRX_GTX_P13 AL28
FDI_CTX_PRX_N0 PEG_RX[2] PCIE_CRX_GTX_P12 CFG0 RSVD45
<15> FDI_CTX_PRX_N0 E22 FDI_TX#[0] PEG_RX[3] F35 AM30 CFG[0] RSVD46 AL29
FDI_CTX_PRX_N1 D21 G33 PCIE_CRX_GTX_P11 AM28 AP30
<15> FDI_CTX_PRX_N1 FDI_TX#[1] PEG_RX[4] CFG[1] RSVD47
FDI_CTX_PRX_N2 D19 E34 PCIE_CRX_GTX_P10 AP31 AP32
<15> FDI_CTX_PRX_N2 FDI_TX#[2] PEG_RX[5] CFG[2] RSVD48
FDI_CTX_PRX_N3 D18 F32 PCIE_CRX_GTX_P9 CFG3 AL32 AL27
<15> FDI_CTX_PRX_N3 FDI_TX#[3] PEG_RX[6] CFG[3] RSVD49
FDI_CTX_PRX_N4 G21 D34 PCIE_CRX_GTX_P8 CFG4 AL30 AT31
<15> FDI_CTX_PRX_N4
FDI_CTX_PRX_N5 FDI_TX#[4] PEG_RX[7] PCIE_CRX_GTX_P7 PCIE Lane Numbers Reversed CFG[4] RSVD50

PCI EXPRESS -- GRAPHICS

<15> FDI_CTX_PRX_N5 E19 FDI_TX#[5] PEG_RX[8] F33 AM31 CFG[5] RSVD51 AT32
FDI_CTX_PRX_N6 F21 B33 PCIE_CRX_GTX_P6 AN29 AP33
<15> FDI_CTX_PRX_N6 FDI_TX#[6] PEG_RX[9] CFG[6] RSVD52
Intel(R) FDI
FDI_CTX_PRX_N7 G18 D31 PCIE_CRX_GTX_P5 @ R59 1 2 CFG7 AM32 AR33
<15> FDI_CTX_PRX_N7 FDI_TX#[7] PEG_RX[10]
PEG_RX[11] A32
C30
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P3
CFG3-PCI Express Static Lane Reversal 3.01K_0402_1% AK32
AK31
CFG[7]
CFG[8]
RSVD53
RSVD_NCTF_54 AT33
AT34

RESERVED
FDI_CTX_PRX_P0 PEG_RX[12] PCIE_CRX_GTX_P2 CFG[9] RSVD_NCTF_55
<15> FDI_CTX_PRX_P0 D22 FDI_TX[0] PEG_RX[13] A28 AK28 CFG[10] RSVD_NCTF_56 AP35
FDI_CTX_PRX_P1 PCIE_CRX_GTX_P1
<15> FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
C21
D20
FDI_TX[1] PEG_RX[14] B29
A30 PCIE_CRX_GTX_P0
FOR ES1 SAMPLE ONLY AJ28
AN30
CFG[11] RSVD_NCTF_57 AR35
AR32
<15> FDI_CTX_PRX_P2
FDI_CTX_PRX_P3 FDI_TX[2] PEG_RX[15] DIS@ CFG[12] RSVD58
<15> FDI_CTX_PRX_P3 C18 FDI_TX[3] PCIE_CTX_GRX_N[0..15] <19> AN32 CFG[13]
FDI_CTX_PRX_P4 G22 L33 PCIE_CTX_GRX_C_N15 C527 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N15 AJ32
<15> FDI_CTX_PRX_P4 FDI_TX[4] PEG_TX#[0] CFG[14]
FDI_CTX_PRX_P5 E20 M35 PCIE_CTX_GRX_C_N14 C540 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N14 AJ29 E15
C <15> FDI_CTX_PRX_P5
FDI_CTX_PRX_P6 F20
FDI_TX[5] PEG_TX#[1]
M33 PCIE_CTX_GRX_C_N13 C529 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N13 AJ30
CFG[15] RSVD_TP_59
F15 C
<15> FDI_CTX_PRX_P6 FDI_TX[6] PEG_TX#[2] CFG[16] RSVD_TP_60
FDI_CTX_PRX_P7 G19 M30 PCIE_CTX_GRX_C_N12 C542 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N12 AK30 A2
<15> FDI_CTX_PRX_P7 FDI_TX[7] PEG_TX#[3] CFG[17] KEY
L31 PCIE_CTX_GRX_C_N11 C531 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N11 H16 D15 R189
FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_C_N10 C544 0.1U_0402_10V6K PCIE_CTX_GRX_N10 RSVD_TP_86 RSVD62 0_0402_5%
<15> FDI_FSYNC0 F17 FDI_FSYNC[0] PEG_TX#[5] K32 1 2 RSVD63 C15
<15> FDI_FSYNC1 FDI_FSYNC1 E17 M29 PCIE_CTX_GRX_C_N9 C533 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N9 AJ15 RSVD64_R 2 @ 1
FDI_FSYNC[1] PEG_TX#[6] PCIE_CTX_GRX_C_N8 C546 0.1U_0402_10V6K PCIE_CTX_GRX_N8 RSVD64 RSVD65_R 2 @
PEG_TX#[7] J31 1 2 RSVD65 AH15 1
<15> FDI_INT FDI_INT C17 K29 PCIE_CTX_GRX_C_N7 C535 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N7 R188
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_C_N6 C562 0.1U_0402_10V6K PCIE_CTX_GRX_N6 0_0402_5%
PEG_TX#[9] H30 1 2 B19 RSVD15
<15> FDI_LSYNC0 FDI_LSYNC0 F18 H29 PCIE_CTX_GRX_C_N5 C564 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N5 R547 A19
FDI_LSYNC1 FDI_LSYNC[0] PEG_TX#[10] PCIE_CTX_GRX_C_N4 C555 0.1U_0402_10V6K PCIE_CTX_GRX_N4 0_0402_5% RSVD16
<15> FDI_LSYNC1 D17 FDI_LSYNC[1] PEG_TX#[11] F29 1 2
E28 PCIE_CTX_GRX_C_N3 C557 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N3 1 @ 2 H_RSVD17_R A20
PEG_TX#[12] PCIE_CTX_GRX_C_N2 C561 0.1U_0402_10V6K PCIE_CTX_GRX_N2 @ H_RSVD18_R RSVD17
PEG_TX#[13] D29 1 2 1 2 B20 RSVD18
D27 PCIE_CTX_GRX_C_N1 C548 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N1 AA5
PEG_TX#[14] PCIE_CTX_GRX_C_N0 C559 0.1U_0402_10V6K PCIE_CTX_GRX_N0 R546 RSVD_TP_66
PEG_TX#[15] C26 1 2 U9 RSVD19 RSVD_TP_67 AA4
0_0402_5% T9 R8
PCIE_CTX_GRX_P[0..15] <19> RSVD20 RSVD_TP_68
L34 PCIE_CTX_GRX_C_P15 C528 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P15 AD3
PEG_TX[0] PCIE_CTX_GRX_C_P14 C541 0.1U_0402_10V6K PCIE_CTX_GRX_P14 RSVD_TP_69
PEG_TX[1] M34 1 2 AC9 RSVD21 RSVD_TP_70 AD2
M32 PCIE_CTX_GRX_C_P13 C530 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P13 AB9 AA2
PEG_TX[2] PCIE_CTX_GRX_C_P12 C543 0.1U_0402_10V6K PCIE_CTX_GRX_P12 RSVD22 RSVD_TP_71
PEG_TX[3] L30 1 2 RSVD_TP_72 AA1
M31 PCIE_CTX_GRX_C_P11 C532 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P11 R9
PEG_TX[4] PCIE_CTX_GRX_C_P10 C545 0.1U_0402_10V6K PCIE_CTX_GRX_P10 RSVD_TP_73
PEG_TX[5] K31 1 2 RSVD_TP_74 AG7
M28 PCIE_CTX_GRX_C_P9 C534 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P9 C1 AE3
PEG_TX[6] PCIE_CTX_GRX_C_P8 C547 0.1U_0402_10V6K PCIE_CTX_GRX_P8 RSVD_NCTF_23 RSVD_TP_75
PEG_TX[7] H31 1 2 A3 RSVD_NCTF_24
K28 PCIE_CTX_GRX_C_P7 C536 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P7
PEG_TX[8] PCIE_CTX_GRX_C_P6 C563 0.1U_0402_10V6K PCIE_CTX_GRX_P6
PEG_TX[9] G30 1 2 RSVD_TP_76 V4
G29 PCIE_CTX_GRX_C_P5 C565 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P5 V5
PEG_TX[10]
PEG_TX[11] F28
E27
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P3
C556
C558
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P3
CFG Straps for PROCESSOR J29
RSVD_TP_77
RSVD_TP_78 N2
AD5
PEG_TX[12] PCIE_CTX_GRX_C_P2 C560 0.1U_0402_10V6K PCIE_CTX_GRX_P2 RSVD26 RSVD_TP_79
PEG_TX[13] D28 1 2 J28 RSVD27 RSVD_TP_80 AD7
C27 PCIE_CTX_GRX_C_P1 C549 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P1 W3
PEG_TX[14] PCIE_CTX_GRX_C_P0 C550 0.1U_0402_10V6K PCIE_CTX_GRX_P0 RSVD_TP_81
PEG_TX[15] C25 1 2 A34 RSVD_NCTF_28 RSVD_TP_82 W2
A33 RSVD_NCTF_29 RSVD_TP_83 N3
B CFG0 1 @ 2 AE5 B
R58 3.01K_0402_1% RSVD_TP_84
C35 RSVD_NCTF_30 RSVD_TP_85 AD9
IC,AUB_CFD_rPGA,R1P0 B35
ME@ PCI-Express Configuration Select RSVD_NCTF_31
1: Single PEG AP34
CFG0 0: Bifurcation enabled VSS
Not applicable for Clarksfield Processor

CFG[1:0] 11=1*16 PEG

10=2*8 PEG IC,AUB_CFD_rPGA,R1P0
ME@

FDI_FSYNC0 R532 1 DIS@ 2 1K_0402_5% CFG3 1 2

R61 3.01K_0402_1%
FDI_FSYNC1 R536 1 DIS@ 2 1K_0402_5%
CFG3-PCI Express Static Lane Reversal
FDI_INT R534 1 DIS@ 2 1K_0402_5% 1: Normal Operation
CFG3 0: Lane Numbers Reversed
FDI_LSYNC0 R533 1 DIS@ 2 1K_0402_5% 15 -> 0, 14 ->1, .....

FDI_LSYNC1 R535 1 DIS@ 2 1K_0402_5% @

CFG4 1 2
R60 3.01K_0402_1%

CFG4-Display Port Presence

1: Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
0: Enabled; An external Display Port
device is connected to the Embedded
Display Port
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/31 Deciphered Date 2009/10/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Arrandale(2/5)-DMI/PEG/FDI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 6 of 51
5 4 3 2 1
 5 4 3 2 1

JCPU1D
JCPU1C

<11> DDR_B_D[0..63] SB_CK[0] W8 M_CLK_DDR2 <11>

D AA6 W9 D
SA_CK[0] M_CLK_DDR0 <10> SB_CK#[0] M_CLK_DDR#2 <11>
AA7 DDR_B_D0 B5 M3
<10> DDR_A_D[0..63] SA_CK#[0] M_CLK_DDR#0 <10> SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <11>
P7 DDR_B_D1 A5
SA_CKE[0] DDR_CKE0_DIMMA <10> SB_DQ[1]
DDR_A_D0 A10 DDR_B_D2 C3
DDR_A_D1 SA_DQ[0] DDR_B_D3 SB_DQ[2]
C10 SA_DQ[1] B3 SB_DQ[3] SB_CK[1] V7 M_CLK_DDR3 <11>
DDR_A_D2 C7 DDR_B_D4 E4 V6
SA_DQ[2] SB_DQ[4] SB_CK#[1] M_CLK_DDR#3 <11>
DDR_A_D3 A7 Y6 DDR_B_D5 A6 M2
SA_DQ[3] SA_CK[1] M_CLK_DDR1 <10> SB_DQ[5] SB_CKE[1] DDR_CKE3_DIMMB <11>
DDR_A_D4 B10 Y5 DDR_B_D6 A4
SA_DQ[4] SA_CK#[1] M_CLK_DDR#1 <10> SB_DQ[6]
DDR_A_D5 D10 P6 DDR_B_D7 C4
SA_DQ[5] SA_CKE[1] DDR_CKE1_DIMMA <10> SB_DQ[7]
DDR_A_D6 E10 DDR_B_D8 D1
DDR_A_D7 SA_DQ[6] DDR_B_D9 SB_DQ[8]
A8 SA_DQ[7] D2 SB_DQ[9]
DDR_A_D8 D8 DDR_B_D10 F2 AB8
SA_DQ[8] SB_DQ[10] SB_CS#[0] DDR_CS2_DIMMB# <11>
DDR_A_D9 F10 AE2 DDR_B_D11 F1 AD6
SA_DQ[9] SA_CS#[0] DDR_CS0_DIMMA# <10> SB_DQ[11] SB_CS#[1] DDR_CS3_DIMMB# <11>
DDR_A_D10 E6 AE8 DDR_B_D12 C2
SA_DQ[10] SA_CS#[1] DDR_CS1_DIMMA# <10> SB_DQ[12]
DDR_A_D11 F7 DDR_B_D13 F5
DDR_A_D12 SA_DQ[11] DDR_B_D14 SB_DQ[13]
E9 SA_DQ[12] F3 SB_DQ[14]
DDR_A_D13 B7 DDR_B_D15 G4 AC7
SA_DQ[13] SB_DQ[15] SB_ODT[0] M_ODT2 <11>
DDR_A_D14 E7 AD8 DDR_B_D16 H6 AD1
SA_DQ[14] SA_ODT[0] M_ODT0 <10> SB_DQ[16] SB_ODT[1] M_ODT3 <11>
DDR_A_D15 C6 AF9 DDR_B_D17 G2
SA_DQ[15] SA_ODT[1] M_ODT1 <10> SB_DQ[17]
DDR_A_D16 H10 DDR_B_D18 J6
DDR_A_D17 SA_DQ[16] DDR_B_D19 SB_DQ[18]
G8 SA_DQ[17] J3 SB_DQ[19]
DDR_A_D18 K7 DDR_B_D20 G1
SA_DQ[18] SB_DQ[20] DDR_B_DM[0..7] <11>
DDR_A_D19 J8 DDR_B_D21 G5 D4 DDR_B_DM0
DDR_A_D20 SA_DQ[19] DDR_B_D22 SB_DQ[21] SB_DM[0] DDR_B_DM1
G7 SA_DQ[20] J2 SB_DQ[22] SB_DM[1] E1
DDR_A_D21 G10 DDR_B_D23 J1 H3 DDR_B_DM2
SA_DQ[21] DDR_A_DM[0..7] <10> SB_DQ[23] SB_DM[2]
DDR_A_D22 J7 B9 DDR_A_DM0 DDR_B_D24 J5 K1 DDR_B_DM3
DDR_A_D23 SA_DQ[22] SA_DM[0] DDR_A_DM1 DDR_B_D25 SB_DQ[24] SB_DM[3] DDR_B_DM4
J10 SA_DQ[23] SA_DM[1] D7 K2 SB_DQ[25] SB_DM[4] AH1
DDR_A_D24 L7 H7 DDR_A_DM2 DDR_B_D26 L3 AL2 DDR_B_DM5
DDR_A_D25 SA_DQ[24] SA_DM[2] DDR_A_DM3 DDR_B_D27 SB_DQ[26] SB_DM[5] DDR_B_DM6
M6 SA_DQ[25] SA_DM[3] M7 M1 SB_DQ[27] SB_DM[6] AR4
DDR_A_D26 M8 AG6 DDR_A_DM4 DDR_B_D28 K5 AT8 DDR_B_DM7
DDR_A_D27 SA_DQ[26] SA_DM[4] DDR_A_DM5 DDR_B_D29 SB_DQ[28] SB_DM[7]
L9 SA_DQ[27] SA_DM[5] AM7 K4 SB_DQ[29]
DDR_A_D28 L6 AN10 DDR_A_DM6 DDR_B_D30 M4
C DDR_A_D29 SA_DQ[28] SA_DM[6] DDR_A_DM7 DDR_B_D31 SB_DQ[30] C
K8 SA_DQ[29] SA_DM[7] AN13 N5 SB_DQ[31]
DDR_A_D30 N8 DDR_B_D32 AF3
DDR_A_D31 SA_DQ[30] DDR_B_D33 SB_DQ[32]
P9 SA_DQ[31] AG1 SB_DQ[33] DDR_B_DQS#[0..7] <11>
DDR_A_D32 AH5 DDR_B_D34 AJ3 D5 DDR_B_DQS#0
DDR_A_D33 SA_DQ[32] DDR_B_D35 SB_DQ[34] SB_DQS#[0] DDR_B_DQS#1
AF5 SA_DQ[33] DDR_A_DQS#[0..7] <10> AK1 SB_DQ[35] SB_DQS#[1] F4
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D36 AG4 J4 DDR_B_DQS#2
SA_DQ[34] SA_DQS#[0] SB_DQ[36] SB_DQS#[2]
DDR SYSTEM MEMORY A

DDR_A_D35 AK7 F8 DDR_A_DQS#1 DDR_B_D37 AG3 L4 DDR_B_DQS#3

DDR_A_D36 SA_DQ[35] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D38 SB_DQ[37] SB_DQS#[3] DDR_B_DQS#4
AF6 SA_DQ[36] SA_DQS#[2] J9 AJ4 SB_DQ[38] SB_DQS#[4] AH2

DDR SYSTEM MEMORY - B

DDR_A_D37 AG5 N9 DDR_A_DQS#3 DDR_B_D39 AH4 AL4 DDR_B_DQS#5
DDR_A_D38 SA_DQ[37] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D40 SB_DQ[39] SB_DQS#[5] DDR_B_DQS#6
AJ7 SA_DQ[38] SA_DQS#[4] AH7 AK3 SB_DQ[40] SB_DQS#[6] AR5
DDR_A_D39 AJ6 AK9 DDR_A_DQS#5 DDR_B_D41 AK4 AR8 DDR_B_DQS#7
DDR_A_D40 SA_DQ[39] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D42 SB_DQ[41] SB_DQS#[7]
AJ10 SA_DQ[40] SA_DQS#[6] AP11 AM6 SB_DQ[42]
DDR_A_D41 AJ9 AT13 DDR_A_DQS#7 DDR_B_D43 AN2
DDR_A_D42 SA_DQ[41] SA_DQS#[7] DDR_B_D44 SB_DQ[43]
AL10 SA_DQ[42] AK5 SB_DQ[44]
DDR_A_D43 AK12 DDR_B_D45 AK2
DDR_A_D44 SA_DQ[43] DDR_B_D46 SB_DQ[45]
AK8 SA_DQ[44] AM4 SB_DQ[46]
DDR_A_D45 AL7 DDR_B_D47 AM3
SA_DQ[45] DDR_A_DQS[0..7] <10> SB_DQ[47] DDR_B_DQS[0..7] <11>
DDR_A_D46 AK11 C8 DDR_A_DQS0 DDR_B_D48 AP3 C5 DDR_B_DQS0
DDR_A_D47 SA_DQ[46] SA_DQS[0] DDR_A_DQS1 DDR_B_D49 SB_DQ[48] SB_DQS[0] DDR_B_DQS1
AL8 SA_DQ[47] SA_DQS[1] F9 AN5 SB_DQ[49] SB_DQS[1] E3
DDR_A_D48 AN8 H9 DDR_A_DQS2 DDR_B_D50 AT4 H4 DDR_B_DQS2
DDR_A_D49 SA_DQ[48] SA_DQS[2] DDR_A_DQS3 DDR_B_D51 SB_DQ[50] SB_DQS[2] DDR_B_DQS3
AM10 SA_DQ[49] SA_DQS[3] M9 AN6 SB_DQ[51] SB_DQS[3] M5
DDR_A_D50 AR11 AH8 DDR_A_DQS4 DDR_B_D52 AN4 AG2 DDR_B_DQS4
DDR_A_D51 SA_DQ[50] SA_DQS[4] DDR_A_DQS5 DDR_B_D53 SB_DQ[52] SB_DQS[4] DDR_B_DQS5
AL11 SA_DQ[51] SA_DQS[5] AK10 AN3 SB_DQ[53] SB_DQS[5] AL5
DDR_A_D52 AM9 AN11 DDR_A_DQS6 DDR_B_D54 AT5 AP5 DDR_B_DQS6
DDR_A_D53 SA_DQ[52] SA_DQS[6] DDR_A_DQS7 DDR_B_D55 SB_DQ[54] SB_DQS[6] DDR_B_DQS7
AN9 SA_DQ[53] SA_DQS[7] AR13 AT6 SB_DQ[55] SB_DQS[7] AR7
DDR_A_D54 AT11 DDR_B_D56 AN7
DDR_A_D55 SA_DQ[54] DDR_B_D57 SB_DQ[56]
AP12 SA_DQ[55] AP6 SB_DQ[57]
DDR_A_D56 AM12 DDR_B_D58 AP8
DDR_A_D57 SA_DQ[56] DDR_B_D59 SB_DQ[58]
AN12 SA_DQ[57] DDR_A_MA[0..15] <10> AT9 SB_DQ[59]
DDR_A_D58 AM13 Y3 DDR_A_MA0 DDR_B_D60 AT7
DDR_A_D59 SA_DQ[58] SA_MA[0] DDR_A_MA1 DDR_B_D61 SB_DQ[60]
AT14 SA_DQ[59] SA_MA[1] W1 AP9 SB_DQ[61]
DDR_A_D60 AT12 AA8 DDR_A_MA2 DDR_B_D62 AR10
B SA_DQ[60] SA_MA[2] SB_DQ[62] DDR_B_MA[0..15] <11> B
DDR_A_D61 AL13 AA3 DDR_A_MA3 DDR_B_D63 AT10 U5 DDR_B_MA0
DDR_A_D62 SA_DQ[61] SA_MA[3] DDR_A_MA4 SB_DQ[63] SB_MA[0] DDR_B_MA1
AR14 SA_DQ[62] SA_MA[4] V1 SB_MA[1] V2
DDR_A_D63 AP14 AA9 DDR_A_MA5 T5 DDR_B_MA2
SA_DQ[63] SA_MA[5] DDR_A_MA6 SB_MA[2] DDR_B_MA3
SA_MA[6] V8 SB_MA[3] V3
T1 DDR_A_MA7 R1 DDR_B_MA4
SA_MA[7] DDR_A_MA8 SB_MA[4] DDR_B_MA5
SA_MA[8] Y9 <11> DDR_B_BS0 AB1 SB_BS[0] SB_MA[5] T8
AC3 U6 DDR_A_MA9 W5 R2 DDR_B_MA6
<10> DDR_A_BS0 SA_BS[0] SA_MA[9] <11> DDR_B_BS1 SB_BS[1] SB_MA[6]
AB2 AD4 DDR_A_MA10 R7 R6 DDR_B_MA7
<10> DDR_A_BS1 SA_BS[1] SA_MA[10] <11> DDR_B_BS2 SB_BS[2] SB_MA[7]
U7 T2 DDR_A_MA11 R4 DDR_B_MA8
<10> DDR_A_BS2 SA_BS[2] SA_MA[11] SB_MA[8]
U3 DDR_A_MA12 R5 DDR_B_MA9
SA_MA[12] DDR_A_MA13 SB_MA[9] DDR_B_MA10
SA_MA[13] AG8 <11> DDR_B_CAS# AC5 SB_CAS# SB_MA[10] AB5
T3 DDR_A_MA14 Y7 P3 DDR_B_MA11
SA_MA[14] <11> DDR_B_RAS# SB_RAS# SB_MA[11]
AE1 V9 DDR_A_MA15 AC6 R3 DDR_B_MA12
<10> DDR_A_CAS# SA_CAS# SA_MA[15] <11> DDR_B_WE# SB_WE# SB_MA[12]
AB3 AF7 DDR_B_MA13
<10> DDR_A_RAS# SA_RAS# SB_MA[13]
AE9 P5 DDR_B_MA14
<10> DDR_A_WE# SA_WE# SB_MA[14]
N1 DDR_B_MA15
SB_MA[15]

IC,AUB_CFD_rPGA,R1P0
ME@

IC,AUB_CFD_rPGA,R1P0
ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/31 Deciphered Date 2009/10/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Arrandale(3/5)-DDR III
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 7 of 51
5 4 3 2 1
 5 4 3 2 1

R132
GFX_IMON 2 1 1K_0402_5%

DIS@

+CPU_CORE

+GFX_CORE
AS NO CONNECT
JCPU1F
JCPU1G BUT A SMALL AMOUNT OF POWER
22U_0805_6.3V6M 10U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M AT21 (~15MW) MAYBE WASTED
VAXG1
AT19 VAXG2 VAXG_SENSE AR22 VCC_AXG_SENSE <47>
AT18 AT22 DESIGN GUIDE REV1.1

SENSE
LINES
1 1 1 1 1 1 1 1 VAXG3 VSSAXG_SENSE VSS_AXG_SENSE <47>
+VCCP C161 C160 C191 C190 C189 C159 C591 C592
48A 18A @ @ @ @
AT16 VAXG4 15A
AR21 VAXG5
D AG35 AH14 UMA@ UMA@ UMA@ UMA@ AR19 D
VCC1 VTT0_1 2 2 2 2 2 2 2 2 VAXG6

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

330U_D2_2.5VY_R9M
AG34 VCC2 VTT0_2 AH12 AR18 VAXG7
AG33 VCC3 VTT0_3 AH11 1 AR16 VAXG8 GFX_VID[0] AM22 GFXVR_VID_0 <47>

C201

C199

C198

C181

C554
AG32 AH10 1 1 1 1 AP21 AP22 R140
VCC4 VTT0_4 + VAXG9 GFX_VID[1] GFXVR_VID_1 <47>
22U_0805_6.3V6M 22U_0805_6.3V6M GFX_VR_EN 2 4.7K_0402_5%

GRAPHICS VIDs
AG31 VCC5 VTT0_5 J14 AP19 VAXG10 GFX_VID[2] AN22 GFXVR_VID_2 <47> 1
AG30 J13 22U_0805_6.3V6M 10U_0805_6.3V6M AP18 AP23
VCC6 VTT0_6 VAXG11 GFX_VID[3] GFXVR_VID_3 <47>
AG29 H14 AP16 AM23 UMA@
VCC7 VTT0_7 2 2 2 2 2 VAXG12 GFX_VID[4] GFXVR_VID_4 <47>
AG28 VCC8 VTT0_8 H12 AN21 VAXG13 GFX_VID[5] AP24 GFXVR_VID_5 <47>

GRAPHICS
AG27 VCC9 VTT0_9 G14 AN19 VAXG14 GFX_VID[6] AN24 GFXVR_VID_6 <47>
AG26 G13 R559 AN18
VCC10 VTT0_10 VAXG15 UMA@
AF35 VCC11 VTT0_11 G12 0_0402_5% AN16 VAXG16

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AF34 VCC12 VTT0_12 G11 DIS@ AM21 VAXG17 GFX_VR_EN AR25 GFX_VR_EN 1 2 R141 0_0402_5%
GFXVR_EN <47>
AF33 F14 AM19 AT25 GFXVR_DPRSLPVR <47>

2
VCC13 VTT0_13 VAXG18 GFX_DPRSLPVR

C271

C270

C216

C182

C200
AF32 VCC14 VTT0_14 F13 1 1 1 1 1 AM18 VAXG19 GFX_IMON AM24 GFX_IMON GFXVR_IMON <47>
AF31 F12 @ @ AM16
VCC15 VTT0_15 VAXG20
AF30 VCC16 VTT0_16 F11 AL21 VAXG21
AF29 VCC17 VTT0_17 E14 AL19 VAXG22
2 2 2 2 2 +1.5V_DDR3
AF28 E12 AL18
AF27
AF26
VCC18
VCC19
VCC20
VTT0_18
VTT0_19
VTT0_20
D14
D13
+VCCP AL16
AK21
VAXG23
VAXG24
VAXG25 VDDQ1 AJ1
1

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z
AD35 D12 AK19 AF1
1.1V RAIL POWER

VCC21 VTT0_21 VAXG26 VDDQ2

C254

C256

C253

C255

C257
AD34 D11 AK18 AE7

- 1.5V RAILS
VCC22 VTT0_22 VAXG27 VDDQ3 1 1 1 1 1

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AD33 VCC23 VTT0_23 C14 AK16 VAXG28 VDDQ4 AE4
AD32 VCC24 VTT0_24 C13 AJ21 VAXG29 VDDQ5 AC1

C219

C217

C274

C207
AD31 VCC25 VTT0_25 C12 1 1 1 1 AJ19 VAXG30 VDDQ6 AB7
2 2 2 2 2
AD30 VCC26 VTT0_26 C11 AJ18 VAXG31 VDDQ7 AB4
AD29 VCC27 VTT0_27 B14 AJ16 VAXG32 VDDQ8 Y1
AD28 VCC28 VTT0_28 B12 AH21 VAXG33 VDDQ9 W7
2 2 2 2

POWER
AD27 VCC29 VTT0_29 A14 AH19 VAXG34 3A VDDQ10 W4
AD26 VCC30 VTT0_30 A13 AH18 VAXG35 VDDQ11 U1

220U_B2_2.5VM_R35

22U_0805_6.3V6M

22U_0805_6.3V6M
AC35 VCC31 VTT0_31 A12 AH16 VAXG36 VDDQ12 T7
AC34 VCC32 VTT0_32 A11 VDDQ13 T4 1 Modify for cost revew.

C268

C252

C258
C AC33 P1 C
VCC33 +VCCP VDDQ14 @ +
1 1 09/16/2009
AC32 VCC34 VDDQ15 N7
AC31 +VCCP N4
VCC35 VDDQ16

DDR3
AC30 VCC36 VTT0_33 AF10 VDDQ17 L1
2 2 2
10U_0805_6.3V6M

10U_0805_6.3V6M

AC29 VCC37 VTT0_34 AE10 J24 VTT1_45 VDDQ18 H1

10U_0805_6.3V6M

10U_0805_6.3V6M

FDI
AC28 VCC38 VTT0_35 AC10 J23 VTT1_46
CPU CORE SUPPLY

C208

C209

AC27 VCC39 VTT0_36 AB10 1 1 H25 VTT1_47 +VCCP

C210

C211
AC26 VCC40 VTT0_37 Y10 1 1
AA35 VCC41 VTT0_38 W10
AA34 VCC42 VTT0_39 U10 VTT0_59 P10
2 2

10U_0805_6.3V6M

10U_0805_6.3V6M
AA33 VCC43 VTT0_40 T10 VTT0_60 N10
2 2
AA32 VCC44 VTT0_41 J12 VTT0_61 L10

C273

C212
AA31 VCC45 VTT0_42 J11 VTT0_62 K10 1 1
AA30 VCC46 VTT0_43 J16
AA29 VCC47 VTT0_44 J15
AA28 VCC48 +VCCP 2 2
AA27 VCC49

1.1V
AA26 VCC50 VTT1_63 J22
Y35 K26 J20 +VCCP
VCC51 VTT1_48 VTT1_64

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
Y34 VCC52 J27 VTT1_49 VTT1_65 J18

PEG & DMI

Y33 VCC53 J26 VTT1_50 VTT1_66 H21

C214

C215

C272

C240

10U_0805_6.3V6M

10U_0805_6.3V6M
Y32 VCC54 1 1 1 1 J25 VTT1_51 VTT1_67 H20
Y31 VCC55 H27 VTT1_52 VTT1_68 H19

C218

C213
Y30 R608 1 2 1K_0402_5% G28 1 1
VCC56 VTT1_53
Y29 VCC57 G27 VTT1_54
2 2 2 2
Y28 VCC58 G26 VTT1_55
Y27 VCC59 F26 VTT1_56 2 2
Y26 VCC60 E26 VTT1_57 VCCPLL1 L26

1.8V
V35 VCC61 PSI# AN33 PSI# <48> E25 VTT1_58 VCCPLL2 L27
+1.8VS
V34 0.6A M26
POWER

VCC62 VCCPLL3
V33 VCC63 H_VID[0..6] <48>
V32 AK35 H_VID0
VCC64 VID[0]

1U_0603_10V4Z

1U_0603_10V4Z

2.2U_0603_6.3V4Z

10U_0805_6.3V6M

4.7U_0603_6.3V6K
B V31 AK33 H_VID1 B
VCC65 VID[1]

C167

C149

C168

C170
V30 AK34 H_VID2 1 1 1 1 1
VCC66 VID[2]

C169
V29 AL35 H_VID3
VCC67 VID[3]
CPU VIDS

V28 AL33 H_VID4

VCC68 VID[4] H_VID5
V27 VCC69 VID[5] AM33
H_VID6 IC,AUB_CFD_rPGA,R1P0 2 2 2 2 2
V26 VCC70 VID[6] AM35
U35 AM34 PM_DPRSLPVR_R 1 2 ME@
VCC71 PROC_DPRSLPVR PROC_DPRSLPVR <48>
U34 R56 0_0402_5%
VCC72
U33 For Intel S3 Power Reduction.
U32
U31
VCC73
VCC74
VCC75 VTT_SELECT G15 VTT_SELECT VTT_SELECT <46>
1 +1.5V
2
J3
2 1 1
+1.5V_DDR3

U30 VCC76

@
U29 JUMP_43X118
VCC77
U28 VCC78
H_VTTVID1 = Low, 1.1V FOR Clarksfiel J2
U27 VCC79 2 2 1 1
U26 H_VTTVID1 = High, 1.05V FOR Auburndale +1.5V_DDR3
VCC80 +1.5V
2

@
R35 JUMP_43X118
VCC81

0.1U_0402_10V6K
R34 VCC82
CPU

C269
R33 VCC83 1

1
R32 AN35 IMVP_IMON <48> U11
VCC84 ISENSE @ R233
R31 VCC85 8 D S 1
R30 +5VALW 7 2 220_0402_5%
VCC86 D S 2

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
R29 0_0402_5% 6 3
VCC87 D S

C289

C288

C287

C286
R28 AJ34 VCC_SENSE 1 R554 2 VCCSENSE 5 4 1 1 1 1
SENSE LINES

VCCSENSE <48>

12
VCC88 VCC_SENSE D G D
R27 VCC89 VSS_SENSE AJ35 VSS_SENSE 1 2 VSSSENSE
VSSSENSE <48>
R26 R553 0_0402_5% SI4800BDY-T1-E3_SO8 SUSP 2 Q19
VCC90 R268 G BSS138_NL_SOT23-3
P35 VCC91 20K_0402_5% +1.5V_DDR3 2 2 2 2
P34 B15 VTT_SENSE <46> S

3
VCC92 VTT_SENSE
P33 VCC93 VSS_SENSE_VTT A15
P32 @ PAD T15 1.5V_DDR3_GATE
VCC94
2

P31 VCC95 D 1
1

P30 R267
A VCC96 Q23 C325 A
P29 VCC97 <39,44,45> SUSP 2 0_0402_5%
P28 G 2N7002_SOT23 0.1U_0603_25V7K
VCC98 @ 2
P27 S
3

VCC99
P26 VCC100 For Intel S3 Power Reduction.
Close to CPU
+CPU_CORE

VCCSENSE 1
R552
2
100_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/31 Deciphered Date 2009/10/31 Title
VSSSENSE 1 2
R551 100_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Arrandale(4/5)-PWR
IC,AUB_CFD_rPGA,R1P0 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ME@ Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 8 of 51
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE
CPU CORE
JCPU1H JCPU1I

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
AT20 VSS1 VSS81 AE34

C568

C585

C580

C579

C574

C573

C584

C578

C583

C577

C572

C571
AT17 AE33
AR31
VSS2
VSS3
VSS82
VSS83 AE32 K27 VSS161
1 1 1 1 1 1 1 1 1 1 1 1
Inside cavity
AR28 VSS4 VSS84 AE31 K9 VSS162
AR26 VSS5 VSS85 AE30 K6 VSS163 2 2 2 2 2 2 2 2 2 2 2 2
AR24 VSS6 VSS86 AE29 K3 VSS164
AR23 VSS7 VSS87 AE28 J32 VSS165
AR20 VSS8 VSS88 AE27 J30 VSS166
D AR17 AE26 J21 D
VSS9 VSS89 VSS167
AR15 VSS10 VSS90 AE6 J19 VSS168
AR12 VSS11 VSS91 AD10 H35 VSS169

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AR9 VSS12 VSS92 AC8 H32 VSS170
AR6 VSS13 VSS93 AC4 H28 VSS171

C147

C163

C162

C179

C193

C166

C148

C165

C194
AR3 VSS14 VSS94 AC2 H26 VSS172 1 1 1 1 1 1 1 1 1
AP20 AB35 H24
AP17
VSS15
VSS16
VSS95
VSS96 AB34 H22
VSS173
VSS174
between Inductor and socket
AP13 VSS17 VSS97 AB33 H18 VSS175 2 2 2 2 2 2 2 2 2
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177
AP4 VSS20 VSS100 AB30 H11 VSS178
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180
AN31 VSS23 VSS103 AB27 H2 VSS181

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
AN23 VSS24 VSS104 AB26 G34 VSS182

470U_D2T_2VM

470U_D2T_2VM

470U_D2T_2VM

470U_D2T_2VM
AN20 VSS25 VSS105 AB6 G31 VSS183 1 1 1 1

C195

C192

C88

C196

C180

C89

C197

C76

C75

C92

C164

C91

C90

C87

C129
AN17 VSS26 VSS106 AA10 G20 VSS184 1 1 1 1 1 1 1 1 1 1 1
AM29 Y8 G9 + + + +
VSS27 VSS107 VSS185
AM27 VSS28 VSS108 Y4 G6 VSS186
AM25 VSS29 VSS109 Y2 G3 VSS187 2 2 2 2 2 2 2 2 3 2 3 2 3 2 3 2 2 2 2
AM20 VSS30 VSS110 W35 F30 VSS188
AM17 VSS31 VSS111 W34 F27 VSS189
AM14 VSS32 VSS112 W33 F25 VSS190
AM11 VSS33 VSS113 W32 F22 VSS191
AM8 W31 F19
AM5
VSS34
VSS35
VSS114
VSS115 W30 F16
VSS192
VSS193
Under cavity
AM2 VSS36 VSS116 W29 E35 VSS194
AL34 W28 E32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
E29
E24
VSS195
VSS196
VSS197
VSS 470uF 4.5mohm
AL20 VSS40 VSS120 W6 E21 VSS198
C AL17 V10 E18 C
VSS41 VSS121 VSS199
AL12 VSS42 VSS122 U8 E13 VSS200
AL9 VSS43 VSS123 U4 E11 VSS201
AL6 VSS44 VSS124 U2 E8 VSS202
AL3 VSS45 VSS125 T35 E5 VSS203
AK29 T34 E2 AT35 VSS_NCTF1_R
VSS46 VSS126 VSS204 VSS_NCTF1 VSS_NCTF2_R
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1
AK25 T32 D30 AR34 VSS_NCTF3_R
VSS48 VSS128 VSS206 VSS_NCTF3 VSS_NCTF4_R
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34
AK17 T30 D9 B2 VSS_NCTF5_R

NCTF
VSS50 VSS130 VSS208 VSS_NCTF5 VSS_NCTF6_R
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1
AJ23 T28 D3 A35 VSS_NCTF7_R
VSS52 VSS132 VSS210 VSS_NCTF7
AJ20 VSS53 VSS133 T27 C34 VSS211
AJ17 VSS54 VSS134 T26 C32 VSS212
AJ14 VSS55 VSS135 T6 C29 VSS213
AJ11 VSS56 VSS136 R10 C28 VSS214
AJ8 VSS57 VSS137 P8 C24 VSS215
AJ5 VSS58 VSS138 P4 C22 VSS216
AJ2 VSS59 VSS139 P2 C20 VSS217
AH35 VSS60 VSS140 N35 C19 VSS218
AH34 VSS61 VSS141 N34 C16 VSS219
AH33 VSS62 VSS142 N33 B31 VSS220
AH32 VSS63 VSS143 N32 B25 VSS221
AH31 VSS64 VSS144 N31 B21 VSS222
AH30 VSS65 VSS145 N30 B18 VSS223
AH29 VSS66 VSS146 N29 B17 VSS224
AH28 VSS67 VSS147 N28 B13 VSS225
AH27 VSS68 VSS148 N27 B11 VSS226
AH26 VSS69 VSS149 N26 B8 VSS227
AH20 VSS70 VSS150 N6 B6 VSS228
AH17 VSS71 VSS151 M10 B4 VSS229
AH13 VSS72 VSS152 L35 A29 VSS230
B AH9 L32 A27 B
VSS73 VSS153 VSS231
AH6 VSS74 VSS154 L29 A23 VSS232
AH3 VSS75 VSS155 L8 A9 VSS233
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2
AF4 VSS78 VSS158 K34
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30

IC,AUB_CFD_rPGA,R1P0 IC,AUB_CFD_rPGA,R1P0
ME@ ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/31 Deciphered Date 2009/10/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Arrandale(5/5)-GND/Bypass
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 9 of 51
5 4 3 2 1
 5 4 3 2 1

+VREF_DQ_DIMMA +1.5V +1.5V

3A@1.5V
<7> DDR_A_D[0..63] +1.5V
DDR3 SO-DIMM A <7> DDR_A_DM[0..7]

1
JDIMM1
<7> DDR_A_DQS[0..7]
+VREF_DQ_DIMMA 1 2 R297
VREF_DQ VSS1 DDR_A_D4 1K_0402_1%
3 VSS2 DQ4 4 <7> DDR_A_DQS#[0..7] +VREF_DQ_DIMMA

0.1U_0402_10V6K

2.2U_0603_6.3V4Z
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5

C303

C347
1 1 DDR_A_D1 7 8 <7> DDR_A_MA[0..15]

2
DQ1 VSS3 DDR_A_DQS#0
9 VSS4 DQS#0 10
DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0
13 VSS5 VSS6 14

1
2 2 DDR_A_D2 DDR_A_D6
15 DQ2 DQ6 16
D DDR_A_D3 17 18 DDR_A_D7 D
DQ3 DQ7 R305
19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12 1K_0402_1%
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24

2
DQ9 DQ13
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS#1 DM1 DRAMRST#
29 DQS1 RESET# 30 DRAMRST# <5,11>
31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36 For Arranale only +VREF_DQ_DIMMA
37 VSS13 VSS14 38
DDR_A_D16 39 DQ16 DQ20 40 DDR_A_D20 supply from a external 1.5V voltage divide
DDR_A_D17 41 42 DDR_A_D21
DQ17 DQ21 circuit.
43 VSS15 VSS16 44
DDR_A_DQS#2 45 DQS#2 DM2 46 DDR_A_DM2 07/17/2009
DDR_A_DQS2 47 48
DQS2 VSS17 DDR_A_D22
49 VSS18 DQ22 50
DDR_A_D18 51 52 DDR_A_D23
DDR_A_D19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDR_A_D28
DDR_A_D24 VSS20 DQ28 DDR_A_D29
57 DQ24 DQ29 58
DDR_A_D25 59 60
DQ25 VSS21 DDR_A_DQS#3
61 VSS22 DQS#3 62
DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

<7> DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA

C CKE0 CKE1 DDR_CKE1_DIMMA <7> C
75 VDD1 VDD2 76
77 78 DDR_A_MA15
DDR_A_BS2 NC1 A15 DDR_A_MA14
<7> DDR_A_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
<7> M_CLK_DDR0 M_CLK_DDR0 101 102 M_CLK_DDR1
CK0 CK1 M_CLK_DDR1 <7>
<7> M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 <7>
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <7>
<7> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
BA0 RAS# DDR_A_RAS# <7>
111 VDD13 VDD14 112
<7> DDR_A_WE# DDR_A_WE# 113 114 DDR_CS0_DIMMA#
WE# S0# DDR_CS0_DIMMA# <7>
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <7>
117 VDD15 VDD16 118
DDR_A_MA13 119 120 M_ODT1
A13 ODT1 M_ODT1 <7> +VREF_DQ_DIMMA
<7> DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
S1# NC2
123 VDD17 VDD18 124 Layout Note:
125 NCTEST VREF_CA 126
127 VSS27 VSS28 128 Place near DIMM

0.1U_0402_10V6K

2.2U_0603_6.3V4Z
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

C346

C355
DDR_A_D33 131 132 DDR_A_D37 1 1
DQ33 DQ37
133 VSS29 VSS30 134
DDR_A_DQS#4 135 136 DDR_A_DM4
DDR_A_DQS4 DQS#4 DM4
137 DQS4 VSS31 138
B DDR_A_D38 2 2 B
139 VSS32 DQ38 140
DDR_A_D34 141 142 DDR_A_D39 +1.5V
DDR_A_D35 DQ34 DQ39
143 DQ35 VSS33 144
145 146 DDR_A_D44
VSS34 DQ44

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDR_A_D40 147 148 DDR_A_D45
DQ40 DQ45

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
DDR_A_D41 149 150 1
DQ41 VSS35

C589

C588

C586

C581

C310

C309

C570

C308

C314

C315

C317

C316
151 152 DDR_A_DQS#5 1 1 1 1 1 1 1 1 1 1 1 1
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5 + C569
153 DM5 DQS5 154
155 156 VDDQ(1.5V) = 220U_B2_2.5VM_R35
DDR_A_D42 VSS37 VSS38 DDR_A_D46 @ @
157 DQ42 DQ46 158
DDR_A_D43 DDR_A_D47 2 2 2 2 2 2 2 2 2 2 2 2 2
159 DQ43 DQ47 160 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52 6*0603 10uf (PER CONNECTOR)
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170 DDR_A_DM6 VTT(0.75V) =
DDR_A_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_A_D54 3*0805 10uf 4*0402 1uf
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178 VREF =
DQ51 VSS45 DDR_A_D60 +0.75VS
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61 1*0402 0.1uf 1*0402 2.2uf
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7 VDDSPD (3.3V)=
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 DM7 DQS7 188

C605

1U_0603_10V4Z

C607

1U_0603_10V4Z

C606

C300

1U_0603_10V4Z

C301

1U_0603_10V4Z
1U_0603_10V4Z
189 VSS49 VSS50 190 1*0402 0.1uf 1*0402 2.2uf
DDR_A_D58 191 192 DDR_A_D62 1 1 1 1 1
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
1 R570 2 195 VSS51 VSS52 196
10K_0402_5% 197 198 PM_EXTTS#1_R
SA0 EVENT# PM_EXTTS#1_R <5,11> 2 2 2 2 2
199 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 <11,12,14,28>
2.2U_0603_6.3V4Z

0.1U_0402_10V6K

201 202 SMB_CLK_S3

SA1 SCL SMB_CLK_S3 <11,12,14,28>
C608

C617

A 203 204 A
1 1 VTT1 VTT2 +0.75VS
1 10K_0402_5%
R571

205 206 0.65A@0.75V

G1 G2
2 2 FOX_AS0A626-U4SN-7F
ME@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/31 Deciphered Date 2009/10/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 10 of 51
5 4 3 2 1
 5 4 3 2 1

+VREF_DQ_DIMMB +1.5V 3A@1.5V +1.5V

<7> DDR_B_DQS#[0..7]

<7> DDR_B_D[0..63]
+1.5V
<7> DDR_B_DM[0..7]
JDIMM2
+VREF_DQ_DIMMB 1 2
VREF_DQ VSS <7> DDR_B_DQS[0..7]

1
3 4 DDR_B_D4
VSS DQ4
2.2U_0603_6.3V4Z

0.1U_0402_10V6K
DDR_B_D0 5 6 DDR_B_D5 R341
DQ0 DQ5 <7> DDR_B_MA[0..15]
1 1 DDR_B_D1 7 8 1K_0402_1%
DQ1 VSS DDR_B_DQS#0 +VREF_DQ_DIMMB
9 VSS DQS0# 10
C382

C384
DDR_B_DM0 11 12 DDR_B_DQS0

2
DM0 DQS0
13 VSS VSS 14
2 2 DDR_B_D2 DDR_B_D6
15 DQ2 DQ6 16
D DDR_B_D3 17 18 DDR_B_D7 D
DQ3 DQ7

1
19 VSS VSS 20
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13 R340
23 DQ9 DQ13 24
25 26 1K_0402_1%
DDR_B_DQS#1 VSS VSS DDR_B_DM1
27 28

2
DDR_B_DQS1 DQS1# DM1 DRAMRST#
29 DQS1 RESET# 30 DRAMRST# <5,10>
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20 For Arranale only +VREF_DQ_DIMMB
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS VSS 44 supply from a external 1.5V voltage divide
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS2# DM2 circuit.
47 DQS2 VSS 48
49 VSS DQ22 50 DDR_B_D22 07/17/2009
DDR_B_D18 51 52 DDR_B_D23
DDR_B_D19 DQ18 DQ23
53 DQ19 VSS 54
55 56 DDR_B_D28
DDR_B_D24 VSS DQ28 DDR_B_D29
57 DQ24 DQ29 58
DDR_B_D25 59 60
DQ25 VSS DDR_B_DQS#3
61 VSS DQS3# 62
DDR_B_DM3 63 64 DDR_B_DQS3
DM3 DQS3
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72

<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 VDD VDD 76
C 77 78 DDR_B_MA15 C
DDR_B_BS2 NC A15 DDR_B_MA14
<7> DDR_B_BS2 79 BA2 A14 80
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
<7> M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3
CK0 CK1 M_CLK_DDR3 <7>
<7> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 <7>
105 VDD VDD 106
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <7>
<7> DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS# Layout Note:
BA0 RAS# DDR_B_RAS# <7>
111 VDD VDD 112
<7> DDR_B_WE# DDR_B_WE# 113 114 DDR_CS2_DIMMB#
DDR_CS2_DIMMB# <7>
Place near DIMM
DDR_B_CAS# WE# S0# M_ODT2
<7> DDR_B_CAS# 115 CAS# ODT0 116 M_ODT2 <7>
117 VDD VDD 118
DDR_B_MA13 119 120 M_ODT3
A13 ODT1 M_ODT3 <7> +VREF_DQ_DIMMB
<7> DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
S1# NC
123 VDD VDD 124
125 TEST VREF_CA 126
+1.5V
0.1U_0402_10V6K

2.2U_0603_6.3V4Z
127 VSS VSS 128
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36
C385

C383
DDR_B_D33 131 132 DDR_B_D37 1 1
DQ33 DQ37

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
133 VSS VSS 134

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
DDR_B_DQS#4 135 136 DDR_B_DM4
DQS4# DM4

C582

C587

C576

C311

C313

C590

C575

C312

C307

C304

C305

C306
DDR_B_DQS4 137 138 1 1 1 1 1 1 1 1 1 1 1 1
DQS4 VSS DDR_B_D38 2 2
139 VSS DQ38 140
B DDR_B_D34 141 142 DDR_B_D39 B
DDR_B_D35 DQ34 DQ39 @ @
143 DQ35 VSS 144
DDR_B_D44 2 2 2 2 2 2 2 2 2 2 2 2
145 VSS DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 DQ41 VSS 150
151 152 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
153 DM5 DQS5 154 VDDQ(1.5V) =
155 VSS VSS 156
DDR_B_D42 157 158 DDR_B_D46 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS VSS 162 6*0603 10uf (PER CONNECTOR)
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166 Layout Note:
167 VSS VSS 168 VTT(0.75V) =
DDR_B_DQS#6 169 DQS6# DM6 170 DDR_B_DM6 Place near DIMM
DDR_B_DQS6 171 172 3*0805 10uf 4*0402 1uf
DQS6 VSS DDR_B_D54
173 VSS DQ54 174
DDR_B_D50 175 176 DDR_B_D55
DDR_B_D51 DQ50 DQ55
177 DQ51 VSS 178
DDR_B_D60 +0.75VS
179 VSS DQ60 180 1*0402 0.1uf 1*0402 2.2uf
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS 184 VDDSPD (3.3V)=
185 186 DDR_B_DQS#7
DDR_B_DM7 VSS DQS7# DDR_B_DQS7
187 DM7 DQS7 188 1*0402 0.1uf 1*0402 2.2uf

10U_0603_6.3V6M

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z
189 VSS VSS 190

C596

C595

C299

C598
DDR_B_D58 191 192 DDR_B_D62 1 1 1 1
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
195 VSS VSS 196
1 R572 2 197 SA0 EVENT# 198 PM_EXTTS#1_R
PM_EXTTS#1_R <5,10>
10K_0402_5% SMB_DATA_S3 2 2 2 2
199 VDDSPD SDA 200 SMB_DATA_S3 <10,12,14,28>
1 2 201 202 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 <10,12,14,28>
2.2U_0603_6.3V4Z

0.1U_0402_10V6K

R573 10K_0402_5% 203 204 +0.75VS

VTT VTT 0.65A@0.75V
C618

C616

A A
1 1
205 GND1 GND1 206

2 2
TYCO_2-2013297-2~D
ME@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/31 Deciphered Date 2009/10/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 11 of 51
5 4 3 2 1
 5 4 3 2 1

Reserve for Low Power CLK GEN.

RTM890N-631(SA00003HQ00)
SLG8LV597VTR
9VLS3199 (SA00003HR00)
+3VS_CK505 VDD_3V3_1V5

1 @ 2
0_0603_5% R278
+1.5VS
D 1 PCS CAP(0.1u) BY 1 INPUT PIN D
1 2 VDD_3V3_1V5
0_0603_5% R269

10U_0805_10V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
C366

C334

C330
1 1 1 1

C336
2 2 2 2

CLK GEN TO PCH CLK GEN TO VGA

1. CLK_DMI
Unused
2. CLK_BUF_BCLK +3VS_CK505 +1.05VS_CK505 +3VS_CK505 +1.05VS_CK505
1. 27M_CLK
3. CLK_BUF_CKSSCD U14
1. 27M_CLK_SS
4. CLK_BUF_DOT96 VDD_3V3_1V5 1 VDD_USB_48 SCL 32 SMB_CLK_S3
SMB_CLK_S3 <10,11,14,28>
R318 0_0402_5% 2 31 SMB_DATA_S3
VSS_48M SDA SMB_DATA_S3 <10,11,14,28>
5. CLK_14M_PCH <14> CLK_BUF_DOT96
CLK_BUF_DOT96 1 2 L_CLK_BUF_DOT96 3 DOT_96 REF_0/CPU_SEL 30 REF_0/CPU_SEL 2 1 R315 CLK_14M_PCH CLK_14M_PCH <14>
CLK_BUF_DOT96# 1 2 L_CLK_BUF_DOT96# 4 29 33_0402_1%
<14> CLK_BUF_DOT96# DOT_96# VDD_REF
R319 0_0402_5% 5 28 CLK_XTAL_IN
VDD_27 XTAL_IN CLK_XTAL_OUT
6 27MHZ XTAL_OUT 27
7 27MHZ_SS VSS_REF 26
CLK_48M_CR_R 8 25 CK_PWRGD
USB_48 CKPWRGD/PD#
CLOSE U14
9 24 VDD_3V3_1V5 R275 0_0402_5%
CLK_BUF_CKSSCD R324 VSS_27M VDD_CPU
<14> CLK_BUF_CKSSCD 1 2 0_0402_5% CLK_BUF_CKSSCD_R 10 SATA CPU_0 23 R_CLK_BUF_BCLK 1 2 CLK_BUF_BCLK CLK_BUF_BCLK <14>
CLK_BUF_CKSSCD# R308 1 2 CLK_BUF_CKSSCD#_R 11 22 R_CLK_BUF_BCLK# 1 2 CLK_BUF_BCLK#
C <14> CLK_BUF_CKSSCD# SATA# CPU_0# CLK_BUF_BCLK# <14> C
0_0402_5% 12 21 R276 0_0402_5%
CLK_DMI R307 VSS_SRC VSS_CPU
<14> CLK_DMI 1 2 0_0402_5% L_CLK_DMI 13 SRC_1 CPU_1 20
CLK_DMI# R306 1 2 L_CLK_DMI# 14 19
<14> CLK_DMI# SRC_1# CPU_1#
0_0402_5% 15 18
R299 CPU_STOP# VDD_SRC_IO VDD_CPU_IO VDD_3V3_1V5
+3VS_CK505 1 2 16 CPU_STOP# VDD_SRC 17
10K_0402_5%
33 TGND
RTM890N-631-GRT QFN 32P
CK_PWRGD R298 1 2 +3VS_CK505
10K_0402_5%
+1.05VS +1.05VS_CK505
D

1
1 PCS CAP(0.1u) BY 1 INPUT PIN S IC SLG8SP587VTR QFN 32P CLK GEN (SA00002XY00) 2 CLK_EN# <48>
G
1
0_0603_5%
2
R277 S IC ICS9LRS3199AKLFT MLF 32P CLK GEN (SA000030P00) Q25 S

3
10U_0805_10V4Z

10U_0805_10V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

2N7002_SOT23-3
C332

C343

C335

1 1 1 1 1
C333

C331

1 2 CLK_48M_CR_R 2 1
CLK_48M_CR
33_0402_1% @ R322 0_0402_5% R323
2 2 2 2 2
@
unstuff 09.09.08
PIN8 IS GND FOR ICS3197
PIN8 IS 48MHz FOR ICS3199

B B
+3VS +3VS_CK505
C364 2 CLK_14M_PCH
1 PCS CAP(0.1u) BY 1 INPUT PIN 1
@ 10P_0402_50V8J
1 2 CLK_XTAL_OUT

14.31818MHZ_16PF_DSX840GA
0_0603_5% R279
10U_0805_10V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

CLK_XTAL_IN
C342

C350

C367

1 1 1 1
C344

C365 2 1 REF_0/CPU_SEL
@ 10P_0402_50V8J
2 2 2 2
Y1
EMI Capacitor
2 1

C348 C349
22P_0402_50V8J 22P_0402_50V8J

+1.05VS

PIN 30 CPU_0 CPU_1

1 2 REF_0/CPU_SEL
R317 @ 10K_0402_5%
0 (Default) 133MHz 133MHz
1 2
R316 10K_0402_5%
1 100MHz 100MHz
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/31 Deciphered Date 2009/10/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CLOCK GENERATOR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 12 of 51
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1

1 2 PCH_RTCX2
R154 10M_0402_5%

32.768KHZ_12.5PF_9H03200413
X1

OSC

OSC
1 1

15P_0402_50V8J
D C171 C183 D

NC

NC
15P_0402_50V8J
2 2
U7A

3
+RTCVCC PCH_RTCX1 B13 D33
1 RTCX1 FWH0 / LAD0 LPC_AD0 <28,34>

1
PCH_RTCX2 D13 B33
RTCX2 FWH1 / LAD1 LPC_AD1 <28,34>
C184 CLRP3 C32
FWH2 / LAD2 LPC_AD2 <28,34>
1U_0603_10V4Z SHORT PADS A32 LPC_AD3 <28,34>

2
2 PCH_RTCRST# FWH3 / LAD3
1 2 C14 RTCRST#
+RTCVCC R419 20K_0402_1% C34
+RTCVCC FWH4 / LFRAME# LPC_FRAME# <28,34>
1 2 PCH_SRTCRST# D17
R422 20K_0402_1% SRTCRST#
1 A34

RTC

LPC
LDRQ0#

1
R421 1 2 SM_INTRUDER# SM_INTRUDER# A16 F34 GPIO23 T7 PAD
+RTCBATT INTRUDER# LDRQ1# / GPIO23 +3VS
R144 1M_0402_5% C202 CLRP2 GPIO23 = NATIVE,3.3V,CORE
1 2 R420 1 2 PCH_INTVRMEN 1U_0603_10V4Z SHORT PADS PCH_INTVRMEN A14 AB9 SERIRQ
SERIRQ <34>

2
INTVRMEN SERIRQ
1

330K_0402_5% @ 2
2 100_0603_1% CLRP1 12P_0402_50V8J 1 2 C647 2 1
C441 SHORT PADS H：Integrated VRM enable 10K_0402_5% R479
*
2

L：Integrated VRM disable <33> HDA_BITCLK_CODEC

R168 1 2 33_0402_5% BITCLK A30 HDA_BCLK
0.1U_0402_16V4Z AK7 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 <32>
1 R167 1 HDA_SYNC SATA0RXN SATA_DTX_C_IRX_P0
2 33_0402_5% D29 AK6
+3VS
R452
1
@
2 PCH_SPKR
1K_0402_5%
<33> HDA_SYNC_CODEC
12P_0402_50V8J
1 2
C648 PCH_SPKR P1
HDA_SYNC SATA0RXP
SATA0TXN AK11
AK9
SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0
0.01U_0402_16V7K
0.01U_0402_16V7K
2
2
1 C140
1 C141
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
SATA_DTX_C_IRX_P0 <32>
SATA_ITX_DRX_N0 <32> HDD
<33> PCH_SPKR SPKR SATA0TXP SATA_ITX_DRX_P0 <32>
@
R169 1 2 33_0402_5% HDA_RST# C30
<33> HDA_RST_CODEC# HDA_RST#
AH6 SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 <32>
SATA1RXN SATA_DTX_C_IRX_P1
AH5
RF team request. HDA_SDIN0 G30 HDA_SDIN0
SATA1RXP
SATA1TXN AH9
AH8
SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1
0.01U_0402_16V7K
0.01U_0402_16V7K
2
2
1 C427
1 C428
SATA_ITX_DRX_N1
SATA_ITX_DRX_P1
SATA_DTX_C_IRX_P1 <32>
SATA_ITX_DRX_N1 <32> ODD
SATA1TXP SATA_ITX_DRX_P1 <32>
<33> HDA_SDIN1 HDA_SDIN1 F30 HDA_SDIN1
SATA2RXN AF11
C E32 AF9 C

IHDA
HDA_SDIN2 SATA2RXP
SATA2TXN AF7
F32 HDA_SDIN3 SATA2TXP AF6

SATA3RXN AH3
R166 1 2 33_0402_5% HDA_SDOUT B29 AH1
<33> HDA_SDOUT_CODEC HDA_SDO SATA3RXP
SATA3TXN AF3
GPIO33 = GPO , internal pull-up,should not be pulled low R409 1 @ 2 1K_0402_5%
SATA3TXP AF1
<34> ME_FLASH R425 1 2 0_0402_5% H32

SATA
HDA_DOCK_EN# / GPIO33 SATA_DTX_C_IRX_N4
flash ME core of strap pin pull down SATA4RXN AD9 SATA_DTX_C_IRX_N4 <37>
+3VALW R424 1 2 10K_0402_5% GPIO13 J30 AD8 SATA_DTX_C_IRX_P4 ESATA@ SATA_DTX_C_IRX_P4 <37>
HDA_DOCK_RST# / GPIO13 SATA4RXP
@ GPIO13 = GPI,3.3V,SUS AD6 SATA_ITX_C_DRX_N4 0.01U_0402_16V7K 2 1 C142 SATA_ITX_DRX_N4_CONN
SATA4TXN
SATA4TXP AD5 SATA_ITX_C_DRX_P4 0.01U_0402_16V7K 2 1 C143 SATA_ITX_DRX_P4_CONN
SATA_ITX_DRX_N4_CONN <37>
SATA_ITX_DRX_P4_CONN <37> E-SATA
PCH_JTAG_TCK M3 AD3 ESATA@
JTAG_TCK SATA5RXN
SATA5RXP AD1
PCH_JTAG_TMS K3 AB3
JTAG_TMS SATA5TXN
SATA5TXP AB1
PCH_JTAG_TDI K1 JTAG_TDI
(2009,07,07)

JTAG
PCH_JTAG_TDO J2 AF16
JTAG_TDO SATAICOMPO R500
+3VALW +3VALW +3VALW +3VALW PCH_JTAG_RST# J4 AF15 SATAICOMP 1 2 +3VS
TRST# SATAICOMPI +1.05VS
37.4_0402_1%
1

@ @ @ @ R99
R74 R72 R73 R75 SPI_CLK_PCH 1 2 SPI_CLK_PCH_R BA2 SPI_CLK

2
200_0402_5% 200_0402_5% 200_0402_5% 20K_0402_5%
0_0402_5% SPI_SB_CS0# AV3 1 2 +3VS R447 R482
SPI_CS0# R453 10K_0402_5% 10K_0402_5% 10K_0402_5%
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_RST# AY3 T3

SPI_CS1# SATALED# HDD_LED# <36>

1
1

B @ @ @ @ GPIO21 = GPI,3.3V,CORE B
R117 R115 R116 R118 SPI_SI AY1 Y9 GPIO21 GPIO21
10K_0402_5% SPI_MOSI SATA0GP / GPIO21
100_0402_1% 100_0402_1% 100_0402_1%

SPI
SPI_SO_R AV1 V1 GPIO19 GPIO19
SPI_MISO SATA1GP / GPIO19
GPIO19 = GPI,3.3V,CORE
2

IBEXPEAK-M_FCBGA1071 SPI_CLK_PCH

1
R100
33_0402_5%
@
4MB SPI ROM FOR HM55

2
+3VS
PCH JTAG
Pre-Production
PCH JTAG
Production
PCH_JTAG_TCK R114 1 2 51_0402_5% (2009,05,04) & Non-share ROM. C138
PCH Pin RefDes 22P_0402_50V8J
ES1 ES2 MP R62 2 SPI_WP# @
* FOR INTEL DPDG REV1.6 (MAY 2009)
1
3.3K_0402_5%
R591 No Install 200ohm No Install
R102 1 2SPI_HOLD#
PCH_JTAG_TDO R590 No Install 100ohm No Install 3.3K_0402_5%
C460
+3VS
1 2
R103
R584 200ohm 200ohm No Install 15_0402_5% U3
0.1U_0402_16V4Z
SPI_SB_CS0# 1 2 1 8
CS# VCC
PCH_JTAG_TMS R583 100ohm 100ohm No Install SPI_SO_R 2 1 SPI_SO_L 2 7 SPI_HOLD#
R101 SPI_WP# SO HOLD# SPI_CLK_PCH
3 WP# SCLK 6
15_0402_5% 4 5 SPI_SI
A GND SI A
R587 200ohm 200ohm No Install S IC FL 32M W25Q32BVSSIG SOIC 8P

PCH_JTAG_TDI R586 100ohm 100ohm No Install

PCH_JTAG_TCK R580 51ohm 51ohm 51ohm

R595 20Kohm 20Kohm No Install
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/31 Deciphered Date 2009/10/31 Title

PCH_JTAG_RST# R594 10Kohm 10Kohm No Install THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(1/6)-HDA/JTAG/SATA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 13 of 51
5 4 3 2 1
 5 4 3 2 1

SMB_CLK_S3 1 2 SMBCLK 1 2
PCIE PORT LIST SMB_DATA_S3
R121
1
10K_0402_5%
2
+3VS
SMBDATA
R123
1
2.2K_0402_5%
2
+3VALW

R406 10K_0402_5% R78 2.2K_0402_5%

SML0CLK
PORT DEVICE 1
R148
2
2.2K_0402_5%
SML0DATA 1 2
R147 2.2K_0402_5%
1 X SML1CLK 1 2
R404 2.2K_0402_5%
2 WLAN SML1DATA 1 2
R403 2.2K_0402_5%
3 LAN GPIO74 1 2
R399 10K_0402_5%
4 3G EC_LID_OUT# <34> LID_OUT# 1 2
D R145 10K_0402_5% D
5 NEW CARD GPIO60 1 2
R400 10K_0402_5%
6 X
R407
7 X 0_0402_5%
8 X U7B Q8A
2N7002DW-T/R7_SOT363-6
BG30 B9 LID_OUT# 6 1 SMB_CLK_S3
PERN1 SMBALERT# / GPIO11 SMB_CLK_S3 <10,11,12,28>
BJ30 PERP1
GPIO11 = NATIVE,3.3V,SUS R122
BF29 H14 SMBCLK 0_0402_5%
PETN1 SMBCLK SMBCLK
BH29 SMBCLK 1 @ 2 SMB_CLK_S3

2
PETP1 SMBDATA
PCIE_PRX_DTX_N2 AW30 SMBDATA C8 SMBDATA +3VS DDR3*2 AND CLK GEN SMBDATA @ 2 SMB_DATA_S3
<28> PCIE_PRX_DTX_N2 PERN2 GPIO60 = NATIVE,3.3V,SUS 1
<28> PCIE_PRX_DTX_P2 PCIE_PRX_DTX_P2 BA30 Q8B
C230 1 PCIE_PTX_DRX_N2 BC30 PERP2 GPIO60 0_0402_5%
WLAN <28> PCIE_PTX_C_DRX_N2 2 0.1U_0402_10V6K PETN2 WLAN SML0ALERT# / GPIO60 J14 2N7002DW-T/R7_SOT363-6
C229 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_P2 BD30 3 4 SMB_DATA_S3 R119
<28> PCIE_PTX_C_DRX_P2 PETP2 SMB_DATA_S3 <10,11,12,28>
C6 SML0CLK
PCIE_PRX_DTX_N3 SML0CLK
<29> PCIE_PRX_DTX_N3 AU30

SMBus
PCIE_PRX_DTX_P3 PERN3 SML0DATA
<29> PCIE_PRX_DTX_P3 AT30 G8

5
C223 1 PCIE_PTX_DRX_N3 PERP3 SML0DATA
LAN 2 0.1U_0402_10V6K AU32 LAN
<29> PCIE_PTX_C_DRX_N3
C222 1 PETN3 GPIO74 = NATIVE,3.3V,SUS
<29> PCIE_PTX_C_DRX_P3 2 0.1U_0402_10V6K PCIE_PTX_DRX_P3 AV32 PETP3
M14 GPIO74
PCIE_PRX_DTX_N4 SML1ALERT# / GPIO74
<28> PCIE_PRX_DTX_N4 BA32 PERN4
<28> PCIE_PRX_DTX_P4 3G@ PCIE_PRX_DTX_P4 BB32 E10 SML1CLK R79 0_0402_5% EC_SMB_CK2 EC_SMB_CK2 <34>
C231 1 PCIE_PTX_DRX_N4 PERP4 SML1CLK / GPIO58
3G <28> PCIE_PTX_C_DRX_N4 2 0.1U_0402_10V6K BD32 PETN4 MINI1 EC_THERMAL
C232 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_P4 BE32 G12 SML1DATA R80 0_0402_5% EC_SMB_DA2 EC_SMB_DA2 <34>
<28> PCIE_PTX_C_DRX_P4 PETP4 SML1DATA / GPIO75
3G@

PCI-E*
<28> PCIE_PRX_DTX_N5 PCIE_PRX_DTX_N5 BF33 PERN5 DTS , read from EC
EXP <28> PCIE_PRX_DTX_P5 PCIE_PRX_DTX_P5 BH33 NEW CARD T13
PERP5 CL_CLK1

Controller
C220 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_N5 BG32
C <28> PCIE_PTX_C_DRX_N5 PETN5 C
C221 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_P5 BJ32 T11
<28> PCIE_PTX_C_DRX_P5 PETP5 CL_DATA1

Link
BA34 PERN6 CL_RST1# T9
AW34 PERP6 PEG_CLKREQ# <19>
BC34 PETN6
BD34 10K_0402_5% R412
PETP6 PEG_CLKREQ#
PEG_A_CLKRQ# / GPIO47 H1 1 2
AT34 PERN7 GPIO47 = 10Kohm PULL DOWN
AU34 PERP7
AU36 AD43 CLK_PCIE_VGA#_R R524 1 2 0_0402_5% CLK_PCIE_VGA#
PETN7 CLKOUT_PEG_A_N CLK_PCIE_VGA# <19>
AV36 AD45 CLK_PCIE_VGA_R R525 1 2 0_0402_5% CLK_PCIE_VGA
PETP7 CLKOUT_PEG_A_P CLK_PCIE_VGA <19>
BG34 AN4 CLK_EXP#_R R105 1 2 0_0402_5%
PERN8 CLKOUT_DMI_N CLK_EXP# <5>

PEG
BJ34 AN2 CLK_EXP_R R106 1 2 0_0402_5%
PERP8 CLKOUT_DMI_P CLK_EXP <5>
BG36 PETN8
BJ36 +3VS
PETP8 CLKOUT_DP_N
CLKOUT_DP_N / CLKOUT_BCLK1_N AT1
AT3 CLKOUT_DP_P +3VS
CLKOUT_DP_P / CLKOUT_BCLK1_P
AK48 CLKOUT_PCIE0N
AK47 CLKOUT_PCIE0P +3VS

From CLK BUFFER

CLKIN_DMI_N AW24 CLK_DMI# <12>
+3VALW R431 1 2 10K_0402_5% P9 BA24
PCIECLKRQ0# / GPIO73 CLKIN_DMI_P CLK_DMI <12>
R124 R82
GPIO73 = NATIVE,3.3V,SUS 2.2K_0402_5% 2.2K_0402_5%
<28> CLK_PCIE_WLAN1#
R196 1 2 0_0402_5% CLK_PCIE_WLAN1#_R AM43 CLKOUT_PCIE1N CLKIN_BCLK_N AP3 CLK_BUF_BCLK# <12>

2
WLAN R197 1 2 0_0402_5% CLK_PCIE_WLAN1_R AM45 AP1
<28> CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKIN_BCLK_P CLK_BUF_BCLK <12>
Q7A
<28> WLAN_CLKREQ1# U4 EC_SMB_DA2 6 1 SMB_EC_DA2_R
PCIECLKRQ1# / GPIO18 SMB_EC_DA2_R <19,31>
+3VS R454 1 2 10K_0402_5% F18
CLKIN_DOT_96N CLK_BUF_DOT96# <12>

5
GPIO18 = NATIVE,3.3V,CORE E18 2N7002DW-T/R7_SOT363-6
Nvidia thermal
CLKIN_DOT_96P CLK_BUF_DOT96 <12>
R220 1 2 0_0402_5% CLK_PCIE_LAN#_R AM47 Q7B
<29> CLK_PCIE_LAN#
R221 1 2 0_0402_5% CLK_PCIE_LAN_R CLKOUT_PCIE2N EC_SMB_CK2 SMB_EC_CK2_R sensor
B
LAN <29> CLK_PCIE_LAN AM48 CLKOUT_PCIE2P 3 4 SMB_EC_CK2_R <19,31> B
CLKIN_SATA_N / CKSSCD_N AH13 CLK_BUF_CKSSCD# <12>
N4 AH12 2N7002DW-T/R7_SOT363-6
<29> CLKREQ_LAN# PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P CLK_BUF_CKSSCD <12>
+3VS R113 1 2 10K_0402_5%
GPIO20 = NATIVE,3.3V,CORE
R223 1 3G@ 2 0_0402_5% CLK_PCIE_CARD_PCH#_R AH42 P41 CLK_14M_PCH R81 0_0402_5%
<28> CLK_PCIE_CARD_PCH# CLKOUT_PCIE3N REFCLK14IN CLK_14M_PCH <12>
3G R222 1 2 0_0402_5% CLK_PCIE_CARD_PCH_R AH41 EC_SMB_DA2 1 @ 2 SMB_EC_DA2_R
<28> CLK_PCIE_CARD_PCH CLKOUT_PCIE3P
3G@
<28> PCIECLKREQ3# A8 J42 CLK_PCI_FB
PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK CLK_PCI_FB <16>
+3VALW R120 1 2 10K_0402_5% R83 0_0402_5%
GPIO25 = NATIVE,3.3V,SUS EC_SMB_CK2 1 @ 2 SMB_EC_CK2_R
R224 1 2 0_0402_5% CLK_PCIE_EXP_PCH#_R AM51 AH51 XTAL25_IN
<28> CLK_PCIE_EXP_PCH# CLKOUT_PCIE4N XTAL25_IN
EXP R225 1 2 0_0402_5% CLK_PCIE_EXP_PCH_R AM53 AH53 XTAL25_OUT
<28> CLK_PCIE_EXP_PCH CLKOUT_PCIE4P XTAL25_OUT
<28> CLKREQ_EXP# CLKREQ_EXP# M9 AF38 R491 1 2 90.9_0402_1% +1.05VS
R435 1 PCIECLKRQ4# / GPIO26 XCLK_RCOMP
+3VALW 2 10K_0402_5%
GPIO26 = NATIVE,3.3V,SUS
XTAL25_IN
AJ50
AJ52
CLKOUT_PCIE5N
CLKOUT_PCIE5P
CLKOUTFLEX0 / GPIO64 T45

R198
EMI REQUEST 0303 XTAL25_OUT 1 2
+3VALW R434 1 2 10K_0402_5% H6 P43 CLK_PCI_DB_R 1 2 22_0402_5% Calpella @ R598 1M_0402_5%
Clock Flex

PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65 CLK_PCI_DB <28>

GPIO44 = NATIVE,3.3V,SUS @ CLK_PCI_FB CLK_14M_PCH @ Y4
schematic
AK53 CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66 T42 checklist REV1.6 1 2
AK51 CLKOUT_PEG_B_P

2
XTAL25_IN needs a
+3VALW R457 1 2 10K_0402_5% P13 N50 R209 R413 25MHZ_20P_1BG25000CK1A
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67 pull-down to GND via

18P_0402_50V8J

18P_0402_50V8J
GPIO56 = NATIVE,3.3V,SUS 33_0402_5% 33_0402_5%
@ @ a 0Ω resistor. 1 C630 1 C631
IBEXPEAK-M_FCBGA1071 @ @

1
C263 C439 C631
2 2
22P_0402_50V8J 22P_0402_50V8J
A @ @ A

0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/31 Deciphered Date 2009/10/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(2/6)-PCI-E/SMBUS/CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 14 of 51
5 4 3 2 1
 5 4 3 2 1

D D

U7C PCH_ENBKL U7D

<27> PCH_ENBKL
BA18 FDI_CTX_PRX_N0 T48 BJ46
FDI_RXN0 FDI_CTX_PRX_N0 <6> L_BKLTEN SDVO_TVCLKINN
<6> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BH17 FDI_CTX_PRX_N1 PCH_ENVDD T47 BG46
DMI0RXN FDI_RXN1 FDI_CTX_PRX_N1 <6> <27> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
<6> DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 BJ22 BD16 FDI_CTX_PRX_N2
DMI1RXN FDI_RXN2 FDI_CTX_PRX_N2 <6>
<6> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 AW20 BJ16 FDI_CTX_PRX_N3 Y48 BJ48
DMI2RXN FDI_RXN3 FDI_CTX_PRX_N3 <6> <27> PCH_PWM L_BKLTCTL SDVO_STALLN
<6> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BJ20 BA16 FDI_CTX_PRX_N4 BG48
DMI3RXN FDI_RXN4 FDI_CTX_PRX_N4 <6> SDVO_STALLP
BE14 FDI_CTX_PRX_N5 EDID_CLK AB48
FDI_RXN5 FDI_CTX_PRX_N5 <6> <27> EDID_CLK L_DDC_CLK
<6> DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BD24 BA14 FDI_CTX_PRX_N6 EDID_DATA Y45 BF45
DMI0RXP FDI_RXN6 FDI_CTX_PRX_N6 <6> <27> EDID_DATA L_DDC_DATA SDVO_INTN
<6> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BG22 BC12 FDI_CTX_PRX_N7 BH45
DMI1RXP FDI_RXN7 FDI_CTX_PRX_N7 <6> SDVO_INTP
<6> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BA20 1 R497 2 AB46
DMI_CTX_PRX_P3 DMI2RXP FDI_CTX_PRX_P0 L_CTRL_CLK
<6> DMI_CTX_PRX_P3 BG20 DMI3RXP FDI_RXP0 BB18 FDI_CTX_PRX_P0 <6> +3VS 1 2 10K_0402_5% V48 L_CTRL_DATA
BF17 FDI_CTX_PRX_P1 R496 10K_0402_5%
FDI_RXP1 FDI_CTX_PRX_P1 <6>
DMI_CRX_PTX_N0 BE22 BC16 FDI_CTX_PRX_P2 AP39 T51
<6> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP2 FDI_CTX_PRX_P2 <6> LVD_IBG SDVO_CTRLCLK

1
DMI_CRX_PTX_N1 BF21 BG16 FDI_CTX_PRX_P3 AP41 T53
<6> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP3 FDI_CTX_PRX_P3 <6> LVD_VBG SDVO_CTRLDATA
DMI_CRX_PTX_N2 BD20 AW16 FDI_CTX_PRX_P4 R502 T10 PAD
<6> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP4 FDI_CTX_PRX_P4 <6>
DMI_CRX_PTX_N3 BE18 BD14 FDI_CTX_PRX_P5 2.37K_0402_1% AT43
<6> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP5 FDI_CTX_PRX_P5 <6> LVD_VREFH
BB14 FDI_CTX_PRX_P6 AT42 BG44
FDI_RXP6 FDI_CTX_PRX_P6 <6> LVD_VREFL DDPB_AUXN
DMI_CRX_PTX_P0 BD22 BD12 FDI_CTX_PRX_P7 BJ44 R510 10K_0402_5%
<6> DMI_CRX_PTX_P0 FDI_CTX_PRX_P7 <6>

2
DMI_CRX_PTX_P1 DMI0TXP FDI_RXP7 DDPB_AUXP
<6> DMI_CRX_PTX_P1 BH21 DMI1TXP DDPB_HPD AU38 2 1

LVDS
DMI_CRX_PTX_P2 BC20 AV53
<6> DMI_CRX_PTX_P2 DMI2TXP <27> LVDS_ACLK# LVDSA_CLK# +3VS
DMI_CRX_PTX_P3 BD18 BJ14 FDI_INT AV51 BD42
<6> DMI_CRX_PTX_P3 DMI3TXP FDI_INT FDI_INT <6> <27> LVDS_ACLK LVDSA_CLK DDPB_0N
BC42

DMI
FDI
FDI_FSYNC0 DDPB_0P
FDI_FSYNC0 BF13 FDI_FSYNC0 <6> <27> LVDS_A0# BB47 LVDSA_DATA#0 DDPB_1N BJ42
+1.05VS BH25 BA52 BG42

Digital Display Interface

DMI_ZCOMP <27> LVDS_A1# LVDSA_DATA#1 DDPB_1P

1
BH13 FDI_FSYNC1 AY48 BB40
FDI_FSYNC1 FDI_FSYNC1 <6> <27> LVDS_A2# LVDSA_DATA#2 DDPB_2N
1 2 DMI_IRCOMP BF25 AV47 BA40 R504 R503
R520 49.9_0402_1% DMI_IRCOMP FDI_LSYNC0 LVDSA_DATA#3 DDPB_2P 2.2K_0402_5% 2.2K_0402_5%
FDI_LSYNC0 BJ12 FDI_LSYNC0 <6> DDPB_3N AW38
4mil width and place <27> LVDS_A0 BB48 LVDSA_DATA0 DDPB_3P BA38 UMA@ UMA@
BG14 FDI_LSYNC1 BA50
within 500mil of the PCH FDI_LSYNC1 <6> <27> LVDS_A1

2
FDI_LSYNC1 LVDSA_DATA1
<27> LVDS_A2 AY49 LVDSA_DATA2
+3VS AV48 Y49 HDMICLK_NB HDMICLK_NB <25>
LVDSA_DATA3 DDPC_CTRLCLK HDMIDAT_NB
DDPC_CTRLDATA AB49 HDMIDAT_NB <25>
2

C
Checklist0.8：MEPWROK R436 10K_0402_5%
C
can be connect to R448 1 2 +3VALW AP48 LVDSB_CLK#
PWROK if iAMT disable 10K_0402_5% AP47 LVDSB_CLK DDPC_AUXN BE44
DDPC_AUXP BD44
SYS_RST# T6 J12 PCIE_WAKE# AY53 AV40
PCIE_WAKE# <28> TMDS_B_HPD# <25>
1

R396 2 100K_0402_1% SYS_RESET# WAKE# LVDSB_DATA#0 DDPC_HPD

1 AT49 LVDSB_DATA#1
AU52 BE40 TMDS_B_DATA2#_PCH C638 1 2 0.1U_0402_10V6K
LVDSB_DATA#2 DDPC_0N TMDS_B_DATA2# <25>
<48> VGATE R398 1 @ 2 0_0402_5% SYS_PWROK M6 Y1 1 2 +3VS AT53 BD40 TMDS_B_DATA2_PCH C639 1 2 0.1U_0402_10V6K
SYS_PWROK CLKRUN# / GPIO32 LVDSB_DATA#3 DDPC_0P TMDS_B_DATA2 <25>
(2009,05,04) R108 10K_0402_5% BF41 TMDS_B_DATA1#_PCH C640 1 2 0.1U_0402_10V6K
DDPC_1N TMDS_B_DATA1# <25>
2

<34> ICH_POK R397 1 2 0_0402_5% System Power Management GPIO32 = GPO,3.3V,CORE AY51 LVDSB_DATA0 DDPC_1P BH41 TMDS_B_DATA1_PCH C641 1 2 0.1U_0402_10V6K
TMDS_B_DATA1 <25>
B17 AT48 BD38 TMDS_B_DATA0#_PCH C642 1 2 0.1U_0402_10V6K
PWROK LVDSB_DATA1 DDPC_2N TMDS_B_DATA0# <25>
R455 AU50 BC38 TMDS_B_DATA0_PCH C643 1 2 0.1U_0402_10V6K
LVDSB_DATA2 DDPC_2P TMDS_B_DATA0 <25>
0_0402_5% AT51 BB36 TMDS_B_CLK#_PCH C644 1 2 0.1U_0402_10V6K
LVDSB_DATA3 DDPC_3N TMDS_B_CLK# <25>
K5 P8 GPIO61 GPIO61 = NATIVE,3.3V,SUS BA36 TMDS_B_CLK_PCH C645 1 2 0.1U_0402_10V6K
TMDS_B_CLK <25>
1

MEPWROK SUS_STAT# / GPIO61 DDPC_3P

R146 1 2 10K_0402_5% A10 LAN_RST# SUSCLK / GPIO62 F3 GPIO62 GPIO62 = NATIVE,3.3V,SUS <26> DAC_BLU
DAC_BLU AA52 CRT_BLUE DDPD_CTRLCLK U50
UMA_HDMI@ HDMI
DAC_GRN AB53 U52
<26> DAC_GRN CRT_GREEN DDPD_CTRLDATA
DAC_RED AD53
<26> DAC_RED CRT_RED
PM_DRAM_PWRGD D9 E4
<5> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 SLP_S5# <34>
DDPD_AUXN BC46
<26> CRT_DDC_CLK V51 CRT_DDC_CLK DDPD_AUXP BD46
R401 2 1 PM_RSMRST# C16 H7 V53 AT38
+3VALW RSMRST# SLP_S4# SLP_S4# <34> <26> CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD
10K_0402_5%
DDPD_0N BJ40
R437 1 2 10K_0402_5% SUS_PWR_DN_ACK_R M1 P12 Y53 BG40
SUS_PWR_DN_ACK / GPIO30 SLP_S3# SLP_S3# <34> <26> CRT_HSYNC CRT_HSYNC DDPD_0P
<34> SUS_PWR_DN_ACK 1 2 <26> CRT_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
R599 @
0_0402_5% BG38
+3VALW DDPD_1P

CRT
<34> PBTN_OUT# PBTN_OUT# P5 K8 Can be left NC when IAMT is BF37
PWRBTN# SLP_M# CRT_IREF AD48 DDPD_2N
not support on the platfrom DAC_IREF DDPD_2P BH37

1K_0402_5%
R450 1 2 10K_0402_5% AB51 BE36
CRT_IRTN DDPD_3N

1
R492
<34> AC_PRESENT 1 2 AC_PRESENT_R P7 ACPRESENT / GPIO31 TP23 N2 DDPD_3P BD36
R451 0_0402_5%
GPIO31 = GPI,3.3V,SUS IBEXPEAK-M_FCBGA1071
+3VALW R77 1 2 8.2K_0402_1% GPIO72 A6 BJ10
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <5>
B B

2
GPIO30 = GPI,3.3V,SUS GPIO29 = GPO,3.3V,SUS
R165 1 2 10K_0402_5% F14 RI# SLP_LAN# / GPIO29 F6
If not using integrated
LAN,signal may be left as NC.
IBEXPEAK-M_FCBGA1071

CRT OUT
MC74VHC1G08DFT2G SC70 5P DAC_BLU R493 1 UMA@ 2 150_0402_1%
3

@
VGATE 1 DAC_GRN R495 1 UMA@ 2 150_0402_1%
G

A SYS_PWROK
Y 4
ICH_POK 2 DAC_RED R494 1 UMA@ 2 150_0402_1%
B
P

U28
5

RSMRST circuit SLP_S3# 1

R418
2
@ 10K_0402_5% +3VS
+3VS @ R402 SLP_S4# 1 2
0_0402_5% R417 @ 10K_0402_5%
1 2 SLP_S5# 1 2
Reserved R416 @ 10K_0402_5% EDID_CLK R458 UMA@ 2.2K_0402_5%
(2009,09,08) PM_RSMRST# EDID_DATA R498 UMA@ 2.2K_0402_5%
C

<34> EC_RSMRST# 3 1
Q14
E

BAV99DW-7_SOT363 MMBT3906_SOT23-3
B

1 2 +3VALW
1 2

R176 4.7K_0402_5%
5

D8B

D8A
BAV99DW-7_SOT363
R175
3

A A
1 2

2.2K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/31 Deciphered Date 2009/10/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(3/6)-DMI/GPIO/LVDS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 15 of 51
5 4 3 2 1
 5 4 3 2 1

U7E U7F
H40 AD0 NV_CE#0 AY9 GPIO8 GPIO0 = GPI,3.3V,CORE
N34 BD1 Weak internal PU, don't PD +3VS 1 2 GPIO0 Y3 AH45
AD1 NV_CE#1 10K_0402_5% R483 BMBUSY# / GPIO0 CLKOUT_PCIE6N
C44 AD2 NV_CE#2 AP15 CLKOUT_PCIE6P AH46
A38 BD8 1 2 GPIO1 C38 +3VS
AD3 NV_CE#3 10K_0402_5% R428 TACH1 / GPIO1
C36 AD4
J34 AV9 Check list Rev0.8 section1.23.2 1 2 GPIO6 D37
AD5 NV_DQS0 TACH2 / GPIO6

2
A40 BG8 10K_0402_5% R427 AF48
AD6 NV_DQS1 If not implemented, the CLKOUT_PCIE7N

MISC
D45 EC_SCI# J32 AF47 R110
AD7 Braidwood <34> EC_SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
E36 AD8 NV_DQ0 / NV_IO0 AP7 10K_0402_5%
H48 AP6 interface signals can be EC_SMI# F10
AD9 NV_DQ1 / NV_IO1 <34> EC_SMI# GPIO8
E40 AT6
left as No Connect (NC).

1
AD10 NV_DQ2 / NV_IO2 CPUSB#
C40 AD11 NV_DQ3 / NV_IO3 AT9 <28> CPUSB# K9 LAN_PHY_PWR_CTRL / GPIO12 A20GATE U2 GATEA20 <34>
M48 AD12 NV_DQ4 / NV_IO4 BB1
M45 AV6 +3VALW 1 2 GPIO15 T7
D AD13 NV_DQ5 / NV_IO5 GPIO15 D
GPIO15 1K_0402_5% R433
F53
M40
AD14
AD15
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
BB3
BA4 *
L：Intel ME Crypto Transport GPIO16 AA2 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3 CLK_CPU_BCLK# <5>
+3VS

NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4 Layer Security(TLS) chiper suite

1
J36 BB6 with no confidentiality GPIO17 F38 AM1
AD17 NV_DQ9 / NV_IO9 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLK <5>
K48 BD6 R111
AD18 NV_DQ10 / NV_IO10
F40 AD19 NV_DQ11 / NV_IO11 BB7 H：Intel ME Crypto Transport 1 2 GPIO22 Y7 SCLOCK / GPIO22 PECI BG10 H_PECI
H_PECI <5> 10K_0402_5%

GPIO
C42 BC8 Layer Security(TLS) chiper suite 10K_0402_5% R449
AD20 NV_DQ12 / NV_IO12 KB_RST# KB_RST#
K46 BJ8 with confidentiality H10 T1 KB_RST# <34>

2
AD21 NV_DQ13 / NV_IO13 GPIO27 if pull down to turn off 1.8V VR GPIO24 RCIN#
M51 AD22 NV_DQ14 / NV_IO14 BJ6
J52 BG6 2 @ 1 AB12 BE10
AD23 NV_DQ15 / NV_IO15 GPIO27 PROCPWRGD H_CPUPWRGD <5>

CPU
K51 AD24
it have weak internal PU 20K 10K_0402_5% R507
L34 BD3 NV_ALE +3VALW 1 2 GPIO28 V13 BD10 H_THERMTRIP#_L 1 R518 2
AD25 NV_ALE GPIO28 THRMTRIP# H_THERMTRIP# <5>
F42 AY6 NV_CLE 10K_0402_5% R446 56_0402_5%
AD26 NV_CLE

1
J40 AD27
GPIO27 2 1 GPIO34 M11 STP_PCI# / GPIO34
56 5%-->checklist 1.6
G46 within 500mil Default：Do not connect(floating) 10K_0402_5% R432 54.9 1%-->CRB 1.0 R519
AD28 NV_RCOMP 1 R104
F44 AD29 NV_RCOMP AU2 2 2 1 GPIO35 V6 SATACLKREQ# / GPIO35
56_0402_5%
M47 AD30
32.4_0402_1% High：Enables the internal VccVRM 10K_0402_5% R456
GPIO36

PCI
H36 AV7 @ to have a clean supply for analog AB7 BA22

2
AD31 NV_RB# SATA2GP / GPIO36 TP1
rails. no need to use on board +VCCP
J50 AY8 1 2 GPIO37 AB13 AW22
C/BE0# NV_WR#0_RE# filter circuit. 10K_0402_5% R481 SATA3GP / GPIO37 TP2
G42 C/BE1# NV_WR#1_RE# AY5
H47 1 2 GPIO38 V3 BB22
C/BE2# SLOAD / GPIO38 TP3
G34 C/BE3# NV_WE#_CK0 AV11 GPIO1 = GPI,3.3V,CORE 10K_0402_5% R109
NV_WE#_CK1 BF5 GPIO6 = GPI,3.3V,CORE 1 2 GPIO39 P3 SDATAOUT0 / GPIO39 TP4 AY45

GPIO18 = NATIVE,5V,CORE
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
G38
H51
PIRQA#
PIRQB# USB20_N0
GPIO7 = GPI,3.3V,CORE
GPIO8 = GPO,3.3V,SUS 6 +3VALW
10K_0402_5% R112
1 2 GPIO45 H3 PCIECLKRQ6# / GPIO45 TP5 AY46
DRAMRST_CNTRL_PCH
USB20_N0 <37> GPIO12 = GPI,3.3V,SUS
B37 H18 10K_0402_5% R76 +3VALW 2 1
PIRQC# USBP0N
GPIO52 = NATIVE,5V,CORE PCI_PIRQD# A44 PIRQD# USBP0P J18 USB20_P0
USB20_P0 <37> LEFT USB <5> DRAMRST_CNTRL_PCH
DRAMRST_CNTRL_PCH GPIO46 F1 PCIECLKRQ7# / GPIO46 TP6 AV43 R405 10K_0402_5%
GPIO54 = NATIVE,5V,CORE USBP1N A18 USB20_N1
USB20_N1 <37>
PCI_REQ0# F51 C18 USB20_P1 LEFT USB (COMBO) 1 2 GPIO48 AB6 AV45
REQ0# USBP1P USB20_P1 <37> SDATAOUT1 / GPIO48 TP7
PCI_REQ1# A46 N20 USB20_N2 10K_0402_5% R480
REQ1# / GPIO50 USBP2N USB20_N2 <27>
PCI_REQ2# B45 P20 USB20_P2 USB Camera PCH_TEMP_ALERT# AA4 AF13
C REQ2# / GPIO52 USBP2P USB20_P2 <27> <34> PCH_TEMP_ALERT# SATA5GP / GPIO49 TP8 C
PCI_REQ3# M53 J20 USB20_N3
REQ3# / GPIO54 USBP3N USB20_N3 <37>
L20 USB20_P3 RIGHT USB +3VALW 1 2 GPIO57 F8 M18
USBP3P USB20_P3 <37> GPIO57 TP9
PCI_GNT0# F48 F20 R415 10K_0402_5%
PCI_GNT1# GNT0# USBP4N
K45 GNT1# / GPIO51 USBP4P G20 TP10 N18
PCI_GNT2# F36 A20 USB20_N5 1 2
GNT2# / GPIO53 USBP5N USB20_N5 <38>
PCI_GNT3# H53 C20 USB20_P5 CARD READER R609 @ 10K_0402_5% A4 AJ24
GNT3# / GPIO55 USBP5P USB20_P5 <38> VSS_NCTF_1 TP11
M22 DIS@ A49

NCTF
USBP6N VSS_NCTF_2

RSVD
GPIO2 = GPI,5V,CORE PCI_PIRQE# B41 PIRQE# / GPIO2 USBP6P N22 R506 0_0402_5% A5 VSS_NCTF_3 TP12 AK41
GPIO3 = GPI,5V,CORE PCI_PIRQF# K53 PIRQF# / GPIO3 USBP7N B21 <28,34,39,42,44,46> SUSP# 1 2 VGA_EN <45> A50 VSS_NCTF_4
GPIO4 = GPI,5V,CORE PCI_PIRQG# A36 D21 A52 AK42
PIRQG# / GPIO4 USBP7P VSS_NCTF_5 TP13
GPIO5 = GPI,5V,CORE PCI_PIRQH# A48 PIRQH# / GPIO5 USBP8N H22 USB20_N8
USB20_N8 <28> A53 VSS_NCTF_6
J22 USB20_P8 WLAN B2 M32
USBP8P USB20_P8 <28> VSS_NCTF_7 TP14
USB

<28,34> PCI_RST# K6 PCIRST# USBP9N E22 B4 VSS_NCTF_8

USBP9P F22 B52 VSS_NCTF_9 TP15 N32
R408 2 1 100K_0402_1% PCI_SERR# E44 A22 USB20_N10 B53
SERR# USBP10N USB20_N10 <28> VSS_NCTF_10
PCI_PERR# E50 C22 USB20_P10 EXPRESS BE1 M30
PERR# USBP10P USB20_P10 <28> VSS_NCTF_11 TP16
G24 USB20_N11 BE53
USBP11N USB20_N11 <37> VSS_NCTF_12
GNT2 USBP11P H24 USB20_P11
USB20_P11 <37> Bluetooth BF1 VSS_NCTF_13 TP17 N30
PCI_IRDY# A42 L24 BF53
IRDY# USBP12N VSS_NCTF_14
Default-Internal pull up
* PCI_DEVSEL#
H44
F46
PAR
DEVSEL#
USBP12P
USBP13N
M24
A24 USB20_N13
USB20_N13 <28>
BH1
BH2
VSS_NCTF_15
VSS_NCTF_16
TP18 H12

Low=Configures DMI for ESI PCI_FRAME# C46 FRAME# USBP13P C24 USB20_P13
USB20_P13 <28> 3G CARD BH52 VSS_NCTF_17 TP19 AA23
compatible operation(for BH53 VSS_NCTF_18
servers only.Not for PCI_LOCK# D49 BJ1 AB45
PLOCK# USBRBIAS VSS_NCTF_19 NC_1
mobile/desktops) USBRBIAS# B25 1 2 BJ2 VSS_NCTF_20
PCI_STOP# D41 R164 22.6_0402_1% BJ4 AB38
PCI_TRDY# STOP# VSS_NCTF_21 NC_2
C48 TRDY# USBRBIAS D25 Within 500 mils minimum spacing to other BJ49 VSS_NCTF_22
BJ5 VSS_NCTF_23 NC_3 AB42
<34> PCI_PME# M7 signal is 15mil BJ50
PME# USB_OC#0 VSS_NCTF_24
OC0# / GPIO59 N16 USB_OC#0 <37> BJ52 VSS_NCTF_25 NC_4 AB41
PLT_RST# D5 J16 USB_OC#1 USB_OC#1 <37> BJ53
PLTRST# OC1# / GPIO40 USB_OC#2 VSS_NCTF_26
OC2# / GPIO41 F16 D1 VSS_NCTF_27 NC_5 T39
B N52 L16 USB_OC#3 D2 B
CLKOUT_PCI0 OC3# / GPIO42 USB_OC#4 VSS_NCTF_28
P53 CLKOUT_PCI1 OC4# / GPIO43 E14 D53 VSS_NCTF_29
R199 22_0402_5% P46 G16 USB_OC#5 E1 P6 INT3_3V#
<34> CLK_PCI_LPC 1
1
2
2
CLK_PCI_LPC_R
CLK_PCI_FB_R
P51
P48
CLKOUT_PCI2
CLKOUT_PCI3
OC5# / GPIO9
OC6# / GPIO10 F12
T15
USB_OC#6
USB_OC#7
E53
VSS_NCTF_30
VSS_NCTF_31
INIT3_3V#
C10 TP24
USB PORT LIST
<14> CLK_PCI_FB CLKOUT_PCI4 OC7# / GPIO14 TP24
22_0402_5%
R211 IBEXPEAK-M_FCBGA1071
IBEXPEAK-M_FCBGA1071 PORT DEVICE
+3VALW
+3VS +3VS PCI_GNT0# R212 1 @ 2 1K_0402_5% RP1
USB_OC#0 1 8
0 RIGHT SIDE
RP5 RP3 PCI_GNT1# R210 1 @ 2 1K_0402_5% Intel Anti-Theft Techonlogy USB_OC#1
PCI_REQ0# 1 8 PCI_PIRQG# 1 8 USB_OC#2
2
3
7
6
1 LEFT SIDE
PCI_PIRQB# 2 7 PCI_PIRQC# 2 7 High=Enabled USB_OC#3 4 5
2 CMOS
PCI_PIRQF# 3 6 PCI_PIRQA# 3 6 Boot BIOS Strap NV_ALE
PCI_REQ3# PCI_PIRQE# Low=Disable(floating) 8.2K_0804_8P4R_5% GPIO17
3 LEFT SIDE
4 5 4 5
PCI_GNT0# PCI_GNT1# Boot BIOS * 1
R429
2
10K_0402_5%
8.2K_0804_8P4R_5% 8.2K_0804_8P4R_5%
Location +1.8VS RP2 1 2 GPIO36 4
RP7 RP6 0 0 LPC USB_OC#4 1 8 R485 10K_0402_5%
5 CARD READER
PCI_REQ1# 1 8 PCI_DEVSEL# 1 8 NV_ALE @ R515 1 2 1K_0402_5% USB_OC#5 2 7
PCI_FRAME# 2 7 PCI_LOCK# 2 7 0 1 Reserved(NAND) USB_OC#6 3 6 +3VS 1 2 PCH_TEMP_ALERT#
6
PCI_TRDY# 3 6 PCI_SERR# 3 6 USB_OC#7 4 5 R484 10K_0402_5%
PCI_PIRQH# 4 5 PCI_PERR# 4 5 1 0 PCI DMI Termination Voltage 7
8.2K_0804_8P4R_5% 2 1 GPIO16
8.2K_0804_8P4R_5% 8.2K_0804_8P4R_5% 1 1 SPI * Set to Vcc when HIGH R107 10K_0402_5%
8 WIRELESS
NV_CLE NV_ALE
RP4 Set to Vss when LOW Enable Intel Anti-Theft @ EC_SCI#
PCI_STOP# 1 8 1 2 Technology：8.2K PU to +3VS
+3VS 1
R426
2
10K_0402_5% 9
PCI_IRDY# R149 0_0402_5% Weak internal
PCI_PIRQD#
2
3
7
6 PU,Do not pull low +3VS Disable Intel Anti-Theft +3VALW 1 @ 2 EC_SMI# 10 NEW CARD
PCI_REQ2# R414 10K_0402_5%
A
4 5
NV_CLE @ R98 1 2 1K_0402_5%
Technology：floating(internal PD) 11 BT A
8.2K_0804_8P4R_5% NV_CLE
MC74VHC1G08DFT2G SC70 5P 12
3

PCI_GNT3# @ R200 1 2 1K_0402_5% @ DMI termination voltage.

1 PLT_RST# weak internal PU, don't PD
13 3G
G

A
<5,19,28,29> BUF_PLT_RST# 4 Y
A16 swap overide Strap/Top-Block B 2
P

Swap Override jumper Security Classification Compal Secret Data Compal Electronics, Inc.
1

1 U5
5

Low=A16 swap 0.1U_0402_16V4Z

Issued Date 2008/08/12 Deciphered Date 2009/08/12 Title
override/Top-Block C646 R155
PCI_GNT3# Swap Override enabled 2
100K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(4/6)-PCI/USB/RSVD
High=Default * Size Document Number Rev
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
+3VS Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 16 of 51
5 4 3 2 1
 5 4 3 2 1

+1.05VS
DG1.1 no M3 U7J POWER +3VS_DAC +3VS
support and not +1.05VS R208
Intel LAN, VCCLAN
AP51 VCCACLK[1] VCCIO[5] V24 U7G POWER

1U_0402_6.3V6K
0.052A VCCIO[6] V26 1 2

C466

0.01U_0402_16V7K

10U_0805_6.3V6M

0.1U_0402_16V4Z
+1.05VS
Source=>GND AP53 VCCACLK[2] VCCIO[7] Y24 1 AB24 VCCCORE[1] VCCADAC[1] AE50

1U_0402_6.3V6K

10U_0603_6.3V6M
Y26 AB26 0_0603_5%
VCCIO[8] VCCCORE[2]

C470

C502

C477

C262

C478
@ R527 1 1 AB28 0.069A AE52 1 1 1
VCCCORE[3] VCCADAC[2]
1 2 AF23 VCCLAN[1] VCCSUS3_3[1] V28
2
AD26 VCCCORE[4] 1.524A

CRT
0_0603_5% 0.344A U28 AD28 AF53
VCCSUS3_3[2] VCCCORE[5] VSSA_DAC[1]
1

D AF24 U26 AF26 @ D

1 VCCLAN[2] VCCSUS3_3[3] 2 2 VCCCORE[6] 2 2 2
R486 @ C469

VCC CORE
PAD T8 VCCSUS3_3[4] U24 AF28 VCCCORE[7] VSSA_DAC[2] AF51
0_0402_5% 1U_0402_6.3V4Z P28 AF30 +3VS
VCCSUS3_3[5] VCCCORE[8]
1 2 Y20 DCPSUSBYP VCCSUS3_3[6] P26 AF31 VCCCORE[9]
2 C461 0.1U_0402_16V4Z N28 AH26
2

VCCSUS3_3[7] VCCCORE[10] +VCCA_LVDS R213

VCCSUS3_3[8] N26 AH28 VCCCORE[11] 1 UMA@ 2 0.022_0805_1%
AD38 VCCME[1] VCCSUS3_3[9] M28 AH30 VCCCORE[12]

1
+3VALW
VCCSUS3_3[10] M26 AH31 VCCCORE[13] 0.030A VCCALVDS AH38
R214
AD39 L28 AJ30

USB
+1.05VS VCCME[2] VCCSUS3_3[11] VCCCORE[14] 0_0402_5%
VCCSUS3_3[12] L26 AJ31 VCCCORE[15] VSSA_LVDS AH39

0.1U_0402_16V4Z
AD41 J28 DIS@
VCCME[3] VCCSUS3_3[13]

C224
J26 1

2
VCCSUS3_3[14] +1.05VS 0.1uH inductor, 200mA +1.8VS
1U_0402_6.3V6K
AF43 VCCME[4] VCCSUS3_3[15] H28 VCCTX_LVDS[1] AP43
C471
1 VCCSUS3_3[16] H26 0.059A VCCTX_LVDS[2] AP45
L28 UMA@
AF41 0.163AVCCSUS3_3[17] G28 AT46

LVDS
VCCME[5] 2 VCCTX_LVDS[3] +VCCTX_LVDS 0.01U_0402_16V7K 10U_0805_6.3V6M
VCCSUS3_3[18] G26 AK24 VCCIO[24] VCCTX_LVDS[4] AT45 2 1
AF42 F28 C485 1 1 1 1 0.1UH_MLF1608DR10KT_10%_1608
2 VCCME[6] VCCSUS3_3[19]
1.998A VCCSUS3_3[20] F26

1
0.01U_0402_16V7K C486 C505 C492
UPDATE 0210 V39 VCCME[7] VCCSUS3_3[21] E28 BJ24 VCCAPLLEXP0.042A UMA@ UMA@ UMA@ UMA@ R528
E26 AB34

Clock and Miscellaneous

VCCSUS3_3[22] VCC3_3[2] 2 2 2 2
V41 VCCME[8] VCCSUS3_3[23] C28 0_0402_5%
+3VS
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

VCCSUS3_3[24] C26 AN20 VCCIO[25] VCC3_3[3] AB35 DIS@

V42 B27 AN22 10U_0805_6.3V6M

HVCMOS

2
VCCME[9] VCCSUS3_3[25] VCCIO[26]
C516

C503

C515

C504

C475

1 1 1 1 1 VCCSUS3_3[26] A28 AN23 VCCIO[27] VCC3_3[4] AD35 1 2

Y39 A26 +3VALW AN24 C456 0.1U_0402_16V4Z
VCCME[10] VCCSUS3_3[27] VCCIO[28]
AN26 VCCIO[29]
Y41 VCCME[11] VCCSUS3_3[28] U23 AN28 VCCIO[30]
2 2 2 2 2

0.1U_0402_16V4Z
BJ26 VCCIO[31]

C455
Y42 VCCME[12] VCCIO[56] V23 +1.05VS 1 BJ28 VCCIO[32]
AT26 VCCIO[33]
PCH_V5REF_SUS +1.05VS
C452
>1mA V5REF_SUS F24 AT28 VCCIO[34]
AU26 VCCIO[35]
C +VCCRTCEXT 2 +PCH_VRM +1.8VS C
1 2 V9 DCPRTC AU28 VCCIO[36]

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1U_0402_16V4Z AV26 R509
VCCIO[37]

C464

C462
1 1 AV28 VCCIO[38] VCCVRM[2] AT24 1 2 0_0402_5%
0.035A >1mA K49 PCH_V5REF_RUN AW26
V5REF VCCIO[39]
+PCH_VRM AU24 VCCVRM[3] AW28 VCCIO[40]
PCI/GPIO/LPC

+VCCP

DMI
BA26 VCCIO[41] VCCDMI[1] AT16
+VCCADPLLA +3VS 2 2
0.072A VCC3_3[8] J38 BA28 VCCIO[42] 0.061A
lsolate AF32,AF34,AH34 BB51 VCCADPLLA[1] BB26 VCCIO[43] VCCDMI[2] AU16 1 2
BB53 L38 BB28 C491 1U_0402_6.3V6K
from AH35,AJ35 VCCADPLLA[2] VCC3_3[9] VCCIO[44]
1 BC26 VCCIO[45]
for Intel request 09.09.08 +VCCADPLLB

PCI E*
0.073A M36 C476 BC28
VCC3_3[10] VCCIO[46]

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M
BD51 0.357A 0.1U_0402_16V4Z BD26
VCCADPLLB[1] VCCIO[47]
BD53 VCCADPLLB[2] VCC3_3[11] N36 BD28 VCCIO[48]
+1.05VS 2

C473

C474

C514
1 1 1 BE26 AM16 R508 1 2 0_0402_5% +1.8VS
VCCIO[49] VCCPNAND[1]
AH23 VCCIO[21] VCC3_3[12] P36 BE28 VCCIO[50] VCCPNAND[2] AK16

C468

0.1U_0402_16V4Z
AJ35 VCCIO[22] BG26 VCCIO[51] VCCPNAND[3] AK20 1
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

AH35 U35 BG28 AK19 R501 1 2 0_0402_5% +3VS

VCCIO[23] VCC3_3[13] +3VS 2 2 2 VCCIO[52] VCCPNAND[4]
C472

C465

C484

1 1 1 BH27 VCCIO[53] 0.156A VCCPNAND[5] AK15

@
AF34 VCCIO[2] 3.208A VCCPNAND[6] AK13
2
VCC3_3[14] AD13 1 2 AN30 VCCIO[54] VCCPNAND[7] AM12
C457 0.1U_0402_16V4Z

NAND / SPI
AH34 VCCIO[3] AN31 VCCIO[55] VCCPNAND[8] AM13
2 2 2
VCCPNAND[9] AM15
AF32 VCCIO[4]
VCCSATAPLL[1] AK3 +3VS AN35 VCC3_3[1]
1 2 +VCCSST V12 0.032A AK1
0.1U_0402_16V4Z DCPSST VCCSATAPLL[2]
C453 +3VS
+PCH_VRM AT22 VCCVRM[1] 0.035A
1 2 +V1.1A_INT_VCCSUS Y22 BJ18 6mA AM8
DCPSUS VCCFDIPLL VCCME3_3[1]

0.1U_0402_16V4Z
0.1U_0402_16V4Z AH22 AM9
VCCIO[9] VCCME3_3[2]

C467
FDI
C463 +1.05VS AM23 0.085A AP11 1
VCCIO[1] VCCME3_3[3]
VCCME3_3[4] AP9
B +3VALW P18 AT20 B
VCCSUS3_3[29] VCCVRM[4] +PCH_VRM
0.2A@3.3V 2
1 2 U19
SATA

0.1U_0402_16V4Z VCCSUS3_3[30] +1.05VS IBEXPEAK-M_FCBGA1071

PCI/GPIO/LPC

VCCIO[10] AH19
C454 U20 VCCSUS3_3[31]
VCCIO[11] AD20
1U_0402_6.3V6K

U22 VCCSUS3_3[32]
C483

VCCIO[12] AF22 1
+3VS

VCCIO[13] AD19
1 2 0.4A@3.3V V15 AF20
0.1U_0402_16V4Z VCC3_3[5] VCCIO[14] 2 +1.05VS +VCCADPLLA
VCCIO[15] AF19
C139 V16 AH20
VCC3_3[6] VCCIO[16]
Y16 AB19 10uH inductor, 120mA
VCC3_3[7] VCCIO[17] L26
VCCIO[18] AB20 1 2
+VCCP AB22 10UH_LB2012T100MR_20% +5VALW +3VALW +5VS +3VS
VCCIO[19] +1.05VS
VCCIO[20] AD22 1 1
0.1A@1.1V AT18 R521
V_CPU_IO[1]

2
4.7U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

AA34 +PCH_VCC1_1_20 1 R488 2 0_0402_5% C507 + C494 0_0402_5%

CPU

VCCME[13]
C500

C501

C489

1 1 1 >1mA Y34 +PCH_VCC1_1_21 1 R487 2 0_0402_5% 220U_B2_2.5VM_R35 1U_0402_6.3V4Z @ R423 D6 R438 D9

VCCME[14] +PCH_VCC1_1_22 R489 0_0402_5% UMA@ @ 2 10_0402_1% 10_0402_1%
AU18 V_CPU_IO[2] VCCME[15] Y35 1 2
+PCH_VCC1_1_23 R490 0_0402_5% 2 CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2
VCCME[16] AA35 1 2

1
2 2 2 +VCCADPLLB
RTC

A12 2mA 6mA L30 R410 1 2 0_0402_5% +3VALW PCH_V5REF_SUS PCH_V5REF_RUN

+RTCVCC VCCRTC VCCSUSHDA
1U_0402_6.3V6K
HDA

10uH inductor, 120mA 20 mils 20 mils

C435

1 R411 1 2 0_0402_5% +1.5V L25 1 2 1 1

2mA@3.3V IBEXPEAK-M_FCBGA1071 @ 10UH_LB2012T100MR_20%
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 C447 C448
C442

C440

1 1 1U_0402_6.3V6K 1U_0402_6.3V6K
2 C506 + C493 2 2
A 220U_B2_2.5VM_R35 1U_0402_6.3V4Z A
UMA@ @ 2
2 2 2
C447 changed to 1u 09/04/2009
check list Rev2.0 update.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/08/12 Deciphered Date 2009/08/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(5/6)-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 17 of 51
5 4 3 2 1
 5 4 3 2 1

U7I
U7H
AY7 VSS[159] VSS[259] H49
B11 VSS[160] VSS[260] H5 AB16 VSS[0]
B15 VSS[161] VSS[261] J24
B19 VSS[162] VSS[262] K11 AA19 VSS[1] VSS[80] AK30
D B23 K43 AA20 AK31 D
VSS[163] VSS[263] VSS[2] VSS[81]
B31 VSS[164] VSS[264] K47 AA22 VSS[3] VSS[82] AK32
B35 VSS[165] VSS[265] K7 AM19 VSS[4] VSS[83] AK34
B39 VSS[166] VSS[266] L14 AA24 VSS[5] VSS[84] AK35
B43 VSS[167] VSS[267] L18 AA26 VSS[6] VSS[85] AK38
B47 VSS[168] VSS[268] L2 AA28 VSS[7] VSS[86] AK43
B7 VSS[169] VSS[269] L22 AA30 VSS[8] VSS[87] AK46
BG12 VSS[170] VSS[270] L32 AA31 VSS[9] VSS[88] AK49
BB12 VSS[171] VSS[271] L36 AA32 VSS[10] VSS[89] AK5
BB16 VSS[172] VSS[272] L40 AB11 VSS[11] VSS[90] AK8
BB20 VSS[173] VSS[273] L52 AB15 VSS[12] VSS[91] AL2
BB24 VSS[174] VSS[274] M12 AB23 VSS[13] VSS[92] AL52
BB30 VSS[175] VSS[275] M16 AB30 VSS[14] VSS[93] AM11
BB34 VSS[176] VSS[276] M20 AB31 VSS[15] VSS[94] BB44
BB38 VSS[177] VSS[277] N38 AB32 VSS[16] VSS[95] AD24
BB42 VSS[178] VSS[278] M34 AB39 VSS[17] VSS[96] AM20
BB49 VSS[179] VSS[279] M38 AB43 VSS[18] VSS[97] AM22
BB5 VSS[180] VSS[280] M42 AB47 VSS[19] VSS[98] AM24
BC10 VSS[181] VSS[281] M46 AB5 VSS[20] VSS[99] AM26
BC14 VSS[182] VSS[282] M49 AB8 VSS[21] VSS[100] AM28
BC18 VSS[183] VSS[283] M5 AC2 VSS[22] VSS[101] BA42
BC2 VSS[184] VSS[284] M8 AC52 VSS[23] VSS[102] AM30
BC22 VSS[185] VSS[285] N24 AD11 VSS[24] VSS[103] AM31
BC32 VSS[186] VSS[286] P11 AD12 VSS[25] VSS[104] AM32
BC36 VSS[187] VSS[287] AD15 AD16 VSS[26] VSS[105] AM34
BC40 VSS[188] VSS[288] P22 AD23 VSS[27] VSS[106] AM35
BC44 VSS[189] VSS[289] P30 AD30 VSS[28] VSS[107] AM38
BC52 VSS[190] VSS[290] P32 AD31 VSS[29] VSS[108] AM39
BH9 VSS[191] VSS[291] P34 AD32 VSS[30] VSS[109] AM42
BD48 VSS[192] VSS[292] P42 AD34 VSS[31] VSS[110] AU20
BD49 VSS[193] VSS[293] P45 AU22 VSS[32] VSS[111] AM46
BD5 VSS[194] VSS[294] P47 AD42 VSS[33] VSS[112] AV22
C BE12 R2 AD46 AM49 C
VSS[195] VSS[295] VSS[34] VSS[113]
BE16 VSS[196] VSS[296] R52 AD49 VSS[35] VSS[114] AM7
BE20 VSS[197] VSS[297] T12 AD7 VSS[36] VSS[115] AA50
BE24 VSS[198] VSS[298] T41 AE2 VSS[37] VSS[116] BB10
BE30 VSS[199] VSS[299] T46 AE4 VSS[38] VSS[117] AN32
BE34 VSS[200] VSS[300] T49 AF12 VSS[39] VSS[118] AN50
BE38 VSS[201] VSS[301] T5 Y13 VSS[40] VSS[119] AN52
BE42 VSS[202] VSS[302] T8 AH49 VSS[41] VSS[120] AP12
BE46 VSS[203] VSS[303] U30 AU4 VSS[42] VSS[121] AP42
BE48 VSS[204] VSS[304] U31 AF35 VSS[43] VSS[122] AP46
BE50 VSS[205] VSS[305] U32 AP13 VSS[44] VSS[123] AP49
BE6 VSS[206] VSS[306] U34 AN34 VSS[45] VSS[124] AP5
BE8 VSS[207] VSS[307] P38 AF45 VSS[46] VSS[125] AP8
BF3 VSS[208] VSS[308] V11 AF46 VSS[47] VSS[126] AR2
BF49 VSS[209] VSS[309] P16 AF49 VSS[48] VSS[127] AR52
BF51 VSS[210] VSS[310] V19 AF5 VSS[49] VSS[128] AT11
BG18 VSS[211] VSS[311] V20 AF8 VSS[50] VSS[129] BA12
BG24 VSS[212] VSS[312] V22 AG2 VSS[51] VSS[130] AH48
BG4 VSS[213] VSS[313] V30 AG52 VSS[52] VSS[131] AT32
BG50 VSS[214] VSS[314] V31 AH11 VSS[53] VSS[132] AT36
BH11 VSS[215] VSS[315] V32 AH15 VSS[54] VSS[133] AT41
BH15 VSS[216] VSS[316] V34 AH16 VSS[55] VSS[134] AT47
BH19 VSS[217] VSS[317] V35 AH24 VSS[56] VSS[135] AT7
BH23 VSS[218] VSS[318] V38 AH32 VSS[57] VSS[136] AV12
BH31 VSS[219] VSS[319] V43 AV18 VSS[58] VSS[137] AV16
BH35 VSS[220] VSS[320] V45 AH43 VSS[59] VSS[138] AV20
BH39 VSS[221] VSS[321] V46 AH47 VSS[60] VSS[139] AV24
BH43 VSS[222] VSS[322] V47 AH7 VSS[61] VSS[140] AV30
BH47 VSS[223] VSS[323] V49 AJ19 VSS[62] VSS[141] AV34
BH7 VSS[224] VSS[324] V5 AJ2 VSS[63] VSS[142] AV38
C12 VSS[225] VSS[325] V7 AJ20 VSS[64] VSS[143] AV42
C50 VSS[226] VSS[326] V8 AJ22 VSS[65] VSS[144] AV46
B D51 W2 AJ23 AV49 B
VSS[227] VSS[327] VSS[66] VSS[145]
E12 VSS[228] VSS[328] W52 AJ26 VSS[67] VSS[146] AV5
E16 VSS[229] VSS[329] Y11 AJ28 VSS[68] VSS[147] AV8
E20 VSS[230] VSS[330] Y12 AJ32 VSS[69] VSS[148] AW14
E24 VSS[231] VSS[331] Y15 AJ34 VSS[70] VSS[149] AW18
E30 VSS[232] VSS[332] Y19 AT5 VSS[71] VSS[150] AW2
E34 VSS[233] VSS[333] Y23 AJ4 VSS[72] VSS[151] BF9
E38 VSS[234] VSS[334] Y28 AK12 VSS[73] VSS[152] AW32
E42 VSS[235] VSS[335] Y30 AM41 VSS[74] VSS[153] AW36
E46 VSS[236] VSS[336] Y31 AN19 VSS[75] VSS[154] AW40
E48 VSS[237] VSS[337] Y32 AK26 VSS[76] VSS[155] AW52
E6 VSS[238] VSS[338] Y38 AK22 VSS[77] VSS[156] AY11
E8 VSS[239] VSS[339] Y43 AK23 VSS[78] VSS[157] AY43
F49 VSS[240] VSS[340] Y46 AK28 VSS[79] VSS[158] AY47
F5 VSS[241] VSS[341] P49
G10 Y5 IBEXPEAK-M_FCBGA1071
VSS[242] VSS[342]
G14 VSS[243] VSS[343] Y6
G18 VSS[244] VSS[344] Y8
G2 VSS[245] VSS[345] P24
G22 VSS[246] VSS[346] T43
G32 VSS[247] VSS[347] AD51
G36 VSS[248] VSS[348] AT8
G40 VSS[249] VSS[349] AD47
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
AF39 VSS[252] VSS[352] AM6
H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
H30 VSS[255] VSS[355] AK45
H34 VSS[256] VSS[356] AK39
H38 VSS[257] VSS[366] AV14
H42 VSS[258]
A A

IBEXPEAK-M_FCBGA1071

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/31 Deciphered Date 2009/10/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(6/6)-GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 18 of 51
5 4 3 2 1
 5 4 3 2 1

U22A
<6> PCIE_CTX_GRX_N[0..15]
PCIE_CTX_GRX_N[0..15] Part 1 of 5 GPIO5 GPIO6
PCIE_CTX_GRX_P0 AE12 N1
PCIE_CTX_GRX_N0 PEX_RX0 GPIO0
<6> PCIE_CTX_GRX_P[0..15]
PCIE_CTX_GRX_P[0..15] AF12 PEX_RX0_N GPIO1 G1 HDMI_DETECT_VGA <24> GPU_VID0 GPU_VID1 VGA_CORE P-State
PCIE_CTX_GRX_P1 AG12 C1 NV_INVTPWM Device ID
PEX_RX1 GPIO2 PAD T9
PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_N1 AG13 M2 VGA_ENVDD_R 0.8V Deep P12
<6> PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_P2 AF13
PEX_RX1_N GPIO3
M3 VGA_ENBKL_R
VGA_ENVDD_R <27> 0 0
PEX_RX2 GPIO4 VGA_ENBKL_R <27>
PCIE_CRX_GTX_P[0..15] PCIE_CTX_GRX_N2 AE13 K3 1 2 GPU_VID0 N11M-GE1/LP1 0.85V P8
<6> PCIE_CRX_GTX_P[0..15]
PCIE_CTX_GRX_P3 PEX_RX2_N GPIO5 GPU_VID1
GPU_VID0 <45> 0 1
AE15 PEX_RX3 GPIO6 K2 R511 1 DIS@ 2 0_0402_5%
GPU_VID1 <45> (40nm) 0x0A7D
PCIE_CTX_GRX_N3 AF15 J2 R512 DIS@ 0_0402_5% 1.03 P0
PCIE_CTX_GRX_P4 AG15
PEX_RX3_N GPIO7
C2
1 1

GPIO
PCIE_CTX_GRX_N4 PEX_RX4 GPIO8
AG16 M1
PCIE_CTX_GRX_P5 PEX_RX4_N GPIO9
AF16 PEX_RX5 GPIO10 D2
PCIE_CTX_GRX_N5 AE16 D1 VGA_GPIO11
PCIE_CTX_GRX_P6 PEX_RX5_N GPIO11
AE18 PEX_RX6 GPIO12 J3
D PCIE_CTX_GRX_N6 D
AF18 PEX_RX6_N GPIO13 J1
PCIE_CTX_GRX_P7 AG18 K1 VGA_GPIO14
PCIE_CTX_GRX_N7 PEX_RX7 GPIO14
AG19 PEX_RX7_N GPIO15 F3
PCIE_CTX_GRX_P8 AF19 G3
PCIE_CTX_GRX_N8 PEX_RX8 GPIO16
AE19 G2 PAD T4
PCIE_CTX_GRX_P9 PEX_RX8_N GPIO17
AE21 PEX_RX9 GPIO18 F1
PCIE_CTX_GRX_N9 AF21 F2
PCIE_CTX_GRX_P10 PEX_RX9_N GPIO19
AG21 PEX_RX10
PCIE_CTX_GRX_N10 AG22 AD2
PEX_RX10_N DACA_HSYNC VGA_HSYNC <26>
PCIE_CTX_GRX_P11 AF22 AD1 VGA_VSYNC <26>
PEX_RX11 DACA_VSYNC

DACA
PCIE_CTX_GRX_N11 AE22
PCIE_CTX_GRX_P12 PEX_RX11_N VGA_CRT_R
AE24 AE2 VGA_CRT_R <26>
PCIE_CTX_GRX_N12 PEX_RX12 DACA_RED VGA_CRT_B
AF24 AD3
PCIE_CTX_GRX_P13 AG24
PEX_RX12_N DACA_BLUE
AE3 VGA_CRT_G
VGA_CRT_B <26>
VGA_CRT_G <26>
CRT OUT
PCIE_CTX_GRX_N13 PEX_RX13 DACA_GREEN VGA_GPIO11
AF25
PCIE_CTX_GRX_P14 PEX_RX13_N DACA_VREF DIS@ 2 VGA_GPIO14
AG25 AF1 1
PEX_RX14 DACA_VREF

1
PCIE_CTX_GRX_N14 DACA_RSET

PCI EXPRESS
AG26 AE1 C81 0.1U_0402_16V4Z
PEX_RX14_N DACA_RSET

1
DIS@ PCIE_CTX_GRX_P15 AF27
PCIE_CTX_GRX_N15 PEX_RX15 R48 DIS@ 124_0402_1% R513 R505
AE27 PEX_RX15_N DACB_HSYNC U6
U4 10K_0402_5% 10K_0402_5%
PCIE_CRX_GTX_P0 C120 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P0 DACB_VSYNC @
1 2 AD10

DACB
@

2
PCIE_CRX_GTX_N0 C119 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N0 PEX_TX0
1 2 AD11 T5

2
PCIE_CRX_GTX_P1 C118 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P1 PEX_TX0_N DACB_RED
1 2 AD12 PEX_TX1 DACB_BLUE R4
PCIE_CRX_GTX_N1 C117 DIS@ 1 2 0.1U_0402_10V6K PCIE_CRX_C_GTX_N1 AC12 T4
PCIE_CRX_GTX_P2 C80 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P2 PEX_TX1_N DACB_GREEN
1 2 AB11
PCIE_CRX_GTX_N2 C79 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N2 PEX_TX2
1 2 AB12 PEX_TX2_N DACB_VREF R6
PCIE_CRX_GTX_P3 C78 DIS@ 1 2 0.1U_0402_10V6K PCIE_CRX_C_GTX_P3 AD13 V6 VGA_CRT_R R537 1 DIS@ 2 150_0402_1%
PCIE_CRX_GTX_N3 C77 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N3 PEX_TX3 DACB_RSET VGA_CRT_G R538
1 2 AD14 1 DIS@ 2 150_0402_1%
PCIE_CRX_GTX_P4 C116 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P4 PEX_TX3_N VGA_CRT_B R530
1 2 AD15 PEX_TX4 1 DIS@ 2 150_0402_1%
PCIE_CRX_GTX_N4 C115 DIS@ 1 2 0.1U_0402_10V6K PCIE_CRX_C_GTX_N4 AC15
PCIE_CRX_GTX_P5 C114 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P5 PEX_TX4_N JTAG_TCK
1 2 AB14 AF3 PAD T14
PCIE_CRX_GTX_N5 C113 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N5 PEX_TX5 JTAG_TCK JTAG_TDI
1 2 AB15 AG4 PAD T13
C PCIE_CRX_GTX_P6 C112 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P6 PEX_TX5_N JTAG_TDI JTAG_TDO C
1 2 AC16 AE4

TEST
PEX_TX6 JTAG_TDO PAD T12
PCIE_CRX_GTX_N6 C111 DIS@ 1 2 0.1U_0402_10V6K PCIE_CRX_C_GTX_N6 AD16 AF4 JTAG_TMS Pull Hi at CRT CONN side.
PEX_TX6_N JTAG_TMS PAD T11 +3VS
PCIE_CRX_GTX_P7 C109 DIS@ 1 2 0.1U_0402_10V6K PCIE_CRX_C_GTX_P7 AD17 AG3 JTAG_TRST_N 1 2
PCIE_CRX_GTX_N7 C110 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N7 PEX_TX7 JTAG_TRST_N R539 DIS@ 10K_0402_5%
1 2 AD18 PEX_TX7_N
PCIE_CRX_GTX_P8 C108 DIS@ 1 2 0.1U_0402_10V6K PCIE_CRX_C_GTX_P8 AC18 AD25 TESTMODE 1 2
PCIE_CRX_GTX_N8 C107 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N8 PEX_TX8 TESTMODE R24 DIS@ 10K_0402_5% +3VS VGA_DDCCLK_C R443 2 @
1 2 AB18 1 4.7K_0402_5%
PCIE_CRX_GTX_P9 C105 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P9 PEX_TX8_N
1 2 AB19 PEX_TX9 1 2 +3VS
PCIE_CRX_GTX_N9 C106 DIS@ 1 2 0.1U_0402_10V6K PCIE_CRX_C_GTX_N9 AB20 10K_0402_5% @ R25 VGA_DDCDATA_C R444 2 @ 1 4.7K_0402_5%
PCIE_CRX_GTX_P10 C104 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P10 PEX_TX9_N VGA_DDCCLK_C +3VS
1 2 AD19 PEX_TX10 I2CA_SCL R1
PCIE_CRX_GTX_N10 C103 DIS@ 1 2 0.1U_0402_10V6K PCIE_CRX_C_GTX_N10 AD20 T3 VGA_DDCDATA_C
PCIE_CRX_GTX_P11 C102 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P11 PEX_TX10_N I2CA_SDA
1 2 AD21 PEX_TX11
PCIE_CRX_GTX_N11 C101 DIS@ 1 2 0.1U_0402_10V6K PCIE_CRX_C_GTX_N11 AC21 R2 I2CB_SCL R517 1 DIS@ 2 2.2K_0402_5%
PCIE_CRX_GTX_P12 C100 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P12 PEX_TX11_N I2CB_SCL I2CB_SDA R516 1 2.2K_0402_5% R499 R478 +3VS
1 2 AB21 PEX_TX12 I2CB_SDA R3 2
PCIE_CRX_GTX_N12 C99 DIS@ 1 2 0.1U_0402_10V6K PCIE_CRX_C_GTX_N12 AB22 DIS@ 2.2K_0402_5% 2.2K_0402_5%
PCIE_CRX_GTX_P13 C98 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P13 PEX_TX12_N VGA_LVDS_SCL_C DIS@ DIS@
1 2 AC22 A2

I2C
PCIE_CRX_GTX_N13 C97 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N13 PEX_TX13 I2CC_SCL VGA_LVDS_SDA_C VGA_LVDS_SCL_C R64
1 2 AD22 B1 2 DIS@ 1 2.2K_0402_5%
PCIE_CRX_GTX_P14 C96 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P14 PEX_TX13_N I2CC_SDA
1 2 AD23
PCIE_CRX_GTX_N14 C95 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N14 PEX_TX14 HDCP_SMB_CK1 VGA_LVDS_SDA_C R63
1 2 AD24 A3 2 DIS@ 1 2.2K_0402_5%
PCIE_CRX_GTX_P15 C94 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_P15 PEX_TX14_N I2CH_SCL HDCP_SMB_DAI
1 2 AE25 A4
PCIE_CRX_GTX_N15 C93 DIS@ 0.1U_0402_10V6K PCIE_CRX_C_GTX_N15 PEX_TX15 I2CH_SDA
1 2 AE26 PEX_TX15_N
I2CS_SCL
T1 SMB_EC_CK2_R
SMB_EC_CK2_R <14,31> I2CS is VDD33 power plane
CLK_PCIE_VGA AB10 T2 SMB_EC_DA2_R
<14> CLK_PCIE_VGA
CLK_PCIE_VGA# AC10
PEX_REFCLK I2CS_SDA SMB_EC_DA2_R <14,31> same as EC +3.3VS.
<14> CLK_PCIE_VGA# PEX_REFCLK_N
I2CS is internal thermal sensor.
AF10
PEX_TSTCLK_OUT
1 2 AE10
PEX_TSTCLK_OUT_N XTAL_SSIN
D11 Removed external HDCP.
R540 200_0402_5% @
1 2 AG10 E9 07/17/2009
R541 2.49K_0402_1% DIS@ PEX_TERMP XTAL_OUTBUFF

1
AD9 E10 XTALOUT
CLK

<5,16,28,29> BUF_PLT_RST# PEX_RST_N XTAL_OUT

1
R42
1

AE9 D10 XTALIN 10K_0402_5% R34

B R46 PEX_CLKREQ_N XTAL_IN DIS@ 10K_0402_5% B

10K_0402_5% DIS@

2
@ N11M-GE1-S-A3 _BGA533

2
DIS@ DIS@
2

+3VS 1 2 10K_0402_5%
R542

PEG_CLKREQ# 1 2
<14> PEG_CLKREQ#
R543 @ 0_0402_5%

Y2
4 3
GND OUT
1 2
IN GND
27MHZ_16PF_X7S027000BG1H-U
1 DIS@ 1
L17 DIS@ MBK1608121YZF_0603
C69 C56 VGA_DDCCLK_C 1 2 VGA_DDCCLK <26>
20P_0402_50V8 20P_0402_50V8 VGA_DDCDATA_C 1 2
2 2 VGA_DDCDATA <26>
DIS@ DIS@ L18 DIS@ MBK1608121YZF_0603
DIS@ MBK1608121YZF_0603
VGA_LVDS_SCL_C L8 1 2
VGA_LVDS_SDA_C VGA_LVDS_SCL <27>
1 2 VGA_LVDS_SDA <27>
L7 DIS@ MBK1608121YZF_0603

1 1 1 1
C450
C451 C86 C85
A DIS@ DIS@ DIS@ DIS@ A
12P_0402_50V8J 12P_0402_50V8J
2 2 2 2
12P_0402_50V8J 12P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N11M-GE1 PCIE,GPIO,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B LA-5751 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 30, 2009 Sheet 19 of 51
5 4 3 2 1
 5 4 3 2 1

FBAA[0..13] RF team request.

<23> FBAA[0..13]
FBBA[2..5] VGA_LVDS_ACLK
<23> FBBA[2..5]
FBADQM[0..7] VGA_LVDS_ACLK#
<23> FBADQM[0..7]
FBADQS[0..7] 2 2
<23> FBADQS[0..7]
FBADQS#[0..7] C649 C650
<23> FBADQS#[0..7]
12P_0402_50V8J 12P_0402_50V8J
FBA_D[0..63] @ 1 1
<23> FBAD[0..63] @

U22B
D Part 2 of 5 D
FBA_D0 D22 F26 FBAA4
FBA_D1 FBA_D0 FBA_CMD0 FBARAS# U22C
E24 FBA_D1 FBA_CMD1 J24 FBARAS# <23>
FBA_D2 E22 F25 FBAA5 Part 3 of 5
FBA_D3 FBA_D2 FBA_CMD2 FBA_BA1 VGA_LVDS_ACLK AC4
D24 M23 FBA_BA1 <23> <27> VGA_LVDS_ACLK C15
FBA_D4 FBA_D3 FBA_CMD3 FBBA2 VGA_LVDS_ACLK# AD4 IFPA_TXC NC
D26 N27 D15

NC
FBA_D4 FBA_CMD4 <27> VGA_LVDS_ACLK# IFPA_TXC_N NC
FBA_D5 D27 M27 FBBA4 VGA_LVDS_A0 V5 J5
FBA_D5 FBA_CMD5 <27> VGA_LVDS_A0 IFPA_TXD0 NC
FBA_D6 C27 K26 FBBA3 VGA_LVDS_A0# V4
FBA_D6 FBA_CMD6 <27> VGA_LVDS_A0# IFPA_TXD0_N
FBA_D7 B27 J25 FBBA_CKE VGA_LVDS_A1 AA5
FBA_D7 FBA_CMD7 FBBA_CKE <23> <27> VGA_LVDS_A1 IFPA_TXD1

1
FBA_D8 A21 J27 FBBACS0# <27> VGA_LVDS_A1# VGA_LVDS_A1# AA4
FBA_D9 FBA_D8 FBA_CMD8 FBAA11 FBBACS0# <23> VGA_LVDS_A2 IFPA_TXD1_N
B21 G23 R22 <27> VGA_LVDS_A2 W4
FBA_D10 FBA_D9 FBA_CMD9 FBACAS# 10K_0402_5% VGA_LVDS_A2# IFPA_TXD2
C21 G26 FBACAS# <23> <27> VGA_LVDS_A2# Y4 T6
FBA_D11 FBA_D10 FBA_CMD10 FBAWE# DIS@ IFPA_TXD2_N RFU_1
C19 J23 AB4 W6

RFU
FBA_D11 FBA_CMD11 FBAWE# <23> IFPA_TXD3 RFU_2
FBA_D12 FBA_BA0
C18 M25 LVDS AB5 Y6

2
FBA_D13 FBA_D12 FBA_CMD12 FBBA5 FBA_BA0 <23> IFPA_TXD3_N RFU_3
D18 K27 AA6
FBA_D14 FBA_D13 FBA_CMD13 FBAA12 RFU_4
B18 G25 FBAA12 <23> N3
FBA_D15 FBA_D14 FBA_CMD14 FBA_RST RFU_5
C16 FBA_D15 FBA_CMD15 L24 FBA_RST <23> AB3 IFPB_TXC

1
FBA_D16 E21 K23 FBAA7 AB2
MEMORY INTERFACE

FBA_D17 FBA_D16 FBA_CMD16 FBAA10 R16 IFPB_TXC_N

F21 FBA_D17 FBA_CMD17 K24 W1 IFPB_TXD4
FBA_D18 D20 G22 FBAA_CKE 10K_0402_5% V1 C7 STRAP0
FBA_D18 FBA_CMD18 FBAA_CKE <23> IFPB_TXD4_N STRAP0 STRAP0 <22>
FBA_D19 FBAA0 DIS@

STRAP
F20 K25 W3

LVDS / TMDS
FBA_D19 FBA_CMD19 IFPB_TXD5

1
FBA_D20 D17 H22 FBAA9 W2 B9 STRAP1

2
FBA_D21 FBA_D20 FBA_CMD20 FBAA6 IFPB_TXD5_N STRAP1 STRAP1 <22>
F18 M26 R23 AA2
FBA_D22 FBA_D21 FBA_CMD21 FBAA2 10K_0402_5% IFPB_TXD6 STRAP2
D16 FBA_D22 FBA_CMD22 H24 AA3 IFPB_TXD6_N STRAP2 A9 STRAP2 <22>
FBA_D23 E16 F27 FBAA8 DIS@ AB1
FBA_D24 FBA_D23 FBA_CMD23 FBAA3 IFPB_TXD7
A22 J26 AA1

2
FBA_D25 FBA_D24 FBA_CMD24 FBAA1 IFPB_TXD7_N
C24 G24
FBA_D26 FBA_D25 FBA_CMD25 FBAA13
D21 G27
FBA_D27 FBA_D26 FBA_CMD26 FBA_BA2 IFPC_AUX
B22 FBA_D27 FBA_CMD27 M24 FBA_BA2 <23> G4 IFPC_AUX_I2CW_SCL BUFRST_N N5 PAD T1
FBA_D28 C22 K22 FBBAODT0 IFPC_AUX_N G5
FBA_D29 FBA_D28 FBA_CMD28 FBAACS0# FBBAODT0 <23> IFPC_AUX_I2CW_SDA_N
A25 J22 <24> VGA_HDMI_TX2+ P4 +3VS
FBA_D30 FBA_D29 FBA_CMD29 FBAAODT0 FBAACS0# <23> IFPC_L0
B25 L22 <24> VGA_HDMI_TX2- N4

GENERAL
FBA_D30 FBA_CMD30 FBAAODT0 <23> IFPC_L0_N

1
C FBA_D31 C
A26 FBA_D31 <24> VGA_HDMI_TX1+ M5 IFPC_L1 THERMDN D8 PAD T2

1
FBA_D32 U24 C26 FBADQM0 R18 <24> VGA_HDMI_TX1- M4
FBA_D32 FBA_DQM0 IFPC_L1_N

1
FBA_D33 FBADQM1 10K_0402_5% R445
FBA_D34
V24
V23
FBA_D33 FBA_DQM1
B19
D19 FBADQM2 R15 DIS@
HDMI <24> VGA_HDMI_TX0+ L4
K4
IFPC_L2 THERMDP
D9 PAD T3
10K_0402_5%
FBA_D34 FBA_DQM2 <24> VGA_HDMI_TX0- IFPC_L2_N
FBA_D35 R24 D23 FBADQM3 10K_0402_5% H4 DIS@
<24> VGA_HDMI_CLK+

2
FBA_D36 FBA_D35 FBA_DQM3 FBADQM4 DIS@ IFPC_L3 +3VS
T23 T24 <24> VGA_HDMI_CLK- J4

2
FBA_D37 FBA_D36 FBA_DQM4 FBADQM5 IFPC_L3_N
R23 AA23 N2
2

FBA_D37 FBA_DQM5 CEC

1
FBA_D38 P24 AB27 FBADQM6
FBA_D39 FBA_D38 FBA_DQM6 FBADQM7 SPDIF_IN
P22 FBA_D39 FBA_DQM7 T26 D3 IFPD_AUX_I2CX_SCL SPDIF F9 1 DIS@ 2 R468
FBA_D40 AC24 D4 R32 36K_0402_5% 10K_0402_5%
FBA_D41 FBA_D40 FBADQS#0 IFPD_AUX_I2CX_SDA_N DIS@
AB23 FBA_D41 FBA_DQS_RN0 D25 F5 IFPD_L0
FBA_D42 AB24 A18 FBADQS#1 F4

2
FBA_D43 FBA_D42 FBA_DQS_RN1 FBADQS#2 IFPD_L0_N
W24 FBA_D43 FBA_DQS_RN2 E18 E4 IFPD_L1 ROM_CS_N B10
FBA_D44 AA22 B24 FBADQS#3 D5

SERIAL
FBA_D45 FBA_D44 FBA_DQS_RN3 FBADQS#4 IFPD_L1_N ROM_SCLK
W23 R22 C3 C9 ROM_SCLK <22>
FBA_D46 FBA_D45 FBA_DQS_RN4 FBADQS#5 IFPD_L2 ROM_SCLK
W22 Y24 C4
FBA_D47 FBA_D46 FBA_DQS_RN5 FBADQS#6 IFPD_L2_N ROM_SI
V22 AA27 B3 A10 ROM_SI <22>
FBA_D48 FBA_D47 FBA_DQS_RN6 FBADQS#7 IFPD_L3 ROM_SI
AA25 R27 B4
FBA_D49 FBA_D48 FBA_DQS_RN7 IFPD_L3_N ROM_SO
W27 C10 ROM_SO <22>
FBA_D50 FBA_D49 FBADQS0 ROM_SO
W26 FBA_D50 FBA_DQS_WP0 C25
FBA_D51 W25 A19 FBADQS1 +1.5VS F7
FBA_D52 FBA_D51 FBA_DQS_WP1 FBADQS2 IFPE_AUX_I2CY_SCL
AB25 E19 G6
FBA_D53 FBA_D52 FBA_DQS_WP2 FBADQS3 IFPE_AUX_I2CY_SDA_N
AB26 A24 D6
FBA_D53 FBA_DQS_WP3 IFPE_L0

1
FBA_D54 AD26 T22 FBADQS4 C6 AB6 1 2
FBA_D55 FBA_D54 FBA_DQS_WP4 FBADQS5 R30 IFPE_L0_N IFPAB_RSET R44 @ 1K_0402_1%
AD27 AA24 A6
FBA_D56 FBA_D55 FBA_DQS_WP5 FBADQS6 1.3K_0402_1% IFPE_L1
V25 AA26 A7 R5 1 2
FBA_D57 FBA_D56 FBA_DQS_WP6 FBADQS7 @ IFPE_L1_N IFPC_RSET R39 DIS@ 1K_0402_1%
R25 FBA_D57 FBA_DQS_WP7 T27 B6 IFPE_L2
FBA_D58 V26
1.27V~0.9V B7 M6 1 2

2
FBA_D59 FBA_D58 FB_VREF1 10mil IFPE_L2_N IFPD_RSET R40 @ 1K_0402_1%
V27 A16 E6
FBA_D60 FBA_D59 FB_VREF IFPE_L3
R26 E7 F8 1 2
FBA_D61 FBA_D60 IFPE_L3_N IFPE_RSET R477 @ 1K_0402_1%
T25 F24 FBACLK0 <23>
FBA_D61 FBA_CLK0

1
FBA_D62 N25 F23 1
B FBA_D62 FBA_CLK0_N FBACLK0# <23> B
FBA_D63 N26 C43 R29 N11M-GE1-S-A3 _BGA533
FBA_D63 0.01U_0402_16V7K 1.3K_0402_1% DIS@
FBA_CLK1 N24 FBACLK1 <23>
N23 @ @
FBA_CLK1_N FBACLK1# <23> 2 +3VS
+3VS
2

M22 1 R26 2 +1.5VS

FBA_DEBUG 10K_0402_5% DIS@

N11M-GE1-S-A3 _BGA533
DIS@

2
R526
4.7K_0402_5%
DIS@

2
1
Q38A
IFPC_AUX 1 6
2N7002DW-T/R7_SOT363-6 VGA_HDMI_SCL <24>
DIS@

2
R531
4.7K_0402_5%

5
DIS@ DIS@
Q38B

1
IFPC_AUX_N 4 3 VGA_HDMI_SDA <24>
2N7002DW-T/R7_SOT363-6
5V PULL UP IN CONNECTER SIDE
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N11M-GE1 LVDS,Memory Bus
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B LA-5751 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 30, 2009 Sheet 20 of 51
5 4 3 2 1
 5 4 3 2 1

PLACE UNDER GPU CLOSE TO GPU

+1.5VS
NEAR
+VGA_CORE
BGA 0.01U_0402_16V7K 0.047U_0402_25V7K 0.047U_0402_25V7K
4.7U 6.3V K X5R 0603

NEAR BALL U22D

1 1 1 1 1 1
1
Part 4 of 5 C53 C28 C27 C42 C32 C31 C24
4.7U 6.3V K X5R 0603 0.047U_0402_25V7K 0.01U_0402_16V7K J9 A13 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

1 1 1 1
J10
J12
VDD
VDD
FBVDDQ
FBVDDQ B13
C13
2 2 2 2 2 2
2
N11M-GE1:2.55A
VDD FBVDDQ 0.01U_0402_16V7K 0.01U_0402_16V7K 0.047U_0402_25V7K
1 J13 VDD FBVDDQ D13
C26 C50 C38 C39 C40 L9 D14
DIS@ DIS@ DIS@ DIS@ DIS@ VDD FBVDDQ
M9 VDD FBVDDQ E13
2 2 2 2 M11 F13
D 2 VDD FBVDDQ D
M17 VDD FBVDDQ F14
0.1U_0402_10V7K 0.01U_0402_16V7K N9 F15
VDD FBVDDQ +1.05VS
N11
N12
VDD
VDD
FBVDDQ
FBVDDQ
F16
F17
NEAR BALL NEAR BGA 2A
0.047U_0402_25V7K 0.01U_0402_16V7K N13 F19
VDD FBVDDQ 0.1U_0402_10V7K 1U_0402_6.3V6K 4.7U 6.3V K X5R 0603 22U_0805_6.3V6M
N14 VDD FBVDDQ F22
1 1 1 N15 VDD FBVDDQ H23
N16 VDD FBVDDQ H26 1 1 1 1 1 1 1
C41 C37 C29 N17 J15
N11M-GE1:16.7A 2
DIS@
2
DIS@
2
DIS@ N19
P11
VDD
VDD
FBVDDQ
FBVDDQ J16
J18
C46
DIS@
C58
DIS@
C83
DIS@
C35
DIS@
C537
DIS@
C538
DIS@
C552
DIS@
VDD FBVDDQ 2 2 2 2 2 2 2
P12 VDD FBVDDQ J19
0.01U_0402_16V7K P13 L19
VDD FBVDDQ 0.1U_0402_10V7K 1U_0402_6.3V6K 10U_0805_6.3V6M
P14 VDD FBVDDQ L23
0.047U_0402_25V7K 0.01U_0402_16V7K P15 L26
VDD FBVDDQ +1.05VS
P16 VDD FBVDDQ M19
1 1 1 P17
R9
VDD
VDD
FBVDDQ
FBVDDQ
N22
U22 NEAR BALL NEAR BGA
C36 C52 C51 R11 Y22 0.1U_0402_10V7K 1U_0402_6.3V6K 4.7U 6.3V K X5R 0603

POWER
DIS@ DIS@ DIS@ VDD FBVDDQ
R12 VDD
2 2 2 R13 AG6
VDD PEX_IOVDDQ 1 1 1 1 1 1 1
R14 VDD PEX_IOVDDQ AF6
0.01U_0402_16V7K R15 AE6 C47 C60 C59 C49 C48 C551 C553
VDD PEX_IOVDDQ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
R16 VDD PEX_IOVDDQ AD6
R17 AC13 2 2 2 2 2 2 2
VDD PEX_IOVDDQ
T9 VDD PEX_IOVDDQ AC7
T11 AB17 0.1U_0402_10V7K 0.1U_0402_10V7K 1U_0402_6.3V6K 10U_0805_6.3V6M
VDD PEX_IOVDDQ
T17 VDD PEX_IOVDDQ AB16
+3VS +1.05VS
NEAR BGA NEAR BALL U9
U19
VDD
VDD
PEX_IOVDDQ
PEX_IOVDDQ
AB13
AB9 NEAR BGA 120mA
W9 AB8 L3
C 1U_0402_6.3V6K 0.1U_0402_10V7K VDD PEX_IOVDDQ 1U_0402_6.3V6K C
W10 VDD PEX_IOVDDQ AB7 1 2
W12 MBK1608121YZF_0603
VDD
120mA 1 1 1 1 1 W13
W18
VDD
VDD
PEX_IOVDD
PEX_IOVDD
AG7
AF7
1 1
DIS@
C84 C459 C44 C55 C54 W19 AE7 C45 C57
DIS@ DIS@ DIS@ DIS@ DIS@ VDD PEX_IOVDD DIS@ DIS@
PEX_IOVDD AD8
2 2 2 2 2 AD7 2 2
PEX_IOVDD
A12 VDD33 PEX_IOVDD AC9
4.7U 6.3V K X5R 0603 0.1U_0402_10V7K 0.1U_0402_10V7K B12 4.7U 6.3V K X5R 0603
VDD33 +PEX_PLLVDD
C12 VDD33 PEX_PLLVDD AF9
D12 VDD33
E12
F12
VDD33
VDD33
VID_PLLVDD K6
NEAR BALL NEAR BGA +1.05VS
L6 +SP_PLLVDD
SP_PLLVDD 0.1U_0402_10V7K 1U_0402_6.3V6K MBK1608121YZF_0603
NEAR
+1.8VS
BGA NEAR BALL +PEX_SVDD_3V3 AG9 PEX_SVDD_3V3 PLLVDD K5 +1.05VS_PLL 2 1
VID_PLLVDD=45mA
L27
MBK1608121YZF_0603 1U_0402_6.3V6K R19
12~16mil 1 1 1 1 L21
DIS@
1
DIS@
2
1 1 1
0.1U_0402_10V7K
1
+IFPA_IOVDD V3 IFPA_IOVDD
FB_PLLAVDD
AC19
C480
DIS@
C481
DIS@
C65
DIS@
C482
DIS@
SP_PLLVDD=45mA
FB_PLLAVDD 2 2 2 2
300mA C512 C499 C510 C511
+IFPB_IOVDD V2 IFPB_IOVDD
FB_DLLAVDD T19 +FB_PLLAVDD PLLVDD=60mA
DIS@ DIS@ DIS@ DIS@ +IFPC_IOVDD J6 0.1U_0402_10V7K 4.7U 6.3V K X5R 0603
2 2 2 2 IFPC_IOVDD
4.7U 6.3V K X5R 0603 2 1 H6 AG2 +DACA_VDD
0.1U_0402_10V7K 10K_0402_5% R41 IFPDE_IOVDD DACA_VDD
DIS@ W5 +DACB_VDD 1 2 +1.05VS
+IFPAB_PLLVDD DACB_VDD R45 DIS@ 10K_0402_5% L24
AD5 IFPAB_PLLVDD +SP_PLLVDD 1U_0402_6.3V6K 1 2
+IFPC_PLLVDD P6 B15 MBK1608121YZF_0603
IFPC_PLLVDD FB_CAL_PD_VDDQ +1.5VS
R465 DIS@ 40.2_0402_1% 1 1 DIS@
B 1U_0402_6.3V6K 0.1U_0402_10V7K 1 2 N6 W15 The power is base on VRAM type. B
R49 0_0402_5% IFPD_PLLVDD VDD_SENSE C64 C488
1 1 1
DIS@ D7 E15 +VGASENSE DIS@ DIS@
IFPE_PLLVDD VDD_SENSE +VGASENSE <45> 2 2
C498 C497 C496
DIS@ DIS@ DIS@ 4.7U 6.3V K X5R 0603
2 2 2 N11M-GE1-S-A3 _BGA533
DIS@
0.1U_0402_10V7K 2 1 @ NEAR BALL
+3VS +1.05VS
10K_0402_5% R47
1 DIS@
NEAR BGA
2
10K_0402_5% R43 120mA NEAR BGA L1
+PEX_SVDD_3V3 +FB_PLLAVDD 1U_0402_6.3V6K 1 2
+1.05VS L4 MBK1608121YZF_0603
MBK1608121YZF_0603 DIS@
NEAR BALL 1
C458
1 1

1 2 1U_0402_6.3V6K 0.1U_0402_10V7K DIS@ C30 C23 FB_PLLVDD=100mA

DIS@ DIS@ DIS@

285mA 1 1 1 1
2 2 2
FB_DLLVDD=100mA
C68 C67 C74 C66 0.1U_0402_10V7K 4.7U 6.3V K X5R 0603
DIS@ DIS@ DIS@ DIS@
2 2 2 2
L29
4.7U 6.3V K X5R 0603 0.1U_0402_10V7K NEAR BGA
+1.05VS NEAR BALL NEAR BGAMBK1608121YZF_0603
+3VS

L5 DIS@ 1U_0402_6.3V6K +DACA_VDD 4700P_0402_25V7K 0.1U_0402_10V7K 1U_0402_6.3V6K 2 1

1 2 +IFPAB_PLLVDD DIS@

NEAR BGA MBK1608121YZF_0603

1 1 1 1 1 1 1 1 1
120mA
C82 C71 C523 C522 C520 C513 C521 C519 C524
+3VS 220mA 2
DIS@
2
DIS@
2
DIS@
2
DIS@
2
DIS@
2
DIS@
2
DIS@
2
DIS@
2
DIS@
A
L6 DIS@ NEAR BALL A

1 2 1U_0402_6.3V6K 0.1U_0402_10V7K +IFPC_PLLVDD 4.7U 6.3V K X5R 0603 470P_0402_50V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 4.7U 6.3V K X5R 0603

MBK1608121YZF_0603
1 1 1 1 1
220mA C73 C72 C62 C63 C61
DIS@ DIS@ DIS@ DIS@ DIS@
2 2 2 2 2
0.1U_0402_10V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
4.7U 6.3V K X5R 0603 0.1U_0402_10V7K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N11M-GE1 PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5751 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 29, 2009 Sheet 21 of 51
5 4 3 2 1
 5 4 3 2 1

A total of 8 signals are required for GB1 strapping this includes

2 reference signals
6 physical strapping pins
4 logical strapping bits
U22E A total of 24 logical strapping bits are available
B2 Part 5 of 5 U2
GND GND
B5 U5
GND GND
B8 U11
GND GND
B11 GND GND U12
B14 GND GND U13
B17 U14 +3VS
D GND GND D
B20 GND GND U15
B23 GND GND U16
B26 GND GND U17
E2 U23
GND GND

1
E5 U26
GND GND R474 R472 R473 R51 R469 R467
E8 GND GND V9

30K_0402_1%

34.8K_0402_1%

45.3K_0402_1%
E11 V19 @ DIS@ DIS@ DIS@ @ @
GND GND

15K_0402_1%

2K_0402_5%
E17 GND GND W11

2K_0402_5%
E20 W14

2
GND GND
E23 W17
GND GND STRAP2
E26 GND GND Y2 <20> STRAP2
H2 Y5 STRAP1
GND GND <20> STRAP1

GND
H5 Y23 STRAP0
GND GND <20> STRAP0
J11 Y26 ROM_SCLK
GND GND <20> ROM_SCLK ROM_SI
J14 AC2 <20> ROM_SI
GND GND ROM_SO
J17 AC5 <20> ROM_SO
GND GND
K9 GND GND AC6
K19 AC8
GND GND

1
L2 GND GND AC11
L5 AC14 R475 R471 R476 R50 R470 R466
GND GND

30K_0402_1%

34.8K_0402_1%
L11 AC17 DIS@ @ @ @ X76@ DIS@
GND GND

10K_0402_5%

15K_0402_1%

20K_0402_1%

10K_0402_5%
L12 AC20
GND GND
L13 AC23

2
GND GND
L14 GND GND AC26
L15 AF2
GND GND
L16 GND GND AF5
L17 AF8
GND GND
M12 AF11
GND GND
M13 GND GND AF14
M14 GND GND AF17
M15 AF20
GND GND
M16 AF23
C GND GND C
P2 GND GND AF26
P5 T16
GND GND
P9 T15
GND GND
P19 GND GND T14
P23 GND GND F6
P26
GND R28
T12 GND FB_CAL_PU_GND A15 1 DIS@ 2 40.2_0402_1%
T13
GND R27
FB_CAL_TERM_GND B16 1 2 60.4_0402_1%
DIS@
W16 GND_SENSE MULTI_STRAP_REF1_GND F11

E14 GND_SENSE MULTI_STRAP_REF0_GND F10

1

1
R463 R464
N11M-GE1-S-A3 _BGA533 40.2K_0402_1% 40.2K_0402_1% STRAP1 use for 3GIO_PADCFG to set 35K pull up.
DIS@ DIS@ DIS@
(PUN-04335-001_V10 HW9 update)
Place Components Close to BGA
2

GPU FB Memory (DDR3) ROM_SO ROM_SCLK ROM_SI STRAP2 STRAP1 STRAP0

Samsung K4W1G1646E-HC12
Memory/PKG FBVDDQ FB_CAL_PU_GND FBCAL_PD_VDDQ FBCAL_TERM_GND 800MHz
N11M-GE1
LP1 N11M-GE1 (defaul) 64Mx16 PD 10K PU 15K PD 20K PD 30K PU 35K PU 45K
DDR3 +1.5VS 40.2 ohm 40.2 ohm 40.2/60.4 ohm LP1
(0x0A7D) Hynix H5TQ1G63BFR-12C
B 40nm 800MHz B

Must be used 1% resister for driver calibration DG-04642-001-V01(May 22, 2009) 64Mx16 PD 10K PU 15K PD 15K PD 30K PU 35K PU 45K

X76

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N11M-GE1 GND & STRAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B LA-5751 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 29, 2009 Sheet 22 of 51
5 4 3 2 1
 5 4 3 2 1

+VRAM_VREFB +VRAM_VREFB +VRAM_VREFD +VRAM_VREFD

N11x 40nm DDR3 MAPPING +VRAM_VREFC +VRAM_VREFC

+VRAM_VREFA +VRAM_VREFA
NVIDIA COCUMENT FOR DA-3978-001
U21 U2 U1 U23

FBAA[0..13] M9 E4 FBA_D9 M9 E4 FBA_D21 M9 E4 FBA_D37 M9 E4 FBA_D42

<20> FBAA[0..13] VREFCA DQL0 FBA_D14 VREFCA DQL0 FBA_D17 VREFCA DQL0 FBA_D36 VREFCA DQL0 FBA_D46
H2 F8 H2 F8 H2 F8 H2 F8
FBBA[2..5] VREFDQ DQL1 FBA_D8 VREFDQ DQL1 FBA_D20 VREFDQ DQL1 FBA_D35 VREFDQ DQL1 FBA_D40
F3 F3 F3 F3
<20> FBBA[2..5] FBAA0 DQL2 FBA_D12 FBAA0 DQL2 FBA_D16 FBAA0 DQL2 FBA_D32 FBAA0 DQL2 FBA_D45
FBADQM[0..7]
N4
A0 DQL3
F9 1 N4
A0 DQL3
F9 2 N4
A0 DQL3
F9 N4
A0 DQL3
F9
FBAA1 P8 H4 FBA_D10 FBAA1 P8 H4 FBA_D22 FBAA1 P8 H4 FBA_D39 4 FBAA1 P8 H4 FBA_D41 5
<20> FBADQM[0..7] A1 DQL4 A1 DQL4 A1 DQL4 A1 DQL4
FBAA2 P4 H9 FBA_D13 FBAA2 P4 H9 FBA_D18 FBBA2 P4 H9 FBA_D34 FBBA2 P4 H9 FBA_D47
FBADQS[0..7] FBAA3 A2 DQL5 FBA_D11 FBAA3 A2 DQL5 FBA_D23 FBBA3 A2 DQL5 FBA_D38 FBBA3 A2 DQL5 FBA_D44
<20> FBADQS[0..7] N3 G3 N3 G3 N3 G3 N3 G3
FBAA4 A3 DQL6 FBA_D15 FBAA4 A3 DQL6 FBA_D19 FBBA4 A3 DQL6 FBA_D33 FBBA4 A3 DQL6 FBA_D43
P9 H8 P9 H8 P9 H8 P9 H8
FBADQS#[0..7] FBAA5 A4 DQL7 FBAA5 A4 DQL7 FBBA5 A4 DQL7 FBBA5 A4 DQL7
<20> FBADQS#[0..7] P3 P3 P3 P3
FBAA6 A5 FBAA6 A5 FBAA6 A5 FBAA6 A5
R9 R9 R9 R9
FBA_D[0..63] FBAA7 A6 FBA_D26 FBAA7 A6 FBA_D4 FBAA7 A6 FBA_D61 FBAA7 A6 FBA_D50
<20> FBAD[0..63] R3 D8 R3 D8 R3 D8 R3 D8
D
FBAA8 A7 DQU0 FBA_D29 FBAA8 A7 DQU0 FBA_D1 FBAA8 A7 DQU0 FBA_D57 FBAA8 A7 DQU0 FBA_D52 D
T9 C4 T9 C4 T9 C4 T9 C4
FBAA9 A8 DQU1 FBA_D24 FBAA9 A8 DQU1 FBA_D7 FBAA9 A8 DQU1 FBA_D56 FBAA9 A8 DQU1 FBA_D49
R4 C9 R4 C9 R4 C9 R4 C9
FBAA10 A9 DQU2 FBA_D25 FBAA10 A9 DQU2 FBA_D0 FBAA10 A9 DQU2 FBA_D62 FBAA10 A9 DQU2 FBA_D53
L8
A10/AP DQU3
C3 3 L8
A10/AP DQU3
C3 L8
A10/AP DQU3
C3 L8
A10/AP DQU3
C3
FBAA11 R8 A8 FBA_D28 FBAA11 R8 A8 FBA_D5 0 FBAA11 R8 A8 FBA_D58 7 FBAA11 R8 A8 FBA_D48 6
FBAA12 A11 DQU4 FBA_D31 FBAA12 A11 DQU4 FBA_D2 FBAA12 A11 DQU4 FBA_D63 FBAA12 A11 DQU4 FBA_D54
N8 A3 N8 A3 N8 A3 N8 A3
FBAA13 A12 DQU5 FBA_D27 FBAA13 A12 DQU5 FBA_D6 FBAA13 A12 DQU5 FBA_D59 FBAA13 A12 DQU5 FBA_D51
T4 B9 T4 B9 T4 B9 T4 B9
A13 DQU6 FBA_D30 A13 DQU6 FBA_D3 A13 DQU6 FBA_D60 A13 DQU6 FBA_D55
T8 A4 T8 A4 T8 A4 T8 A4
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M8 M8 M8 M8
A15/BA3 +1.5VS A15/BA3 +1.5VS A15/BA3 +1.5VS A15/BA3 +1.5VS

FBA_BA0 M3 B3 FBA_BA0 M3 B3 FBA_BA0 M3 B3 FBA_BA0 M3 B3

<20> FBA_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
FBA_BA1 N9 D10 FBA_BA1 N9 D10 FBA_BA1 N9 D10 FBA_BA1 N9 D10
<20> FBA_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
FBA_BA2 M4 G8 FBA_BA2 M4 G8 FBA_BA2 M4 G8 FBA_BA2 M4 G8
<20> FBA_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K3 K3 K3 K3
VDD VDD VDD VDD
K9 K9 K9 K9
VDD VDD VDD VDD
N2 N2 N2 N2
VDD FBACLK0 VDD FBACLK1 VDD FBACLK1 VDD
<20> FBACLK0 J8 N10 J8 N10 <20> FBACLK1 J8 N10 J8 N10
CK VDD FBACLK0# CK VDD FBACLK1# CK VDD FBACLK1# CK VDD
<20> FBACLK0# K8 R2 K8 R2 <20> FBACLK1# K8 R2 K8 R2
FBAA_CKE CK VDD FBAA_CKE CK VDD CK VDD FBBA_CKE CK VDD
<20> FBAA_CKE K10 R10 K10 R10 K10 R10 K10 R10
CKE/CKE0 VDD +1.5VS CKE/CKE0 VDD +1.5VS FBBA_CKE CKE/CKE0 VDD +1.5VS CKE/CKE0 VDD +1.5VS
<20> FBBA_CKE
FBAAODT0 K2 A2 FBAAODT0 K2 A2 FBBAODT0 K2 A2 FBBAODT0 K2 A2
<20> FBAAODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ <20> FBBAODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBAACS0# L3 A9 FBAACS0# L3 A9 FBBACS0# L3 A9 FBBACS0# L3 A9
<20> FBAACS0# CS VDDQ CS VDDQ <20> FBBACS0# CS VDDQ CS VDDQ
FBARAS# J4 C2 FBARAS# J4 C2 FBARAS# J4 C2 FBARAS# J4 C2
<20> FBARAS# RAS VDDQ RAS VDDQ RAS VDDQ RAS VDDQ
FBACAS# K4 C10 FBACAS# K4 C10 FBACAS# K4 C10 FBACAS# K4 C10
<20> FBACAS# CAS VDDQ CAS VDDQ CAS VDDQ CAS VDDQ
FBAWE# L4 D3 FBAWE# L4 D3 FBAWE# L4 D3 FBAWE# L4 D3
<20> FBAWE# WE VDDQ WE VDDQ WE VDDQ WE VDDQ
E10 E10 E10 E10
VDDQ VDDQ VDDQ VDDQ
F2 F2 F2 F2
FBADQS1 VDDQ FBADQS2 VDDQ FBADQS4 VDDQ FBADQS5 VDDQ
F4 H3 F4 H3 F4 H3 F4 H3
FBADQS3 DQSL VDDQ FBADQS0 DQSL VDDQ FBADQS7 DQSL VDDQ FBADQS6 DQSL VDDQ
C8 H10 C8 H10 C8 H10 C8 H10
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

FBADQM1 E8 A10 FBADQM2 E8 A10 FBADQM4 E8 A10 FBADQM5 E8 A10

FBADQM3 DML VSS FBADQM0 DML VSS FBADQM7 DML VSS FBADQM6 DML VSS
D4 B4 D4 B4 D4 B4 D4 B4
DMU VSS DMU VSS DMU VSS DMU VSS
E2 E2 E2 E2
VSS VSS VSS VSS
G9 G9 G9 G9
FBADQS#1 VSS FBADQS#2 VSS FBADQS#4 VSS FBADQS#5 VSS
G4 J3 G4 J3 G4 J3 G4 J3
FBADQS#3 DQSL VSS FBADQS#0 DQSL VSS FBADQS#7 DQSL VSS FBADQS#6 DQSL VSS
C B8 J9 B8 J9 B8 J9 B8 J9 C
DQSU VSS DQSU VSS DQSU VSS DQSU VSS
M2 M2 M2 M2
VSS VSS VSS VSS
M10 M10 M10 M10
VSS VSS VSS VSS
P2 P2 P2 P2
FBA_RST VSS FBA_RST VSS FBA_RST VSS FBA_RST VSS
<20> FBA_RST T3 P10 T3 P10 T3 P10 T3 P10
RESET VSS RESET VSS RESET VSS RESET VSS
T2 T2 T2 T2
VSS VSS VSS VSS
L9 T10 L9 T10 L9 T10 L9 T10
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J2 B2 J2 B2 J2 B2 J2 B2
R12 NC/ODT1 VSSQ R21 NC/ODT1 VSSQ R7 NC/ODT1 VSSQ R523 NC/ODT1 VSSQ
L2 B10 L2 B10 L2 B10 L2 B10
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
240_0402_1% J10 D2 240_0402_1% J10 D2 240_0402_1% J10 D2 240_0402_1% J10 D2
DIS@ NC/CE1 VSSQ DIS@ NC/CE1 VSSQ DIS@ NC/CE1 VSSQ DIS@ NC/CE1 VSSQ
L10 D9 L10 D9 L10 D9 L10 D9
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E3 E3 E3 E3
2

2
VSSQ VSSQ VSSQ VSSQ
A1 E9 A1 E9 A1 E9 A1 E9
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
A11 F10 A11 F10 A11 F10 A11 F10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T1 G2 T1 G2 T1 G2 T1 G2
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T11 G10 T11 G10 T11 G10 T11 G10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3

K4B1G1646D-HCF8_FBGA100 K4B1G1646D-HCF8_FBGA100 K4B1G1646D-HCF8_FBGA100 K4B1G1646D-HCF8_FBGA100

X76@ X76@ X76@ X76@

+1.5VS
+1.5VS +1.5VS

10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M

1
1 1 1 1 1 1
R20 R11
B +VRAM_VREFA +VRAM_VREFB B
C21 C518 C444 C3 C6 C7 1.33K_0402_1% 1.33K_0402_1%
DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ DIS@ DIS@
2 2 2 2 2 2

2
10U_0603_6.3V6M 10U_0603_6.3V6M
10U_0603_6.3V6M
12MIL 12MIL
FBACLK0
2

C4
C22
1 1

0.1U_0402_10V6K

0.1U_0402_10V6K
DIS@ R19 R10
243_0402_1% 1.33K_0402_1% DIS@ 1.33K_0402_1% DIS@
R442 DIS@ DIS@
FBACLK0# +1.5VS 2 2
1

2
1U_0402_6.3V4Z 1U_0402_6.3V4Z
FBACLK1 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1

R14 1 1 1 1 1 1 1 1 1 1
C517

C509

C5

C20

C487

C479

C437

C445

C446

C525

243_0402_1%
DIS@
FBACLK1# DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2

2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z
+1.5VS +1.5VS

1
+1.5VS R9 R529
+1.5VS 1.33K_0402_1% +VRAM_VREFC 1.33K_0402_1% +VRAM_VREFD
220U_B2_2.5VM_R35

1U_0402_6.3V4Z 1U_0402_6.3V4Z DIS@ DIS@

1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1

2
C436

+ DIS@
12MIL 12MIL
1 1 1 1 1 1 1 1 1 1
C526

C438

C10

C9

C18

C17

C12

C11

C16

C19

1
C8

C495
2 1 1

0.1U_0402_10V6K

0.1U_0402_10V6K
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ R8 R522
2 2 2 2 2 2 2 2 2 2 1.33K_0402_1% 1.33K_0402_1%
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z DIS@ DIS@ DIS@ DIS@
A 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 2 A

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDR3
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-5751 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 29, 2009 Sheet 23 of 51
5 4 3 2 1
 5 4 3 2 1

C284 1 2 DIS@ 0.1U_0402_16V7K HDMI_CLK+_CK <25> HDMI_CLK+_CK HDMI_CLK+_CK

<20> VGA_HDMI_CLK+
C283 1 2 DIS@ 0.1U_0402_16V7K HDMI_CLK-_CK <25> HDMI_CLK-_CK HDMI_CLK-_CK
<20> VGA_HDMI_CLK-
C282 1 2 DIS@ 0.1U_0402_16V7K HDMI_TX0+_CK <25> HDMI_TX0+_CK HDMI_TX0+_CK
<20> VGA_HDMI_TX0+
C281 1 2 DIS@ 0.1U_0402_16V7K HDMI_TX0-_CK <25> HDMI_TX0-_CK HDMI_TX0-_CK
<20> VGA_HDMI_TX0-
C601 1 2 DIS@ 0.1U_0402_16V7K HDMI_TX1+_CK <25> HDMI_TX1+_CK HDMI_TX1+_CK
<20> VGA_HDMI_TX1+
C600 1 2 DIS@ 0.1U_0402_16V7K HDMI_TX1-_CK <25> HDMI_TX1-_CK HDMI_TX1-_CK
<20> VGA_HDMI_TX1-
C614 1 2 DIS@ 0.1U_0402_16V7K HDMI_TX2+_CK <25> HDMI_TX2+_CK HDMI_TX2+_CK
<20> VGA_HDMI_TX2+
C599 1 2 DIS@ 0.1U_0402_16V7K HDMI_TX2-_CK <25> HDMI_TX2-_CK HDMI_TX2-_CK
<20> VGA_HDMI_TX2-
D D

L15 DIS@ MBK1608121YZF_0603

<20> VGA_HDMI_SDA 1 2 HDMIDAT_R
<20> VGA_HDMI_SCL 1 2 HDMICLK_R
L16 DIS@ MBK1608121YZF_0603

1 1
C295 C302

DIS@ DIS@
2 2
12P_0402_50V8J 12P_0402_50V8J

C C

HDMI_CLK+_CONN 1 2
R585 DIS@ 499_0402_1%
HDMI_CLK-_CONN 1 2
R583 DIS@ 499_0402_1%
HDMI_TX0+_CONN 1 2
R589 DIS@ 499_0402_1% +5VS
HDMI_TX0-_CONN 1 2
R587 DIS@ 499_0402_1%
HDMI_TX1+_CONN 1 2

2
R593 DIS@ 499_0402_1%
D
1

HDMI_TX1-_CONN 1 2 HDMI@
R591 DIS@ 499_0402_1% 2 +3VS R581 @ D28
HDMI_TX2+_CONN 1 2 G 0_0805_5% RB491D_SC59-3
R597 DIS@ 499_0402_1% S DIS@ +5VS
3

1
HDMI_TX2-_CONN 1 2 Q41 +5VS_HDMI
R595 DIS@ 499_0402_1% 2N7002W-T/R7_SOT323-3

2
1 C627
NEAR CONNECT 0.1U_0402_16V4Z

2
B B
L33 @ HDMI@
HDMI_CLK+_CK HDMI_CLK+_CONN R249 R257 2
1 1 2 2
@ 2.2K_0402_5% 2.2K_0402_5%

1
D23 HDMI@ HDMI@

1
HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN BAT54S-7-F_SOT23-3
4 3 HDMI_DET_UMA
<25> HDMI_DET_UMA
WCM-2012-900T_4P
R579
L34 @ 10K_0402_1% DIS@ JHDMI1
HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN HDMI_DETECT_VGA 1 2 1 2 19
1 2 <19> HDMI_DETECT_VGA HP_DET
DIS@ MBK1608121YZF_0603 L30 18 +5V
1

DIS@ 17
HDMI_TX0-_CK HDMI_TX0-_CONN @ R578 C603 HDMIDAT_R DDC/CEC_GND
4 4 3 3 <25> HDMIDAT_R 16 SDA
D22 100K_0402_5% 330P_0402_50V7K <25> HDMICLK_R HDMICLK_R 15
WCM-2012-900T_4P RB751V_SOD323 DIS@ SCL
14 Reserved
13
2

L35 @ HDMI_CLK-_CONN CEC

12 CK- GND 20
HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN 11 21
1 2 HDMI_CLK+_CONN CK_shield GND
10 CK+ GND 22
HDMI_TX0-_CONN 9 23
HDMI_TX1-_CK HDMI_TX1-_CONN D0- GND
4 4 3 3 8 D0_shield
HDMI_TX0+_CONN 7
WCM-2012-900T_4P +5VS +5VS HDMI_TX1-_CONN D0+
6 D1-
5 D1_shield
L36 @ 3 3 HDMI_TX1+_CONN 4
HDMI_TX2+_CK HDMI_TX2+_CONN HDMI_TX2-_CONN D1+
1 1 2 2 3 D2-
1 HDMIDAT_R 1 HDMICLK_R 2
HDMI_TX2+_CONN D2_shield
A 1 D2+ A
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN 2 @ 2 @
4 3 D24 D25 TAITW_PDVBR9-19FLBS4NN4N1
WCM-2012-900T_4P BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 ME@

HDMI_CLK+_CK R584 1 HDMI@ 2 0_0402_5% HDMI_CLK+_CONN

HDMI_CLK-_CK R582 1 HDMI@ 2 0_0402_5% HDMI_CLK-_CONN
HDMI_TX0+_CK R588 1 HDMI@ 2 0_0402_5% HDMI_TX0+_CONN Security Classification Compal Secret Data Compal Electronics,Ltd.
HDMI_TX0-_CK R586 1 HDMI@ 2 0_0402_5% HDMI_TX0-_CONN 2008/03/25 2008/04/ Title
Issued Date Deciphered Date
HDMI_TX1+_CK R592 1 HDMI@ 2 0_0402_5% HDMI_TX1+_CONN
HDMI_TX1-_CK R590 1 HDMI@ 2 0_0402_5% HDMI_TX1-_CONN HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI_TX2+_CK R596 1 HDMI@ 2 0_0402_5% HDMI_TX2+_CONN Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
HDMI_TX2-_CK R594 1 HDMI@ 2 0_0402_5% HDMI_TX2-_CONN Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 24 of 51
5 4 3 2 1
 5 4 3 2 1

P/N:SA00003GT00 (ASM1442) P/N:SA00002D700 (8101T)

P/N:SA00001U900 (CH7318A)
FOR asmedia R230 STUFF FOR 7318C PIN6 PULL DOWN 1.2Kohm
RESERVE THE R232 PULL UP TO 3VS PIN7 PULL DOWN 7.5Kohm
D RESERVE THE R247 PULL DOWN TO GND PIN7 PULL UP 20Kohm D

CHANGE R245 FROM 499 TO 3.4K OHM

+3VS

1
@
R231 U12
0_0402_5%
2

25 +3VS +3VS
OE#
1

+3VS 2
VCC

1
UMA_HDMI@ <24> HDMICLK_R HDMICLK_R 28 11 1 1 1 1
R230 SCL_SINK VCC UMA_HDMI@ UMA_HDMI@ UMA_HDMI@ UMA_HDMI@ R253
output VCC 15
1

0_0402_5% <24> HDMIDAT_R HDMIDAT_R 29 21 C280 C602 C604 C285 20K_0402_1%

R242 SDA_SINK VCC 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z @
26
2

VCC 2 2 2 2 TMDS_B_HPD#
4.7K_0402_5% 33

1 2
HDMI_DET_UMA 30 VCC
UMA_HDMI@ <24> HDMI_DET_UMA HPD_SINK VCC 40
internal pull down 46
2

VCC 4.7K_0402_5% R252

32 DDC_EN R247 1 @ 2 +3VS 7.5K_0402_1%
1

+3VS 4.7K_0402_5% @
C @ R254 1 2 @ 34 R246 1 2 @ 4.7K_0402_5% C
PC1 4

2
R243 R255 CFG0
1 2 @ 35 CFG1 3
PC0 internal
R248 1 2 @ 4.7K_0402_5%
0_0402_5% 4.7K_0402_5% pull down
UMA_HDMI@
2

6 R245 1 2 3.4K_0402_1%
REXT
2

2
R244 R256 7 TMDS_B_HPD#
HPD# TMDS_B_HPD# <15>
4.7K_0402_5% 4.7K_0402_5%
@ @ SDA 8 HDMIDAT_NB <15>
input
1

SCL 9 HDMICLK_NB <15>

+3VS
10 R232 1 @ 2 4.7K_0402_5%
RT_EN#

48 13 HDMI_CLK+_CK
<15> TMDS_B_CLK IN_D4+ OUT_D4+ HDMI_CLK+_CK <24>
47 14 HDMI_CLK-_CK
<15> TMDS_B_CLK# IN_D4- OUT_D4- HDMI_CLK-_CK <24>
45 16 HDMI_TX0+_CK
<15> TMDS_B_DATA0 IN_D3+ OUT_D3+ HDMI_TX0+_CK <24>
44 17 HDMI_TX0-_CK
<15> TMDS_B_DATA0# IN_D3- OUT_D3- HDMI_TX0-_CK <24>
42 19 HDMI_TX1+_CK
<15> TMDS_B_DATA1 IN_D2+ OUT_D2+ HDMI_TX1+_CK <24>
41 20 HDMI_TX1-_CK
<15> TMDS_B_DATA1# IN_D2- OUT_D2- HDMI_TX1-_CK <24>
<15> TMDS_B_DATA2 39 22 HDMI_TX2+_CK
IN_D1+ OUT_D1+ HDMI_TX2-_CK HDMI_TX2+_CK <24>
<15> TMDS_B_DATA2# 38 IN_D1- OUT_D1- 23 HDMI_TX2-_CK <24>

B B

GND 1
GND 5
GND 12
GND 18
GND 24
GND 27
GND 31
GND 36
GND 37
GND 43
PAD 49

ASM1442_QFN48_7X7
UMA_HDMI@

A A

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
Level Shiftter_ASM1442
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 25 of 51
5 4 3 2 1
 A B C D E

+5VS +5VS +5VS +5VS +5VS

3 3 3 3 3

1 BLUE 1 GREEN 1 RED 1 JVGA_HS 1 JVGA_VS

2 2 2 BAT54S-7-F_SOT23-3 2 2
@ @ @ @ @
D1 D2 D3 D27 D26
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3

1 <15> DAC_RED
DAC_RED

DAC_GRN
R92
1 2
UMA@ 0_0402_5%
CRT_R

CRT_G CRT_R
FCM1608CF-121T03 0603
RED
+5VS
D21
+CRT_VCC
CRT Connector
F1
1

<15> DAC_GRN 1 2 UMA only 1 2

R91 UMA@ 0_0402_5% L11 2 1 1 2
DAC_BLU 1 2 CRT_B FCM1608CF-121T03 0603 1
<15> DAC_BLU
R93 UMA@ 0_0402_5% CRT_G 1 2 GREEN RB491D_SC59-3
L10 1.1A_6V_SMD1812P110TF C629
FCM1608CF-121T03 0603 0.1U_0402_16V4Z
CRT_B 1 2 BLUE W=40mils 2
L9

1
VGA_CRT_R 1 2 CRT_R 1 1 1 1 1 1
<19> VGA_CRT_R
R66 DIS@ 0_0402_5%
VGA_CRT_G 1 2 CRT_G R153 R131 R90 C158 C146 C137 C157 C145 C136
<19> VGA_CRT_G
R65 DIS@ 0_0402_5% DIS only 150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J
VGA_CRT_B CRT_B 2 2 2 2 2 2 JCRT1
<19> VGA_CRT_B 1 2

2
R67 DIS@ 0_0402_5% 6
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 11
CLOSE TO CONN RED 1
7
CRT_DDC_DAT_CONN 12
GREEN 2
8
JVGA_HS 13
BLUE 3
9
JVGA_VS 14 G 16
4 G 17
10
CRT_DDC_CLK_CONN 15
2 5 2
+CRT_VCC 1
R575
C628 TYCO_1775763-1
1 2 ME@
1 100P_0402_50V8J
2
C619 1K_0402_5%
0.1U_0402_16V4Z
2

1
UMA@ R94 0_0402_5%

OE#
P
1 2 HSYNC_G 2 4 CRT_HSYNC_1 1 2 JVGA_HS
<15> CRT_HSYNC A Y L32 FCM1608CF-121T03 0603

G
DIS@ R68 0_0402_5% U26
1 2 SN74AHCT1G125DCKR_SC70-5 1
<19> VGA_HSYNC

3
@
C626
10P_0402_50V8J
+CRT_VCC 2
R580
1 2
1
C620 1K_0402_5%
0.1U_0402_16V4Z
2

1
UMA@ R95 0_0402_5%

OE#
P
1 2 VSYNC_G 2 4 CRT_VSYNC_1 1 2 JVGA_VS
3 <15> CRT_VSYNC A Y 3
L31 FCM1608CF-121T03 0603

G
DIS@ R69 0_0402_5% U25 1
1 2 SN74AHCT1G125DCKR_SC70-5
<19> VGA_VSYNC

3
@ C625
10P_0402_50V8J
2
+3VS +3VS +CRT_VCC
1

R159 R162
2.2K_0402_5% 2.2K_0402_5% R157 R158
5

2.2K_0402_5% 2.2K_0402_5%
2

<15> CRT_DDC_DATA CRT_DDC_DATA 2 UMA@ 1 CRT_DDC_DATA_R 4 3 CRT_DDC_DAT_CONN

R96 0_0402_5%
<19> VGA_DDCDATA VGA_DDCDATA 2 DIS@ 1 Q13B
2

R70 0_0402_5% 2N7002DW-T/R7_SOT363-6

<15> CRT_DDC_CLK CRT_DDC_CLK 2 UMA@ 1 CRT_DDC_CLK_R 1 6 CRT_DDC_CLK_CONN

R97 0_0402_5% 1 1
<19> VGA_DDCCLK VGA_DDCCLK 2 DIS@ 1 Q13A @ @
R71 0_0402_5% 2N7002DW-T/R7_SOT363-6 C178 C177
100P_0402_50V8J 68P_0402_50V8K
2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 26 of 51
A B C D E
 5 4 3 2 1

INVPWM
+LEDVDD B+
DAC_BRIG
1 R549 2 0_0805_5%

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K
DISPOFF# 1 1 1 R550 2 0_0805_5%
C567
C15 680P_0402_50V7K C566
1 @ 1 @ 1 @ @ 4.7U_0805_25V6-K
C13 C296 2 2

JLVDS1 +CMOS_PW
2 2 2 2 1
2 1 USB20_N2
+LCDVDD_CONN
4 4 3 3 USB20_N2 <16> CMOS
D
For EMI (60 MIL) 6 6 5 5 USB20_P2 USB20_P2 <16> D
8 8 7 7
10 9 CONN_LVDS_A0#
10 9 CONN_LVDS_A0
12 11
LCD POWER CIRCUIT +3VS 14
16
12
14
11
13
13
15 CONN_LVDS_A1#
@ LCD_COLOR_1 16 15
1 <34> INVT_PWM R17 1 2 INVPWM 18 17 CONN_LVDS_A1
680P_0402_50V7K 0_0402_5% DIS@ DISPOFF# 18 17
20 19
+LCDVDD +5VALW C14 20 19 CONN_LVDS_A2#
<34> DAC_BRIG 22 22 21 21
24 23 CONN_LVDS_A2
2 24 23
26 25
+3VS 26 25 CONN_LVDS_ACLK#
W=60mils +3VS
28 28 27 27
CONN_LVDS_ACLK
30 29
30 29

1
R13 R31
150_0603_1% 100K_0402_5% 1 32 31
C539 GNDGND
4.7U_0805_10V4Z R392 R395 ACES_87142-3041
2.2K_0402_5% 2.2K_0402_5% ME@

2
1

3
D S
R38 220K_0402_5% 2 @
G @
2 1 2 2
Q3 G CONN_LVDS_SCL
2N7002_SOT23 S 1
D AO3413_SOT23-3 CONN_LVDS_SDA
3

1
1
DTC124EK C34 Q4
W=60mils

OUT
0.1U_0402_16V4Z
2 +LCDVDD +LCDVDD_CONN
L2
<15> PCH_ENVDD R35 2 1 0_0402_5% LCD_ENVDD 2
UMA@ IN
1 2

GND
Q5 FBMA-L11-201209-221LMA30T_0805
1

<19> VGA_ENVDD_R R36 2 1 0_0402_5% DTC124EKAT146_SC59-3 1 1

3

DIS@ C33 C25 +3VS

R37 @
C 100K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z C

1
2 2
2

R250

4.7K_0402_5%
D12

2
BKOFF# 1 2 DISPOFF#
<34> BKOFF#
CH751H-40PT_SOD323-2

+3VS R261 DIS@ 0_0402_5%

<19> VGA_ENBKL_R 1 2 ENBKL <34>
UMA@
U6
5

<15> PCH_ENBKL R260 1 2 0_0402_5%

1 UMA@
P

NC

2
2 4 PCH_PWM_R 1 R161 2 INVPWM
<15> PCH_PWM A Y 0_0402_5% R259
G

100K_0402_1%
TC7SZ14FU_SSOP5
3

UMA@

1
@
1 R160 2
2
G

0_0402_5%

3 1 INVPWM 2 R156 1 +3VS

10K_0402_5% @
S

B B
2N7002_SOT23
Q12
@
For GMCH DPST

CMOS Camera
VGA_LVDS_SCL 0_0402_5% 2 DIS@ 1 R390 CONN_LVDS_SCL +5VS Q24 AO3413_SOT23-3
<19> VGA_LVDS_SCL
<19> VGA_LVDS_SDA VGA_LVDS_SDA 0_0402_5% 2 DIS@ 1 R391 CONN_LVDS_SDA

D
3 1
VGA_LVDS_A0 0_0402_5% 2 DIS@ 1 R86 CONN_LVDS_A0 1
<20> VGA_LVDS_A0

1
VGA_LVDS_A0# 0_0402_5% 2 DIS@ 1 R85 CONN_LVDS_A0# CMOS@
<20> VGA_LVDS_A0#
CMOS@ C275

G
2
VGA_LVDS_A1 0_0402_5% 2 DIS@ 1 R150 CONN_LVDS_A1 R270 R280 0.1U_0402_16V4Z
<20> VGA_LVDS_A1 2 CMOS@
VGA_LVDS_A1# 0_0402_5% 2 DIS@ 1 R128 CONN_LVDS_A1# 10K_0402_5% 0_0603_5%
<20> VGA_LVDS_A1#
CMOS@

2
VGA_LVDS_A2 CONN_LVDS_A2 C326
0_0402_5% 2 DIS@ 1 R126 0.01U_0402_16V7K
<20> VGA_LVDS_A2 VGA_LVDS_A2# CONN_LVDS_A2# CMOS1
0_0402_5% 2 DIS@ 1 R127 1 2 +CMOS_PW
<20> VGA_LVDS_A2#

1
VGA_LVDS_ACLK 0_0402_5% 2 DIS@ 1 R84 CONN_LVDS_ACLK CMOS@ 1

OUT
<20> VGA_LVDS_ACLK
VGA_LVDS_ACLK#0_0402_5% 2 DIS@ 1 R125 CONN_LVDS_ACLK#
<20> VGA_LVDS_ACLK#
C337
2 10U_0805_10V4Z
<34> CMOS_OFF# IN 2 CMOS@

GND
<15> EDID_CLK EDID_CLK 0_0402_5% 2 UMA@ 1 R393 CONN_LVDS_SCL
<15> EDID_DATA EDID_DATA 0_0402_5% 2 UMA@ 1 R394 CONN_LVDS_SDA Q21
A DTC124EKAT146_SC59-3 A

3
LVDS_A0 0_0402_5% 2 UMA@ 1 R383 CONN_LVDS_A0 CMOS@
<15> LVDS_A0 LVDS_A0# CONN_LVDS_A0#
0_0402_5% 2 UMA@ 1 R382
<15> LVDS_A0#
LVDS_A1 0_0402_5% 2 UMA@ 1 R389 CONN_LVDS_A1
<15> LVDS_A1 LVDS_A1# CONN_LVDS_A1#
0_0402_5% 2 UMA@ 1 R388
<15> LVDS_A1#
LVDS_A2 0_0402_5% 2 UMA@ 1 R386 CONN_LVDS_A2
<15>
<15>
LVDS_A2
LVDS_A2#
LVDS_A2# 0_0402_5% 2 UMA@ 1 R387 CONN_LVDS_A2# Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
LVDS_ACLK 0_0402_5% 2 UMA@ 1 R384 CONN_LVDS_ACLK
<15> LVDS_ACLK
<15> LVDS_ACLK#
LVDS_ACLK# 0_0402_5% 2 UMA@ 1 R385 CONN_LVDS_ACLK#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 27 of 51
5 4 3 2 1
 A B C D E

Mini-Express Card for WLAN/WiMAX(Half)

Mini-Express Card for WWAN(Full) +1.5VS +3VALW

1
Mini-Express Card(WLAN/WiMAX)

2
J4 C422

2
+3VS JUMP_43X79 0.1U_0402_16V4Z
JP10 2
@

1
<15> PCIE_WAKE# PCIE_WAKE# 1 2
BT_ACTIVE R333 1 WAKE# 3.3V 2Watt
2 @ 0_0402_5% 3 4
<37> BT_ACTIVE Reserve for SW mini-pcie debug card.

1
NC GND
5 6
WLAN_CLKREQ1# NC 1.5V LPC_FRAME#_R
<14> WLAN_CLKREQ1# 7
9
CLKREQ# NC
8
10 LPC_AD3_R Series resistors closed to KBC side.
GND NC LPC_AD2_R
<14> CLK_PCIE_WLAN1# 11 12
1 REFCLK- NC LPC_AD1_R LPC_FRAME#_R R284 @ 0_0402_5% LPC_FRAME# 1
<14> CLK_PCIE_WLAN1 13 14 1 2 LPC_FRAME# <13,34>
REFCLK+ NC LPC_AD0_R LPC_AD3_R R285 @ 0_0402_5% LPC_AD3
15 16 1 2 LPC_AD3 <13,34>
PCI_RST#_R GND NC LPC_AD2_R R286 @ 0_0402_5% LPC_AD2
17 18 1 2 LPC_AD2 <13,34>
CLK_PCI_DB NC GND R377 1 0_0402_5% LPC_AD1_R R287 @ 0_0402_5% LPC_AD1
19 20 2 WL_OFF# <34> 1 2 LPC_AD1 <13,34>
NC NC LPC_AD0_R R288 @ 0_0402_5% LPC_AD0
21 22 BUF_PLT_RST# <5,16,19,29> 1 2 LPC_AD0 <13,34>
GND PERST# R376 1 PCI_RST#_R PCI_RST#
<14> PCIE_PRX_DTX_N2 23 24 2 @ 0_0402_5% +3VALW R290 1 @ 2 0_0402_5%
PCI_RST# <16,34>
PERn0 +3.3Vaux R375 1 0_0402_5% CLK_PCI_DB
<14> PCIE_PRX_DTX_P2 25 26 2 +3VS CLK_PCI_DB <14>
PERp0 GND
27 28
GND +1.5V R374 1
29 30 2 @ 0_0402_5% SMB_CLK_S3 <10,11,12,14>
GND SMB_CLK R373 1
<14> PCIE_PTX_C_DRX_N2 31 32 2 @ 0_0402_5% SMB_DATA_S3 <10,11,12,14>
PETn0 SMB_DATA
<14> PCIE_PTX_C_DRX_P2 33 34
PETp0 GND
35 36 USB20_N8 <16>
+3VS GND USB_D-
37 38 USB20_P8 <16>
NC USB_D+
39 40
NC GND 300_0402_5%
41 42 2 @ 1 R372
NC LED_WWAN# 300_0402_5% WLAN_LED#
43 44 2 1 R371 WLAN_LED# <36>
100_0402_1% NC LED_WLAN#
45 46
R274 NC LED_WPAN#
47 48
EC_TX_P80_DATA 1 NC +1.5V
<34,35> EC_TX_P80_DATA 2 49 50
EC_RX_P80_CLK 1 NC GND
<34,35> EC_RX_P80_CLK 2 51 52
R273 NC +3.3V
100_0402_1% 53 54
GND GND

TAITW_PFPET0-AFGLBG1ZZ4N0
ME@

+3VS
2 2
D4 @
Mini-Express Card(WWAN 3G) +3VS
1 1
@
CM1293-04SO_SOT23-6
@
C418 C420 1 4 UIM_DATA 2 1 +UIM_PWR
10U_0805_10V4Z 10U_0805_10V4Z CH1 CH4 R152
JP9 2 2 10K_0402_5%
<15> PCIE_WAKE# PCIE_WAKE# 1 2 +3VS
BT_ACTIVE R370 1 WAKE# 3.3V +1.5VS 2Watt
<37> BT_ACTIVE 2 @ 0_0402_5% 3 4 2 5
NC GND Vn Vp
5 6
PCIECLKREQ3# NC 1.5V +UIM_PWR
<14> PCIECLKREQ3# 7 8
CLKREQ# NC UIM_DATA
9 10
GND NC UIM_CLK
<14> CLK_PCIE_CARD_PCH# 11 12 3 6
REFCLK- NC UIM_RST CH2 CH3 +3VS
<14> CLK_PCIE_CARD_PCH 13 14
REFCLK+ NC UIM_VPP DAN217T146_SC59-3
15 16
GND NC JP2
17
NC GND
18
+UIM_PWR
40mil 3
19 20 R368 1 3G@ 2 0_0402_5% 4 1 1
NC NC 3G_OFF# <34> GND VCC
21 22 UIM_VPP 5 2 UIM_RST 2
GND PERST# BUF_PLT_RST# <5,16,19,29> VPP RST
23 24 R367 1 2 @ 0_0402_5% +3VALW UIM_DATA 6 3 UIM_CLK
<14> PCIE_PRX_DTX_N4 PERn0 +3.3Vaux I/O CLK @ D5
25 26 R369 1 2 @ 0_0402_5% +3VS 7
<14> PCIE_PRX_DTX_P4 PERp0 GND DET
27 28

4.7U_0805_10V4Z
GND +1.5V R366 1
29 30 2 @ 0_0402_5% SMB_CLK_S3 <10,11,12,14> 1 1
GND SMB_CLK

1
R365 1 2 @ 0_0402_5%

C188
31 32

10K_0402_5%
<14> PCIE_PTX_C_DRX_N4 PETn0 SMB_DATA SMB_DATA_S3 <10,11,12,14>

R151
33 34 8 C176
<14> PCIE_PTX_C_DRX_P4 PETp0 GND GND
35 36 USB20_N13 9 0.1U_0402_16V4Z
GND USB_D- USB20_N13 <16> GND 2 2
Vcc 3.3V +/- 8% 37 38 USB20_P13
NC USB_D+ USB20_P13 <16>
39 40

2
Peak Icc 2750mA +3VS NC GND
41 42
NC LED_WWAN#
with max supply droop 50mA 43 44
3G@ NC LED_WLAN# +1.5VS +UIM_PWR
45 46
Average Icc 1000mA 100_0402_1% NC LED_WPAN# TAITW_PMPAT6-06GLBS7N14N0
47 48
EC_TX_P80_DATA R364 1 NC +1.5V ME@
<34,35> EC_TX_P80_DATA 2 49 50
EC_RX_P80_CLK NC GND
<34,35> EC_RX_P80_CLK 1 2 51 52 1 1
NC +3.3V
R363
100_0402_1% 53 54 C417 C419
3G@ GND GND 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
TAITW_PFPET0-AFGLBG1ZZ4N0
3 3
ME@

+1.5VS +1.5VS_CARD1
New Card 34mm Socket (Left/TOP)
1 Express Card Power Switch Imax = 0.75A JEXP1
1 1
C358 1
0.1U_0402_16V4Z +1.5VS U15 +1.5VS_CARD1 C360 C359 USB20_N10 GND
<16> USB20_N10 2
2 10U_0805_10V4Z 0.1U_0402_16V4Z USB20_P10 USB_D-
12 11 <16> USB20_P10 3
1.5Vin 1.5Vout 2 2 CPUSB# USB_D+
14 13 4
1.5Vin 1.5Vout 40mil <16> CPUSB#
5
CPUSB#
+3VS_CARD1 RSV
6
+3VS RSV
2 3 7
+3VS
4
3.3Vin 3.3Vout
5
60mil +3VS_CARD1 <10,11,12,14>
<10,11,12,14>
SMB_CLK_S3
SMB_DATA_S3 8
SMB_CLK
3.3Vin 3.3Vout +3VALW_CARD1 SMB_DATA
9
1
17 15
Imax = 1.35A +1.5VS_CARD1
10
+1.5V
C386
+3VALW AUX_IN AUX_OUT 40mil 1 1 <15> PCIE_WAKE# 11
+1.5V
0.1U_0402_16V4Z WAKE#
<5,16,19,29> BUF_PLT_RST# 6 19 +3VALW_CARD1 12
2 SYSRST# OC# C388 C387 PERST# +3.3VAUX
13
SYSON PERST# 10U_0805_10V4Z 0.1U_0402_16V4Z PERST#
<34,39,44> SYSON 20 8 +3VS_CARD1 14
SHDN# PERST# 2 2 +3.3V
15
SUSP# +3.3V
<16,34,39,42,44,46> SUSP# 1 16 <14> CLKREQ_EXP# 16
+3VALW STBY# NC CPUSB# CLKREQ#
17
R334 1 CPPE#
+3VALW 2 @ 100K_0402_5% 10 7 <14> CLK_PCIE_EXP_PCH# 18
CPPE# GND +3VALW_CARD1 REFCLK-
1 <14> CLK_PCIE_EXP_PCH 19
CPUSB# REFCLK+
9 20
C372
<16> CPUSB# CPUSB# Imax = 0.275A 21
GND
<14> PCIE_PRX_DTX_N5 PERn0
0.1U_0402_16V4Z 18 1 1 22
2 RCLKEN <14> PCIE_PRX_DTX_P5 PERp0
@ 23
C356 C357 GND
G577BSR91U_QFN20 <14> PCIE_PTX_C_DRX_N5 24
10U_0805_10V4Z 0.1U_0402_16V4Z PETn0
<14> PCIE_PTX_C_DRX_P5 25
2 2 PETp0
4 26 4
GND
27
GND
28
GND
SANTA_130801-5_LT
ME@

Security Classification
2007/10/15
Compal Secret Data
2008/10/15 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/Nwe Card/SIM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 28 of 51
A B C D E
 A B C D E

Close to 8111DL pins--1,29,37

1 2 +3V_LAN
R182 3.6K_0402_5%
+3V_LAN
100@
0.1U_0402_16V4Z

LAN_DI 2 2 2
C597 C613 C246
LAN_CS
1 1 1
0.1U_0402_16V4Z
1 2
4 R203 1K_0402_5% 0.1U_0402_16V4Z 4

Place Close to Chip U24

C593 0.1U_0402_10V6K PCIE_IRX_C_PTX_P3 20 33

<14> PCIE_PRX_DTX_P3 HSOP LED3/EEDO LAN_DI
LED2/EEDI/AUX 34
C594 0.1U_0402_10V6K PCIE_IRX_C_PTX_N3 21 35 LAN_SK#
<14> PCIE_PRX_DTX_N3 HSON LED1/EESK LAN_SK# <30>
32 LAN_CS
EECS
<14> PCIE_PTX_C_DRX_P3 15 HSIP
38 ACTIVITY#
LED0 ACTIVITY# <30>
<14> PCIE_PTX_C_DRX_N3 16 HSIN
RTL8111DL 2 MDI0+
MDIP0 MDI0- MDI0+ <30>
<14> CLK_PCIE_LAN 17 3 MDI0- <30>
REFCLK_P MDIN0 MDI1+
<14> CLK_PCIE_LAN# 18 5 MDI1+ <30>
REFCLK_N MDIP1 MDI1-
MDIN1 6 MDI1- <30>
25 8 MDI2+
<14> CLKREQ_LAN# CLKREQB MDIP2 MDI2+ <30>
9 MDI2-
MDIN2 MDI3+ MDI2- <30>
<5,16,19,28> BUF_PLT_RST# 27 11 MDI3+ <30>
PERSTB MDIP3 MDI3-
12 MDI3- <30>
MDIN3
R171 1 2 2.49K_0402_1% 46 4 +LAN_VDD12
RSET FB12
26 48 VCTRL12
<34> LAN_WAKE# LANWAKEB SROUT12
ISOLATEB 28 ISOLATEB
+3V_LAN 2 1 19 +EVDD12
R206 10K_0402_5% LAN_XTALI EVDD12
41 30 +LAN_VDD12
@ LAN_XTALO CKTAL1 DVDD12
42 CKTAL2 DVDD12 36
DVDD12 13
10 C243
AVDD12
2 R177 1 GIGA@
3 +3VS GIGA@ 0_0402_5% 3
AVDD12 39 2 1 40 mil width
0.1U_0402_16V4Z
23 44 1 R576 2 +3V_LAN
GPO VDDSR
1

24 45 GIGA@ 0_0603_5%
R204 NC VDDSR
1K_0402_5% 7 29 +3V_LAN 1 R577 2 +LAN_VDD12
GND VDD33

22U_0805_6.3V6M
0.1U_0402_16V4Z
14 37 1 1 100@ 0_0603_5%
GND VDD33
31
2

ISOLATEB GND C245 C244

47 GND AVDD33 1
40 2 R181 1 GIGA@
AVDD33 GIGA@ 0_0402_5% 2 2
22 EGND ENSR 43

R205 +3V_LAN
2
15K_0402_5% RTL8111DL-VB-GR_LQFP48_7X7 C242
GIGA@ Close to pin.

2
0.1U_0402_16V4Z
1 GIGA@ R180
Y3 0_0402_5%
U24
LAN_XTALI 1 2 LAN_XTALO GIGA@ For RTL8111DL pin43:

1
pull hi if switching regulator is enable.

2
1 25MHZ_20P 1 pull low if external power 1.2Vis used.
C612 C611 R179
RTL8103EL-VB-GR 0_0402_5% For RTL8103EL is NC.
30P_0402_50V8J 30P_0402_50V8J 100@
2 2 @

1
2 2

The trace length L69 to 8111DL's pin<200mils.

60 mil width L69 to C238/C239<200mils. Close to U24 pin19
GIGA@ L12
VCTRL12 1 2 1 R173 2 1U_0603_10V4Z +EVDD12
S INDUC_ 4.7UH +-20% SIA4012-4R7M GIGA@ 0_0603_5%
2 2
C251 C250

22U_0805_6.3V6M

0.1U_0402_16V4Z
1 R170 2 1 1 1U_0603_10V4Z
100@ 0_0603_5%
C238 C239 1 1
60 mil width
2 2

Layout Notice : Place as close

J1 @ chip as possible.
2 1 JOPEN
1 R172 2 0.1U_0402_16V4Z +LAN_VDD12
+3V_LAN GIGA@ 0_0603_5%
+3VALW 2 2 2 2
3 Q17 C247 C248 C260 C259
D

1
+5VALW
4.7U_0805_10V4Z

AO3414_SOT23-3 0.1U_0402_16V4Z
1 1 1 1
G
2
1

C261

R219 0.1U_0402_16V4Z 0.1U_0402_16V4Z

33K_0402_5%
1 1
Close to U24 pin10,13,30,36
2

D 2
1

C267
EN_WOL# 2
<34> EN_WOL#
G 0.1U_0402_16V4Z
Q18 S 1
Security Classification Compal Secret Data Compal Electronics, Inc.
3

2N7002_SOT23-3
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTL8103EL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-5751 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 30, 2009 Sheet 29 of 51
A B C D E
 5 4 3 2 1

Close to T14

GIGA@ T16
D C133 2 1 0.01U_0402_16V7K 1 24 MCT3 R55 2 GIGA@ 1 75_0402_5% D
TCT1 MCT1
MDI3+ 2 1:1 23 MDO3+
<29> MDI3+ TD1+ MX1+

MDI3- 3 22 MDO3-
<29> MDI3- TD1- MX1-
GIGA@
C132 2 1 0.01U_0402_16V7K 4 21 MCT2 R54 2 GIGA@ 1 75_0402_5%
TCT2 MCT2
MDI2+ 5 1:1 20 MDO2+
<29> MDI2+ TD2+ MX2+

MDI2- 6 19 MDO2-
<29> MDI2- TD2- MX2-
C131 2 1 0.01U_0402_16V7K 7 18 MCT1 R53 2 1 75_0402_5%
TCT3 MCT3
MDI1+ 8 1:1 17 MDO1+
<29> MDI1+ TD3+ MX3+

MDI1- 9 16 MDO1-
<29> MDI1- TD3- MX3-
C130 2 1 0.01U_0402_16V7K 10 15 MCT0 R52 2 1 75_0402_5%
TCT4 MCT4
C MDI0+ 11 1:1 14 MDO0+ C
<29> MDI0+ TD4+ MX4+
1
C128
Place close to TCT pin
1000P_1206_2KV7K
MDI0- MDO0- 2
<29> MDI0- 12 TD4- MX4- 13

LG-2446S-1
GIGA@

T16

RJ45 Conn.
JRJ45
HH-065 10/100 <29> ACTIVITY# ACTIVITY# R178 2 1 300_0402_5% 12
100@ Amber LED-
1
+3V_LAN 11 Amber LED+ SHLD4 16
C249
@ 68P_0402_50V8K MDO3- 8 15
2 PR4- SHLD3
C70 @ MDO3+ 7 PR4+
2 1 470P_0402_50V7K
MDO1- 6 PR2-
For EMI.
MDO2- 5
B PR3- B
MDO2+ 4 PR3+
MDO1+ 3 PR2+
MDO0- 2 PR1-
SHLD2 14
MDO0+ 1 PR1+
<29> LAN_SK# LAN_SK# R574 2 1 300_0402_5% 10 13
Green LED- SHLD1
1 +3V_LAN 9 Green LED+
C609 FOX_JM36113-P2221-7F
68P_0402_50V8K ME@
2
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/03/20 Deciphered Date 2010/03/20 Title
LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5751 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 30, 2009 Sheet 30 of 51
5 4 3 2 1
 5 4 3 2 1

R430 1403@

1403:
@C508/@C324=100p
0_0402_5%

D D

+3VS +3VS +3VS +3VS +3VS +3VS +3VS

SMSC thermal sensor REMOTE1+

Close to DDR

1
2103@ 2103@ 2103@ 2103@ 1
1

1
2103@
R430
2103@
R459
R460
10K_0402_5%
R462
10K_0402_5%
R440
10K_0402_5%
placed near by VRAM R461
10K_0402_5%
R441
10K_0402_5% C508
@
2
C
Q39
68_0402_5% 6.8K_0402_5% @ 1000P_0402_50V7K B MMST3904-7-F_SOT323-3
U20 2103@ 2 E

3
1 2 REMOTE1-
2

VDD DN1 DP1

3 VDD GPIO1 4
5 6 ALERT#
GPIO2 ALERT# SMB_EC_DA2_R
7 SYS_SHDN# SMDATA 8 SMB_EC_DA2_R <14,19>
2 SMB_EC_CK2_R 9 10 TACH
<14,19> SMB_EC_CK2_R SMCLK TACH
FAN_PWM 11 12
C443 SHDN_SEL PWM GND TRIP_SET
0.1U_0402_16V4Z
13
15
SHDN_SEL TRIP_SET 14
16 REMOTE2+ REMOTE2+
Under WWAN
1 DN2 / DP3 DP2 / DN3
GPAD 17 1

1
@ C

2
REMOTE2- C324 2 Q22
EMC2103-2-AP-TR_QFN16_4X4 R439 1000P_0402_50V7K B MMST3904-7-F_SOT323-3
2 E
FAN_PWM & TACH 1.5K_0402_1%

3
@ REMOTE2-
for PWM FAN Address 0101_110xb

1
REMOTE1,2+/-:
C
internal pull up 1.2K to 1.5V Trace width/space:10/10 mil C

R for initial thermal Trace length:<8"

shutdown temp

TACH 1 @ 2
R617 0_0402_5%
Close U20 2103@ FAN_PWM 1 @ 2
REMOTE1+ REMOTE2+ 1 2 REMOTE1- R618 0_0402_5%
1 R622 0_0402_5%
1403@ 2103@
C449 REMOTE2- 1 2 REMOTE1+ 1 2 TACH_R
<34> EC_TACH
2200P_0402_50V7K R623 0_0402_5% R619 0_0402_5%
2 REMOTE1-
<34> EC_FAN_PWM 1 2 FAN_PWM_R
R620 0_0402_5%

REMOTE2+
+3VS
1
C651

1
B 2200P_0402_50V7K B
2 REMOTE2- R624
10K_0402_5%
@
U29 1403@

2
VDD 1 10 SMB_EC_CK2_R
VDD SMCLK
REMOTE1+ 2 DP1 SMDATA 9 SMB_EC_DA2_R FAN1 Conn
REMOTE1- 3 8 ALERT#
DN1 ALERT#
Shutdown TRIP_SET REMOTE2+ 4 7 +5VS
DP2 THERM#
Temp R439 (1%) REMOTE2- JP12
5 DN2 GND 6
93 953ohm TACH_R
1
2
1
FAN_PWM_R 2
94 1020ohm EMC1403-2-AIZL-TR_MSOP10
3
4
3
4
95 1100ohm 2 5
6
G5
Address 1001_101xb C490 G6
96 1150ohm 10U_0805_10V4Z ACES_85205-04001
1 ME@
97 1240ohm
98 1330ohm
A 99 1400ohm A

100 1500ohm
101 1580ohm
102 1690ohm Security Classification Compal Secret Data Compal Electronics,Ltd.
103 1820ohm Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
EMC2103/1403_Thermal sensor/FAN
104 1960ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
105 2050ohm DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 31 of 51
5 4 3 2 1
 A B C D E F G H

1 1

SATA HDD Conn.

JHDD1
2 2
1 GND
SATA_ITX_DRX_P0 2
<13> SATA_ITX_DRX_P0
<13> SATA_ITX_DRX_N0
SATA_ITX_DRX_N0 3
A+
A-
SATA ODD Conn.
4 GND
SATA_DTX_C_IRX_N0 C434 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N0 5
<13> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 C433 1 SATA_DTX_IRX_P0 B-
2 0.01U_0402_16V7K 6
<13> SATA_DTX_C_IRX_P0 B+ JODD1
7 GND
1 GND
SATA_ITX_DRX_P1 2
<13> SATA_ITX_DRX_P1 A+
8 SATA_ITX_DRX_N1 3
VCC3.3 <13> SATA_ITX_DRX_N1 A-
+3VS 9 4
VCC3.3 SATA_DTX_C_IRX_N1 C426 1 SATA_DTX_IRX_N1 GND
10 VCC3.3 2 0.01U_0402_16V7K 5 B-
<13> SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 C425 1 SATA_DTX_IRX_P1
11 2 0.01U_0402_16V7K 6
GND <13> SATA_DTX_C_IRX_P1 B+
12 7
GND GND
13
GND R380
14
VCC5
+5VS 15 +3VS 1 2 8
VCC5 @ 10K_0402_5% DP
16 +5V_ODD 9
VCC5 +5V
17 GND 10 +5V GND 17
18 ODD_Power_ON# 1 @ 2 11 16
RESERVED <34> ODD_Power_ON# R379 0_0402_5% MD GND
19 12
GND GND
20 13
+5VS +3VS VCC12 GND
21
VCC12
22
VCC12 OCTEK_SLS-13SB1G_RV
1 1 1 1 1 1 ME@
@ SUYIN_127043FB022G208ZR_RV
C125 C126 C124 C123 C122 C121 ME@
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2

3
ODD Power Control 3

J6
1 1 2 2

@
JUMP_43X79 +5V_ODD
+5VS Q37

D
3 1
1

1
@ AO3413_SOT23-3
@ C424

G
2
R378 0.1U_0402_16V4Z
10K_0402_5% 2
1

2
C423
0.01U_0402_16V7K @
1 2 C431

1
10U_0805_10V4Z
@ 2

OUT
<34> ODD_OFF# 2
IN

GND
@
Q36
DTC124EKAT146_SC59-3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 32 of 51
A B C D E F G H
 5 4 3 2 1

CX20671
High Definition Audio Codec SoC HDA_RST_CODEC#
With Integrated Class-D Stereo
HDA_SYNC_CODEC
EMI
Amplifier.
HDA_SDOUT_CODEC
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO). 1
33_0402_5%
2
R331
HDA_BITCLK_CODEC

An integrated 3.3 V to 1.8V Low-dropout

1 1 1 1
voltage regulator (LDO).

C375

C376

C378

C370
22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
2 2 2 2
D D
@ @ @

+3VS

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1

C407

C400

C408
+LDO_OUT_3.3V
+3VS 2 1 +VAUX_3.3
0_0402_5% R339 2 2 2

1U_0603_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
+3VALW 2 @ 1 1 1 1 1 AVDD_3.3 pinis output of

10U_0805_10V4Z

0.1U_0402_16V4Z
0_0402_5% R337

C414

C412

C410

C409
1 1 internal LDO. NOT connect
To support Wake-on-Jack or Wake-on-Ring, the CODEC

C381

C380
VAUX_3.3 & VDD_IO pins must be powerd by a rail that to external supply.
is not removed unless AC power is removed. 2 2 2 2
*DSH page42 has more detail. 2 2

Layout Note:Path from +5VS to LPWR_5.0

RPWR_5.0 must be very low
+1.5V 0_0402_5% 2 @ 1 R330
resistance (<0.01 ohms)
+3VS 2 1 +5VS

1U_0603_10V4Z

0.1U_0402_16V4Z
0_0402_5% R328 1 1 10K only needed if supply to VAUX_3.3
@

C369

C377
+3VALW 2 1 is removed during system re-start. 1 R348 2 +5VS

10U_0805_10V4Z

0.1U_0402_16V4Z
0_0402_5% R329 1 1

C413

C411
0.1_1206_1%

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2 2
1 1 1 1

C391

C392

C390

C399
10U_0805_10V4Z

0.1U_0402_16V4Z
1
2 2

10K_0402_5%
1 1

C371

C379
R332 2 2 2 2

0.1U_0402_16V4Z
2 2

18

29

27
28
26
C 1 C

3
7
2
U17

C393
FILT_1.8

VAUX_3.3
DVDD_3.3

FILT_1.65

AVDD_3.3
VDD_IO

AVDD_5V
AVDD_HP
Please bypass caps very close to device.
12 2
LPWR_5.0
15
HDA_RST_CODEC# RPWR_5.0
<13> HDA_RST_CODEC# 9 17
RESET# CLASS-D_REF R344 1 2 5.11K_0402_1% +VAUX_3.3
HDA_BITCLK_CODEC 5 Sense resistors must be
<13> HDA_BITCLK_CODEC BIT_CLK
HDA_SYNC_CODEC 8 36 R345 1 2 10K_0402_1% Port C
<13> HDA_SYNC_CODEC SYNC SENSE_A MIC_JD <38> connected same power
<13> HDA_SDIN1 1 R336 2 33_0402_5% 6 R346 1 2 39.2K_0402_1% PLUG_IN <38> Port A
HDA_SDOUT_CODEC 4
SDATA_IN that is used for VAUX_3.3
<13> HDA_SDOUT_CODEC SDATA_OUT
35 MIC_INR Internal MIC
PORTB_R MIC_INL
34
PORTB_L
33 +MICBIASB
PC_BEEP B_BIAS R352 2.2K_0402_5%
EAPD active low 10
PC_BEEP +MICBIASC
R351 2.2K_0402_5%
0=power down ex AMP 32 +MICBIASC
C_BIAS
1=power up ex AMP PORTC_R
31 C403 1 2 2.2U_0603_10V7K R350 100_0402_1%
EXT_MIC_R <38>
30 C415 1 2 2.2U_0603_10V7K External MIC
PORTC_L EXT_MIC_L <38>
0_0402_5% 1 2 R338 38 R356 100_0402_1%
<34> EAPD GPIO0/EAPD#
EC_MUTE# 2 1 37
<34> EC_MUTE# GPIO1/SPK_MUTE#
0_0402_5% R343 23 HP_OUTR_R R601 1 2 5.1_0402_1%
PORTA_R HP_OUTR <38>
22 HP_OUTL_R R602 1 2 5.1_0402_1% Headphone
PORTA_L HP_OUTL <38>
C416
1 2 40
0.1U_0402_16V4Z DMIC_CLK
1 24
DMIC_1/2 NC
25
C396 NC
39
SPK_L2+ NC
1 2 11
0.1U_0402_16V4Z SPK_L1- LEFT+
13
LEFT-
C395
Internal SPEAKER AVEE
21
19
SPK_R2+ FLY_P
1 2 16 20 1 2

10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z SPK_R1- RIGHT+ FLY_N C401 1U_0603_10V4Z
14 1 1
RIGHT-

C406

C404
GND

C405
B
1 2 B
0.1U_0402_16V4Z CX20671-11Z_QFN40_6X6 2 2
41

R355
1 2
0_0402_5% +MICBIASB
R354
1 2

1
0_0402_5% MIC_INR 2 1 MIC_INL
R362 R349 0_0402_5% R600
1 2 4.7K_0402_5%
0_0402_5%
J7

2
1 2 MIC1
1 C394 1 2 2.2U_0603_10V7K MIC_INR
SHORT PADS 2 GNDA
GND GNDA C402 1 2 2.2U_0603_10V7K MIC_INL
WM-64PCY_2P
45@ @

+3VS
PC Beep
1

R325
10K_0402_1%
2

2 1C368
wide 20MIL
1

1U_0603_10V4Z
JSPK1
R326 SPK_R1- L19 1 2 FBMA-L11-160808-121LMA30T SPK_R1-_CONN 1
10K_0402_1% SPK_R2+ L20 FBMA-L11-160808-121LMA30T SPK_R2+_CONN 1
1 2 2
C374 1U_0603_10V4Z SPK_L1- L22 FBMA-L11-160808-121LMA30T SPK_L1-_CONN 2
1 2 3
2

3
1 2PC_BEEP1 2 1 PC_BEEP SPK_L2+ L23 1 2 FBMA-L11-160808-121LMA30T SPK_L2+_CONN 4
R327 20K_0402_5% 4
5
GND1
EC Beep 6

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
GND2
1

A C351 R310 C 1 1 1 1 A
2

Q30

C632

C633

C634

C635
<34> BEEP# 2 1 1 2 2 ACES_88231-04001
1 B 2SC2411KT146_SOT23-3 R335 ME@
560_0402_5% E 20K_0402_5%
3

C345 1U_0603_10V4Z 2 2 2 2
@ 0.1U_0402_16V4Z @
1

C352
R311
<13> PCH_SPKR 2 1 1 2
Security Classification Compal Secret Data Compal Electronics,Ltd.
1

1U_0603_10V4Z 560_0402_5%
ICH Beep D15 @ 2008/03/25 2008/04/ Title
R309 Issued Date Deciphered Date
10K_0402_5%
RB751V_SOD323
CX20671 Codec
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2

C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 33 of 51
5 4 3 2 1
 +3VALW
+EC_AVCC
1 1 1 1 1 1

0.1U_0402_16V4Z
C290

0.1U_0402_16V4Z
C319

0.1U_0402_16V4Z
C339

0.1U_0402_16V4Z
C329

1000P_0402_50V7K
C341

1000P_0402_50V7K
C327
L14 1 2
+3VALW +EC_AVCC
FBM-11-160808-601-T_0603 2 1
C293 2 2 2 2 2 2
0.1U_0402_16V4Z C294

111
125
1000P_0402_50V7K

22
33
96

67
9
1 2 1 ECAGND 2 U13
L13 FBM-11-160808-601-T_0603

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
R613
1 2 +3VS
1 21 INVT_PWM 10K_0402_5%
<16> GATEA20 KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP# INVT_PWM <27>
2 23 @
<16> KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# <33>
3 26 EC_FAN_PWM FAN control by EC 09.09.08
<13> SERIRQ SERIRQ# FANPWM1/GPIO12 ACOFF EC_FAN_PWM <31>
<13,28> LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF <40,42>
LPC_AD3 5
<13,28> LPC_AD3 LAD3
LPC_AD2 7 PWM Output
<13,28> LPC_AD2 LPC_AD1 LAD2 BATT_TEMP
<13,28> LPC_AD1 8 63 BATT_TEMP <41>
LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_OVP
LAD0 LPC & MISC
<13,28> LPC_AD0 10 64 BATT_OVP <42>
BATT_OVP/AD1/GPIO39
2 1 2 1 65 ADP_I <42>
ADP_I/AD2/GPIO3A
<38> changed 09.09.08
@ C340 22P_0402_50V8J @ R289 10_0402_5% 12 AD Input 66
<16> CLK_PCI_LPC PCICLK AD3/GPIO3B NOVO#
13 75 PCH_TEMP_ALERT# PCH_TEMP_ALERT# <16> changed 09.09.08
<16,28> PCI_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 ODD_Power_ON#
+3VALW 1 2 37 ECRST# SELIO2#/AD5/GPIO43 76 ODD_Power_ON# <32>
R266 47K_0402_5% EC_SCI# +5VS
<16> EC_SCI# 20
EC_ID SCI#/GPIO0E
2 38
+3VALW CLKRUN#/GPIO1D DAC_BRIG TP_CLK R236 1
68 DAC_BRIG <27> 2 4.7K_0402_5%
C323 R614 DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D 70
0.1U_0402_16V4Z 1 @ 2 EC_ID DA Output 71 IREF TP_DATA R235 1 2 4.7K_0402_5%
1 KSI0 IREF/DA2/GPIO3E IREF <42>
4.7K_0402_5% 55 72 +3VALW
KSI1 KSI0/GPIO30 DA3/GPIO3F CHGVADJ <42> BATT_OVP
R615 56 +3VALW 1 2
@ KSI2 KSI1/GPIO31 EC_MUTE# R238 1 10K_0402_5% C297 100P_0402_50V8J
1 2 57 KSI2/GPIO32 2
4.7K_0402_5% KSI3 58 83 BATT_TEMP 1 2
<35> KSI3 KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# <33>
KSI4 59 84 USB_ON# USB_ON# R237 1 2 10K_0402_5% C298 100P_0402_50V8J
<35> KSI4 KSI5 KSI4/GPIO34 PSDAT1/GPIO4B USB_ON# <37> ACIN
EC_ID to identify KB926 D or E 60
KSI5/GPIO35 PSCLK2/GPIO4C
85 ME_FLASH <13> 1 2
KSI6 61 PS2 Interface 86 +3VALW C328 100P_0402_50V8J
KSO[0..15] KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK SUS_PWR_DN_ACK <15>
62 87 TP_CLK <35>
<35> KSO[0..15] KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA <35>
KSI[0..7] KSO1 40 1 2 4.7K_0402_5%
<35> KSI[0..7] KSO2 KSO1/GPIO21 R607
41
KSO3 KSO2/GPIO22 R234 1
42 KSO3/GPIO23 SDICS#/GPXOA00 97 2 @ 4.7K_0402_5%
KSO4 43 98 KB926 SPI STRAP PIN
KSO5 KSO4/GPIO24 SDICLK/GPXOA01 EN_WOL# <29>
+3VALW
KSO5/GPIO25 Int. K/B
44 99 BATT_SEL_EC <42>
KSO6 SDIDO/GPXOA02
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 CMOS_OFF# <27>
KSO7 46 SPI Device Interface
KSO7/GPIO27
R265 1 2 47K_0402_5% KSO1 KSO8 47 KSO8/GPIO28
+3VS
KSO9 48 119 FRD#SPI_SO
KSO9/GPIO29 SPIDI/RD# FRD#SPI_SO <36>
R263 1 2 47K_0402_5% KSO2 KSO10 49 KSO10/GPIO2A SPIDO/WR# 120 FWR#SPI_SI
FWR#SPI_SI <36>

1
KSO11 50 SPI Flash ROM 126 SPI_CLK
KSO12 KSO11/GPIO2B SPICLK/GPIO58 FSEL#SPICS# SPI_CLK <36>
ENE UPDATE 08/10/21 KSO13
51
52
KSO12/GPIO2C
KSO13/GPIO2D
SPICS#
128 FSEL#SPICS# <36>
R241
KSO14 53 10K_0402_5%
KSO15 KSO14/GPIO2E PM_BTN#
54 73

2
KSO15/GPIO2F CIR_RX/GPIO40 PM_BTN# <38>
81 74 I2C_INT I2C_INT
+3VS KSO16/GPIO48 CIR_RLC_TX/GPIO41 I2C_INT <38>
82 89 FSTCHG <42>
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 CHARGE_LED0#
90 CHARGE_LED0# <36>
+3VALW BATT_CHGI_LED#/GPIO52 CAPS_LED#
91 CAPS_LED# <35>
EC_SMB_CK1 CAPS_LED#/GPIO53 CHARGE_LED1#
<41> EC_SMB_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 CHARGE_LED1# <36>
2

EC_SMB_DA1 78 93
<41> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED# <36>
2

EC_SMB_CK2 79 SM Bus 95 SYSON

<14> EC_SMB_CK2 EC_SMB_DA2 SCL2/GPIO46 SYSON/GPIO56 SYSON <28,39,44>
R611 R292 80 121
<14> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 ACIN VR_ON <48>
10K_0402_5% 10K_0402_5% 127
AC_IN/GPIO59 ACIN <40>
1

EC_TACH 6 100
<15> SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_LID_OUT# EC_RSMRST# <15>
<15> SLP_S5# 14 101 EC_LID_OUT# <14>
EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON @
<16> EC_SMI# 15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 EC_ON <38>
1 2 LID_SW# 16 103 ODD_OFF# D11 RB751V_SOD323
<29> LAN_WAKE# <35> LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06 ODD_OFF# <32>
R293 0_0402_5% ESB_CLK 17 104 ICH_POK_EC 1 2 ICH_POK
<38> ESB_CLK ESB_DAT SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# ICH_POK <15>
<38> ESB_DAT 18
PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08
105 BKOFF# <27>
1 2 EC_PME# 19 GPIO 106 1 2 1 2
EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# <28> +3VS
R303 @ 0_0402_5% 25 107 R258 0_0402_5% 10K_0402_5%
EC_THERM#/GPIO11 GPXO10 AC_PRESENT <15>
EC_TACH<35> KILL_SW#
28 108 RST# R251 @
<31> EC_TACH FAN_SPEED1/FANFB1/GPIO14 GPXO11 RST# <38>
S

3 1 <28> 3G_OFF# 29 FANFB2/GPIO15

<16> PCI_PME# EC_TX_P80_DATA
<28,35> EC_TX_P80_DATA 30
EC_TX/GPIO16
@ Q26
<28,35> EC_RX_P80_CLK
EC_RX_P80_CLK 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 SLP_S4# <15>
6
G

2N7002_SOT23 32 112
2

<38> ON/OFF# H_PROCHOT# ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL <27>

+3VALW 34 114 EAPD <33>
<5,48> H_PROCHOT# PWR_LED#/GPIO19 GPXID3
changed 09.09.08 <35> NUM_LED# 36
NUMLED#/GPIO1A GPI GPXID4
115 DRAMRST_CNTRL_EC <5>
116 SUSP#
GPXID5 PBTN_OUT# SUSP# <16,28,39,42,44,46>
1 100P_0402_50V8J
2 117 PBTN_OUT# <15>
C652 GPXID6
118 BT_OFF# <37>
@ XCLKI GPXID7
122 XCLK1
+3VALW Reserve for ESD. XCLKO 123
XCLK0 V18R
124
1
AGND

1 2 FRD#SPI_SO SUSP#
GND
GND
GND
GND
GND

R262 @ 100K_0402_1% C320 1

+3VS 4.7U_0805_10V4Z @
1 2 FSEL#SPICS# R291 KB926QFA1_LQFP128 2 C318
11
24
35
94
113

69

R271 @ 100K_0402_1% 1 2 ESB_CLK 1000P_0402_50V7K

4.7K_0402_5% 2
ECAGND

R294
1 2 ESB_DAT
4.7K_0402_5%

+3VALW needed to update to D3 version

R240
1 2 EC_SMB_CK1 SA00001J580
4.7K_0402_5%
R239
1 2 EC_SMB_DA1
4.7K_0402_5%

+3VS

1 2
C322 15P_0402_50V8J
R226 R227 XCLKO
2.2K_0402_5% 2.2K_0402_5%
1

@ @ 32.768KHZ_12.5PF_1TJS125DJ4A420P
3 NC @
EC_SMB_CK2 OUT 4 R264
EC_SMB_DA2 2 1 20M_0603_5%
NC IN
1 1
2

@ @ XCLKI
C291
100P_0402_50V8J
C292
100P_0402_50V8J
X2 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2
1 2 Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
C321 15P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 34 of 51
 5 4 3 2 1

JP5
KSI1 1
KSI7 1
2
INT_KBD Conn. KSI6
KSO9
3
2
3 EC DEBUG PORT
4 4
KSI[0..7] KSI4 5
KSI[0..7] <34> 5
KSI5 6
KSO[0..15] KSO0 6
D KSO[0..15] <34> 7 7 D
KSI2 8
KSI3 8 JP11
9 9
KSO5 10 +3VALW 1
KSO2 C203 1 10 1
2 @ 100P_0402_50V8J KSO1 C205 1 2 @ 100P_0402_50V8J KSO1 11 11 <28,34> EC_TX_P80_DATA
EC_TX_P80_DATA 2 2
KSI0 12 EC_RX_P80_CLK 3
12 <28,34> EC_RX_P80_CLK 3
KSO15 C153 1 2 @ 100P_0402_50V8J KSO7 C186 1 2 @ 100P_0402_50V8J KSO2 13 4
KSO4 13 4
14 14
KSO6 C175 1 2 @ 100P_0402_50V8J KSI2 C226 1 2 @ 100P_0402_50V8J KSO7 15 ACES_85205-0400
KSO8 15
16 16 ME@
KSO8 C185 1 2 @ 100P_0402_50V8J KSO5 C206 1 2 @ 100P_0402_50V8J KSO6 17
KSO3 17
18 18
KSO13 C172 1 2 @ 100P_0402_50V8J KSI3 C225 1 2 @ 100P_0402_50V8J KSO12 19
KSO13 19
20 20
KSO12 C173 1 2 @ 100P_0402_50V8J KSO14 C156 1 2 @ 100P_0402_50V8J KSO14 21
KSO11 21
22 22
KSO11 C155 1 2 @ 100P_0402_50V8J KSI7 C236 1 2 @ 100P_0402_50V8J +5VS KSO10 23
KSO15 23
24 24
KSO10 C154 1 2 @ 100P_0402_50V8J KSI6 C235 1 2 @ 100P_0402_50V8J 300_0402_5% 2 1 R130 25
300_0402_5% R129 25
2 1 26 26
KSO3 C174 1 2 @ 100P_0402_50V8J KSI5 C228 1 2 @ 100P_0402_50V8J 27

KSO4 C187 1 2 @ 100P_0402_50V8J KSI4 C233 1 2 @ 100P_0402_50V8J

<34> NUM_LED#
<34> CAPS_LED# 28
29
27
28
31
Lid Switch
29 G1
30 30 G2 32
KSI0 C204 1 2 @ 100P_0402_50V8J KSO9 C234 1 2 @ 100P_0402_50V8J
PAD T5 2 2 ACES_85201-3005N
KSO0 C227 1 2 @ 100P_0402_50V8J KSI1 C241 1 2 @ 100P_0402_50V8J PAD T6 C654 ME@
C653 +3VALW 1 2 +VCC_LID R353 1 2 100K_0402_5%
100P_0402_50V8J @ 100P_0402_50V8J R347 0_0402_5%
C @ 1 1 C
CONN PIN define need double check

2
Reserve for ESD. A3212ELHLT-T_SOT23W-3

VDD
1
OUTPUT 3 LID_SW# <34>
C398
To TP/B Conn. 0.1U_0402_16V4Z 2

GND
2
+5VS C397
U18 10P_0402_50V8J

1
1

C150

0.1U_0402_16V4Z
JP4

<34> TP_CLK
TP_CLK
TP_DATA
4
3
4
3 +3VALW
Kill Switch
<34> TP_DATA 2 2 100K_0402_5% LSSM12-P-V-T-R_3P
1
@
C151
1
@
C152
1 1
2 R295 1 3 3
Kill
100P_0402_50V8J 100P_0402_50V8J E&T_6905-E04N-00R 2
STATUS
2 2 <34> KILL_SW# 2
ME@ KILL_SW# 1,2(LOW) OFF
CONN PIN define need double check 1 1 2,3(HI) ON
B B
SW2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB /SW /LPC Debug Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 35 of 51
5 4 3 2 1
 FOR EC 256KB SPI ROM
(150mil PACKAGE)
+3VALW
20mils
1

1
C265
0.1U_0402_16V4Z R217
2 10K_0402_5%
Changed to BEAD for EMI.

2
U9
<34> FSEL#SPICS#
FSEL#SPICS#
Close to EC after C1059.
1 CS# VCC 8
FRD#SPI_SO R218 1 2 15_0402_5% SPI_SO 2 7 HOLD# R215 FBMA-10-100505-101T 0402
<34> FRD#SPI_SO DO HOLD#
3 6 SPI_CLK_R 1 2 SPI_CLK
WP# CLK SPI_CLK <34>
4 5
GND DIO
MX25L2005CMI-12G SOP SPI_SI_EC 1 2 15_0402_5% FWR#SPI_SI SPI_CLK_R
FWR#SPI_SI <34>
R201

1
R216
0_0402_5%
@
Colse to EC

2
1 1
C266 C264
10P_0402_50V8J 12P_0402_50V8J
2 @ 2

EMI 3G

LED 1
FD1
1
FD4
1
FD2
1
FD3

LED1
White
1 2 2 1
A:H_2P8
<34> PWR_LED# +5VALW
300_0402_5% R357
H24 H1 H11 H15 H2 H12
19-213A-T1D-CP2Q2HY-3T_WHITE HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

Orange LED2

1
BATT_LOW_LED# 1 2 2 1
<34> CHARGE_LED1# +3VALW
O 300_0402_5% R358
H22 H18 H5
<34> CHARGE_LED0# 3 4 2 1 +5VALW HOLEA HOLEA HOLEA
W 300_0402_5% R359
BATT_CHG_LED#
White
18-225A-S2T3D-C01-3T_ORG-WHITE

1
D17 LED3 I:H_3P0 X1
White
<28> WLAN_LED# 1 2 1 2 2 1 +5VS H3
300_0402_5% R360 C:H_3P8 HOLEA
RB751V_SOD323
19-213A-T1D-CP2Q2HY-3T_WHITE H6 H7 H9 H14 H4
D16
HOLEA HOLEA HOLEA HOLEA HOLEA

1
<37> BT_LED# 1 2

RB751V_SOD323

1
LED4
J:H_2P8 X1
White H23
HOLEA
<13> HDD_LED# 1 2 2
300_0402_5%
1
R361
+5VS D:H_3P8 X2
H13 H10
19-213A-T1D-CP2Q2HY-3T_WHITE HOLEA HOLEA

1
1

1
H20 H16
HOLEA HOLEA
H_4P5X3P0N H_6P0N
G:H_3P2 X2 H19 H8
HOLEA HOLEA
H17

1
HOLEA

1
1
H_3P0X4P0N
H21
HOLEA

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED/EC SPI ROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 36 of 51
 A B C D E

+5VALW Right USB Conn.

+USB_VCCA
W=80mils JUSB1
+USB_VCCA +USB_VCCA 1
1 1
U19 1 USB20_N3 2
+ <16> USB20_N3 2
1 GND OUT 8 RIGHT USB PORT X1 C430
<16> USB20_P3
USB20_P3 3 3
C421 0.1U_0402_16V4Z 2 7 C432 4
IN OUT 150U_B2_6.3VM_R35M 470P_0402_50V7K 4
2 1 3 IN OUT 6 5 G5
USB_ON# 4 5 2 2 6
<34> USB_ON# EN OC# USB_OC#1 <16> G6
1 APL3510BKI_SO8 ACES_85205-04001 1
ME@
1
C429
@ 1000P_0402_50V7K
2
Left USB Conn.
+USB_VCCB
W=80mils JUSB2
1 1
USB20_N0 2
<16> USB20_N0 2
U19/U27 USB power switch need update symbol 1 <16> USB20_P0
USB20_P0 3 3
to SA000039E00(Low enable) 4 4
C237 5 GND

2
PJDLC05_SOT23-3
470P_0402_50V7K 6
2 D7 GND
7 GND
@ 8 GND
SUYIN_020173MR004S558ZL
ME@
+5VALW ESATA and USB Conn.

1
+USB_VCCB

+USB_VCCB W=80mils
E-SATA COMBO +USB_VCCB
U27 1
1 8
LEFT USB PORT
2 GND OUT 1 2
C621 0.1U_0402_16V4Z 2 7 C615 + C622 JESAT1
IN OUT 470P_0402_50V7K USB
2 1 3 IN OUT 6 1 VBUS
USB_ON# 4 5 150U_B2_6.3VM_R35M USB20_N1 2
<34> USB_ON# EN
APL3510BKI _SO8
OC# USB_OC#0 <16> 2 2 <16> USB20_N1
<16> USB20_P1
USB20_P1 3
4
D-
D+
USB
5
GND
A+ = RXP
1 GND
C610 SATA_ITX_DRX_P4_CONN 6
@ 1000P_0402_50V7K
<13> SATA_ITX_DRX_P4_CONN
<13> SATA_ITX_DRX_N4_CONN SATA_ITX_DRX_N4_CONN 7
8
A+ ESATA
A-
A- = RXN
2 SATA_DTX_C_IRX_N4 0.01U_0402_16V7K 2 GND
<13> SATA_DTX_C_IRX_N4 1 C624 SATA_DTX_IRX_N4 9 B-
USB20_N1 SATA_DTX_C_IRX_P4 ESATA@ 2 1 C623 SATA_DTX_IRX_P4 10
<13> SATA_DTX_C_IRX_P4 0.01U_0402_16V7K B+
11 GND
USB20_P1 ESATA@
12 GND
B- = TXN
3

2
PJDLC05_SOT23-3

13 GND
D10 14
@ 15
GND
GND
B+ = TXP
+5VALW TYCO_1759576-1
ME@
BT MODULE CONN

1
BT@
1

R304 BT@
100K_0402_5%
C353
3 0.1U_0402_16V4Z 3
2 1 R616 2 1 2
100K_0402_5%
1
BT@
OUT

2 BT@ +3VS Q32 +3VS_BT

<34> BT_OFF# IN Q31 30mils
GND

D
DTC124EKAT146_SC59-3 3 1
1
BT@ 0.1U_0402_16V4Z
3

C354

G
2
AO3413_SOT23-3 BT@
BT@ 2
<36> BT_LED#
Q29 JP7
1

DTC124EKAT146_SC59-3 1 1
2
OUT

USB20_P11 2
<16> USB20_P11 3 3
<16> USB20_N11 USB20_N11 4
BTON_LED 4
IN 2 5 5 G1 7
<28> BT_ACTIVE BT_ACTIVE 6 8
GND

6 G2
ACES_87213-0600G
ME@
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB ports/BT/E-SATA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 37 of 51
A B C D E
 ON/OFF switchSW1 @ Power Bottom Board Conn. 4pin Cap Sensor Board Conn. 6pin
1 3
Power Button 2 4 ENE SB3534
SMT1-05_4P

6
5
+3VALW

TOP Side J5

2
1 2
JP3
SHORT PADS R272 NOVO_BTN# 1 JP1
Bottom Side 100K_0402_5% ON/OFFBTN# 2
1
1
D14 2 1
PM_BTN# 3 R3 1 2 0_0402_5% I2C_INT_R 2
<34> PM_BTN# <34> I2C_INT

1
ON/OFF# 3 R2 2
3 ON/OFF# <34> 4 4 <34> ESB_DAT 1 2 0_0402_5% 3 3
ON/OFFBTN# 1 R1 1 2 0_0402_5% 4
<34> ESB_CLK 4
2 51_ON# 5
51_ON# <40> E&T_6905-E04N-00R <34> RST# 5
+3VS 6 6
DAN202UT106_SC70-3 ME@ 7 7
+5VS 8 8
9 GND
2 2 10 GND
@ @
C1 C2 ACES_85201-08051
33P_0402_50V8J 33P_0402_50V8J ME@
D

1
1 1
EC_ON 2
<34> EC_ON
G
Q28 S

3
2

2N7002_SOT23-3 +3VS
R302
10K_0402_5%

1
R603
1

100K_0402_1%

2
PM_BTN#

NOVO_BTN# ON/OFFBTN# PM_BTN#

+3VALW

2
D19 D20
2

PJSOT24C 3P C/A SOT-23 PJSOT24C 3P C/A SOT-23

R296 @ @
100K_0402_5%

1
D13
1

NOVO# 2
<34> NOVO#
1 NOVO_BTN#
51_ON# 3
<40> 51_ON#

DAN202UT106_SC70-3
EMI REQUEST 1ST = SCA00000E00
2ST = SCA00000R00

Card Reader/Audio Jack SB CONN

JP8

<33> PLUG_IN PLUG_IN 1

HP_OUTR 1
<33> HP_OUTR 2 2
HP_OUTL 3
<33> HP_OUTL 3
4 4
<33> MIC_JD MIC_JD 5
EXT_MIC_L 5
<33> EXT_MIC_L 6 6
EXT_MIC_R 7
<33> EXT_MIC_R 7
8 8
9 9
+3VALW USB20_P5 10
<16> USB20_P5 10
USB20_N5 11 13
<16> USB20_N5 11 GND
12 12 GND 14

ACES_85201-1205N

ME@

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2008/03/25 Deciphered Date 2008/04/ Title
Audio Jack & SW connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Friday, October 30, 2009 Sheet 38 of 51
 A B C D E

+5VALW TO +5VS +3VALW TO +3VS +1.5V to +1.5VS

+1.5V +1.5VS
U16
+5VALW +5VS +3VALW +3VS 8 D
U4 S 1
U10 7 D
1 S 2 1 1

1
8 D S 1 8 D S 1 6 D S 3
7 2 7 D C389 C362 C363
1 D S 1 1 1 S 2 1 1 5
10U_0805_10V4Z D G 4

1
6 3 6 D 10U_0805_10V4Z 1U_0603_10V4Z R314
C279 D S C277 C276 C127 S 3 C134 C135 2 2
SI4800BDY-T1-E3_SO8 2 470_0603_5%
5 D G 4 5 D G 4
10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R202 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R87 @

2
1 2 2 2 2 2 2 1
SI4800BDY-T1-E3_SO8 470_0603_5% SI4800BDY-T1-E3_SO8 470_0603_5%
@ @

1 2

1 2

1
B+ B+ B+ D
D D
2 SUSP
2 SUSP 2 SUSP G

1
G G S Q34

3
S Q16 S Q6 2N7002_SOT23

3
R229 2N7002_SOT23 R89 2N7002_SOT23 100K_0402_5% @
20K_0402_5% @ 47K_0402_5% @ R312

2
5VS_GATE2 R228 15VS_GATE_R 1.5VS_GATE

2
10K_0402_5% 1 1 Q33 1 1
1

1
D D R88 D R313
SUSP 2 Q20 C278 SUSP 2 Q9 0_0402_5% C144 SUSP 2 0_0402_5% C373 C361
G 2N7002_SOT23 0.1U_0603_25V7K G 2N7002_SOT23 0.1U_0603_25V7K G DIS@ 0.1U_0603_25V7K
S 2 S @ 2 2N7002_SOT23S @ 2 2
3

1
0.1U_0603_25V7K

+1.8VS +1.5V +VCCP +0.75VS +1.05VS

2 2
1

1
R142 R342 R174 R568 R143
470_0603_5% 470_0603_5% 470_0603_5% 22_0603_5% 470_0603_5%
@ @ @ @
1 2

1 2

1 2

1 2

1 2
D D D D D
2 SUSP 2 SYSON# 2 SUSP 2 SUSP 2 SUSP
G G G G G
S Q10 S Q35 S Q15 S Q40 S Q11
3

3
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23
@ @ @ @

For Intel S3 Power Reduction.

3 RTCVREF +5VALW 3
+5VALW
1

@
R4 R5 @
100K_0402_5% 100K_0402_5% R6
100K_0402_5%
2

SUSP
<8,44,45> SUSP
2

SYSON#
Q1 Q2
1

DTC124EKAT146_SC59-3 DTC124EKAT146_SC59-3
@
OUT

OUT

2 SYSON 2
<16,28,34,42,44,46> SUSP# IN <28,34,44> SYSON IN
GND

GND
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5751
Date: Thursday, October 29, 2009 Sheet 39 of 51
A B C D E
 A B C D

ACIN BATT ONLY

Precharge detector Precharge detector
DC030006J00 VIN
Min. typ. Max. Min. typ. Max.
PF1 PL2 L-->H 14.991V 15.381V 15.782V L-->H 7.196V 7.349V 7.505V
7A_24VDC_429007.WRML SMB3025500YA_2P
4 APDIN 1 2 APDIN1 1 2
H-->L 13.860V 14.247V 14.621V H-->L 6.138V 6.214V 6.056V
4

3 3

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
0.1U_0603_25V7K

0.1U_0603_25V7K
1
2 2 1

PR142

1
1 1K_1206_5%
1 PQ26
1 2

PC7
TP0610K-T1-E3_SOT23-3

2
@ 4602-Q04C-09R 4P P2.5

PC8

PC9

PC6

PC5
PC10
PR38
JDCIN 1K_1206_5%
VIN 2 1 1 2 3 1

PD13 PR31
RLS4148_LL34-2 1K_1206_5%
1 2

100K_0402_1%
1

1
100K_0402_1%
PR143

PR138

2
Vin Detector

2
Min. typ. Max.
L-->H 17.430V 17.901V 18.384V

100K_0402_1%
H-->L 16.976V 17.262V 17.728V

PR39
1
PR26
1M_0402_1%

1 2
1 2
VINDE-2 VIN 2
VS <34,42> ACOFF PQ11
VIN
2
DTC115EUA_SC70-3 2
0.01U_0402_25V7K
B+

10K_0805_5%
2

3
1
PQ12
1

PC97

PR21
PR134 PR18 DTC115EUA_SC70-3
84.5K_0402_1% 10K_0402_1%
2

3
1 2

2
PR27 ACIN <34>
2

22K_0402_1%
VINDE-1 1 2 3
P

+ PACIN PR25
1000P_0603_50V7K

O 1 PACIN <42>
VINDE-3 2 -
VL 2.2M_0402_5%
G
1

20K_0402_1%

10K_0402_5%
PU10A
0.1U_0402_16V7K

2 1
1

1
LM393DG_SO8
4
PC14

PR135

PC13

PR19
PD9
2

LLZ4V3B_LL34-2

499K_0402_1%
2

1
PR20 VS
2

PR22
10K_0402_5%

0.01U_0402_25V7K
100K_0402_1%
2 1 RTCVREF 3.3V

1
PR137

PC99

2
2
PD10

8
RB715F_SOT323-3
<41,43> MAINPWON 2 5

P
+
VIN 1 7 O

205K_0402_1%

499K_0402_1%
<42> ACON

0.01U_0402_25V7K
3 - 6

1
PU10B

1
PR23

PR24

PC12
LM393DG_SO8

1000P_0402_50V7K
4
2

1
3 3

PC11
PD2

0.1U_0603_25V7K

2
LL4148_LL34-2

PRG++ 2

2
1

PC98
PD12
1

LL4148_LL34-2 51ON-1

2
BATT+ 2 1
1

PQ3
PR141 PR140 PR17 SSM3K7002F_SC59-3 PR136

1
PQ4 68_1206_5% 68_1206_5% 10K_0402_5% D 47K_0402_5%
TP0610K-T1-E3_SOT23-3 2 1 2 2 1
PR122 RTCVREF G PACIN <42>
2

1
200_0603_5% S

3
CHGRTCP 1 2 51ON-2 3 1
VS
0.22U_0603_25V7K
1

2 +5VALW
2

1
PC4

PR15 PC16
100K_0402_1% 0.1U_0603_25V7K
1

PR16 PQ25
2

3
22K_0402_1% DTC115EUA_SC70-3
1 2 51ON-3
<38> 51_ON# - JRTC +
2 1 +RTCBATT

RTCVREF PD8
1

@ MAXEL_ML1220T10 1 2
PR123 +CHGRTC
+CHGRTC PU8 200_0603_5% RB751V-40_SOD323-2
4
PR125 PR124 G920AT24U_SOT89-3 4

560_0603_5% 560_0603_5% 3.3V

RTC Battery
2

1 2RTCVREF-1
1 2 3 OUT IN 2CHGRTCIN
1

GND PC90
PC91 1U_0805_25V6K
10U_0603_6.3V6M 1
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2009/01/06 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 30, 2009 Sheet 40 of 51
A B C D
 A B C D

1 1

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
VMB2 VMB Recovery at 56 degree C
PF2 PL3 VS
JBATT 12A_65V_451012MRL SMB3025500YA_2P
VL

0.01U_0402_25V7K
1 1 1 2 1 2 BATT+
2 VL
2 EC_SMCA
3 3

PC62
2
4 EC_SMDA 2

2
5 5

1
6 PR84

2
6
1

1
7 PC110 PC109 47K_0402_1%
7 0.01U_0402_25V7K
100_0402_1%

100_0402_1%

8 1000P_0402_50V7K PR83
MAINPWON <40,43>

2
GND PH1 47K_0402_1%
9

1
GND 100K_0402_1%_TSM0B104F4251RZ TM-2 1 2
PR4

PR3

TYCO_1775789-1
2

2
@ PR87

8
13.7K_0402_1%

1
TM-1 D
1 2 3

P
+ TM-3 PQ20
O 1 2
TM_REF1 2 G SSM3K7002FU_SC70-3
-

G
PU4A S

3
LM393DG_SO8

4
EC_SMB_CK1 <34>

1000P_0402_50V7K
15.4K_0402_1%
1
0.22U_0603_25V7K
1

1
PR88
EC_SMB_DA1 <34> 2 1 VL

PC63

PC64
PR85

1
1 2 +3VALW 100K_0402_1%

2
PR6
6.49K_0402_1% PR86
100K_0402_1%

8
2
1 2 A/D 5

P
BATT_TEMP <34> +
PR5 7
10K_0402_5% O
6 -

G
PU4B
LM393DG_SO8

4
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 29, 2009 Sheet 41 of 51
A B C D
 5 4 3 2 1

P3
B+
P2
PQ27 PQ6
FDS6675BZ_SO8 FDS6675BZ_SO8
PR152
VIN 8
7
1
2
1
2
8
7 0.02_1206_1% CHG_B+
6 3 3 6 PJ11
PQ34
5 5 1 4 2 2 1 1
FDS6675BZ_SO8

470P_0603_50V8J
2 3 @ JUMP_43X118 1 8

1
47K_0402_5%

2 7
1

PC15
D 3 6 D

2200P_0402_50V7K
PR145

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
5

2
DTA144EUA_SC70-3

200K_0402_1%
0.1U_0603_25V7K

PC111

4
1

PC112

PC114

PC113
CSIN
2

PC107

PR30
PQ7 CSIP

1
PR28
47K_0402_1%

2
2 1 2

2
VIN
1

2
PD15 PR155 3 ACOFF
1

RB751V-40TE17_SOD323-2 10K_0402_1% 1
1 2 6251_VDD 2
2 PR162

2.2U_0603_6.3V6K

1 1
PC128
PQ28 PR7 PD3 200K_0402_1%

1
10K_0402_1% RB715F_SOT323-3 1 2 VIN
DTC115EUA_SC70-3 2 1 PU11 PC125
<34> FSTCHG 0.1U_0603_25V7K
3

2
1 2 1 24 6251_DCIN 2 1 PQ32
VDD DCIN

1
PC132 DTC115EUA_SC70-3

100K_0402_1%
2
PQ8 0.1U_0402_16V7K
1

D 2N7002KW_SOT323-3

PR8
150K_0402_1%

2 ACSET ACPRN 23
PR29

2 PR161

SIS412DN-T1-GE3 _PAK1212-8
G 20_0402_5%

0.1U_0603_25V7K
2

3
5

1
6251_EN CSON D
S 3 22 1 2
3

EN CSON

1
PC121
PC124 2 PACIN
2

0.047U_0402_16V7K G

PQ29
CELLS 4 21 1 2 CSOP S

3
CELLS CSOP PR160 PQ5
C PC131 6800P_0402_25V7K 20_0402_5% 2N7002KW_SOT323-3 C
4
PR37 PQ9 1 2 5 20 2 1
ICOMP CSIN
1

2
3K_0402_1% D 2N7002KW_SOT323-3 PR159
PACIN 1 2 2 PC3 PR175 6.81K_0402_1% PC123 20_0402_5%
<40> PACIN
G 1 2 1 2 6 19 0.1U_0402_16V7K1 2 PL5 PR151

3
2
1
VCOMP CSIP PR158 10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1%
S
3

0.01U_0402_25V7K 1 2 2.2_0402_5% BATT+

PC130 1 2 7 18 LX_CHG 1 2 CHG
1 4
@ 100P_0402_50V8J PR174 ICM PHASE
<40> ACON

5
<34> ADP_I 100_0402_1% 2 3

SI7716ADN-T1-GE3 _PAK1212-8

1
6251_VREF DH_CHG

4.7_1206_5%
8 VREF UGATE 17
1

PR154
PQ10 PR173 1 2 PR157 PC120
DTC115EUA_SC70-3 154K_0402_1% PC1 2.2_0402_5% 0.1U_0603_25V7K

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
PQ31
2 1 0.1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1
<34> IREF CHLIM BOOT

1
PR172 4

1
PC106

PC103

PC105
ACOFF 21K_0402_1% PD14
0.01U_0402_25V7K

<34,40> ACOFF 2
6251_VREF 1 2 10 15 6251_VDDP RB751V-40TE17_SOD323-2
ACLIM VDDP
1

2
1
PC2

PR167 26251_VDD

680P_0603_50V7K
1

3
2
1
1

PC118
100K_0402_1% 11 14 DL_CHG
3

2
VADJ LGATE

1
PR2 PR163
2

31.6K_0402_1% 4.7_0402_5%
2

12 13 PC122

2
GND PGND 4.7U_0805_6.3V6K
2

ISL6251AHAZ-T_QSOP24
PR171
CHGVADJ=(Vcell-4)/0.10627 Connect to EC A/D Pin. 15.4K_0402_1%
Vcell CHGVADJ <34> CHGVADJ
1 2

B
4V 0V UMA CP mode B
1

4.2V 1.882V Vaclim=2.39*{(2.26K//514K)/((2.26K//514K)+(21K//514K))}=0.239V 6251_VDD 6251_VDD

PR1
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05) 31.6K_0402_1% VMB2
4.35V 3.2935V

2
where Vaclim=0.239V, Iinput=2.75A
PR168 PR178
2

1
@ 100K_0402_1% @ 100K_0402_1%
CC=0.25A~3A
DIS CP mode VS PR9

1
IREF=1.016*Icharge @ 340K_0402_1% CELLS
Vaclim=2.39*{(31.6K//514K)/((31.6K//514K)+(21K//514K))}=1.425V

3
IREF=0.254V~3.048V

@0.01U_0402_25V7K
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)
LI-3S :13.5V----BATT-OVP=1.5012V
VCHLIM need over 95mV where Vaclim=1.425V, Iinput=4A PR176

PC100
BATT-OVP=0.1112*VMB 0_0402_5% 2 5 2 1

1
VS PR177

2
Per cell=3.5V PR10 @ 0_0402_5%

4
@ 499K_0402_1% <34> BATT_SEL_EC
PQ2 TP0610K-T1-E3_SOT23-3 PR14

2
8

8
10_0603_5% PU1B PR139 PU1A PQ1A PQ1B
3 1 1 2 6251_DCIN @ LM358DT_SO8 5 @ 10K_0402_1% @ LM358DT_SO8 3 @ 2N7002KDW-2N_SOT363-6 @ 2N7002KDW-2N_SOT363-6
P

P
P3 7 0
+
1 2 1 0
+
<34> BATT_OVP
1
100K_0402_1%

- 6 - 2
G

@0.01U_0402_25V7K
1
PR13

1
PR11
@ 105K_0402_1%
2

PR12
2

2
PC101
2 1

2
A 100K_0402_1% A
1

PQ38
DTC115EUA_SC70-3 2 FSTCHG
2 1
FSTCHG <34>
3 SUSP# Security Classification Compal Secret Data Compal Electronics, Inc.
SUSP# <16,28,34,39,44,46> 2007/6/22 2008/6/22 Title
Issued Date Deciphered Date
PD1 CHARGER
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RB715F_SOT323-3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 29, 2009 Sheet 42 of 51

5 4 3 2 1
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
B+
PJ4 PR41
@ JUMP_43X118 0_0402_5%
2 2 1 1 1 2

330P_0402_50V7K

10U_1206_25V6M

2200P_0402_50V7K

10U_1206_25V6M

2200P_0402_50V7K
0.1U_0402_25V6

0.1U_0402_25V6
D D

1
PC21

PC38

PC26

PC39

PC36

PC37
5

PC25
1U_0603_10V6K
VL

2
2
2

PC41
PC27
PQ14 0.1U_0603_25V7K 4

4.7U_0805_6.3V6K
3/5V_VCC
1

1
3/5V_VIN
4 SIS412DN-T1-GE3_PAK1212-8

PC23
PQ13 +5VALWP

2
SIS412DN-T1-GE3_PAK1212-8

3
2
1
PL6

1
2
3
PL4 4.7UH_PCMC063T-4R7MN_5.5A_20%

7
4.7UH_PCMC063T-4R7MN_5.5A_20% PC40 2 1
1 2 1U_0603_10V6K

VIN

VCC

LDO
+3VALWP 33 19 1 2
TP PVCC

1
1

5
UG3 26 15 HG5
PR153 UGATE2 UGATE1 PR156
0_0402_5%

4.7_1206_5% BST3A-1 2 1 BST3A 24 17 BST5A2 1BST5A-1 4.7_1206_5% 1

BOOT2 BOOT1
2

PR42 PR40

15V_SNB
1

2
2

2
+
PR52

2.2_0603_5% 2.2_0603_5% PC117

@ 61.9K_0402_1%
4

13V_SNB
2
PC116 + 4 PC43 150U_B2_6.3VM_R45M

2
150U_B2_6.3VM_R45M 0.1U_0603_25V7K

1
2

PR36
SW3 25 16 SW5 PC119
1

2 PC115 PHASE2 PHASE1 PC22 680P_0402_50V7K

3
2
1
680P_0402_50V7K 0.1U_0603_25V7K

1
2
3

2
2 LG3 23 18 LG5

1
PQ30 LGATE2 LGATE1
10K_0402_1%

SI7716ADN-T1-GE3_PAK1212-8
2

PGND 22

2
C C
PR148

FB3 30 PQ33
OUT2

PR35
0_0402_5%
SI7716ADN-T1-GE3_PAK1212-8
OUT1 10
VL 32
1

@ REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 REF
PC102
0.22U_0603_25V7K 9
BYP
8 LDOREFIN
PD11 29 5V_SKIP 2 1
SKIP PR150
VL
1 2
@ 0_0402_5%
RB751V-40_SOD323-2 1 2
20 28 PR149
PR44 NC POK2 0_0402_5%
VS PD5 100K_0402_1% 2 1 2VREF_ISL6237
1 2 EN_LDO-1 1 2 EN_LDO 4 13 PR51
EN_LDO POK1 @ 0_0402_5%
2

LLZ5V1B_LL34-2
200K_0402_1%

2
PR144

PC42 3/5V_EN1 14 12 ILM1 2 1

0.22U_0603_25V7K EN1 ILIM1 PR34
301K_0402_1%
1

3/5V_EN2 27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2

NC
2 PR147
PU2 301K_0402_1%

21
B VL ISL6237IRZ-T_QFN32_5X5 B
PD4
806K_0603_1%

13/5V_NC
2

1 2 PR50

13/5V_TON
PR146

0_0402_5%
1

RB751V-40_SOD323-2 PR33 1U_0603_10V6K

PC28

@ 47K_0402_1%
2VREF_ISL6237

PR32
1

2 1 1 2
2

0_0402_5% PR43
0.047U_0402_16V7K

0.047U_0402_16V7K

MAINPWON <40,41> 0_0402_5% PJ10

1

+3VALWP 2 1 +3VALW
2

2 1
PC104

PC108

@ JUMP_43X118
2

2VREF_ISL6237

@ PJ12
+5VALWP 2 2 1 1 +5VALW
@ JUMP_43X118

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2009/01/06 2010/01/06
Issued Date Deciphered Date Title
3VALW/5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 29, 2009 Sheet 43 of 51
5 4 3 2 1
 5 4 3 2 1

PJ20
1.5V_IN 2 1 B+
2 1
@ JUMP_43X79

5
6
7
8

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
0.1U_0402_25V6
1

1
PC169

PC175

PC173

PC174
PR247

2
240K_0402_1% 4
1.5V_TON 1 2
D D
PR248
0_0402_5%
1 2 1.5V_EN BST_1.5V 1 2BST_1.5V-1
1 2
<28,34,39> SYSON

3
2
1
PR249 PC182 PQ48
2.2_0603_5% 0.1U_0603_25V7K SI4686DY-T1-E3_SO8

1
PL13

15

14
1
PC184 1UH_PCMB103E-1R0MS_20A_20%
@0.1U_0402_16V7K 1 2

EN_PSV

TP

VBST
+1.5VP

220U_B2_2.5VM_R15M
1
2 13 UG_1.5V
TON DRVH

PQ49

TPCA8028-H_SOP-ADVANCE8-5
PR242 3 12 1.5V_TRIP PR241
VOUT LL

5
100_0603_1% 4.7_1206_5%

10U_0603_6.3V6M
1
+5VALW 1 2 1.5V_V5FILT 4 11 SW_1.5V
1 2 +5VALW

1.5V_SNB 2
V5FILT TRIP

1
+

PC172
PR245
1.5V_FB 5 10 7.15K_0402_1%
VFB V5DRV

PC177
2
1
LG_1.5V 2
1 2 6 PGOOD DRVL 9 4

PGND
PC178

GND
4.7U_0603_6.3V6K PC181 PR243

1
@ 47P_0402_50V8J @ 100K_0402_1% PC180
1 2 PC179 PC183 680P_0402_50V7K

3
2
1
@0.1U_0402_16V7K PU14 4.7U_0805_6.3V6K

2
TPS51117RGYR_QFN14_3.5x3.5
1.5V_PGOOD
PR244
31.6K_0402_1%
1 2

1
C PR246 C
30.1K_0402_1%
PJ16
2 VCCP_IN 2 2 1 1 B+
@ JUMP_43X79

10U_1206_25V6M

2200P_0402_50V7K
PQ41

0.1U_0402_25V6
1

1
SIS412DN-T1-GE3_PAK1212-8

PC140

PC138

PC141
@ PR133 @

2
240K_0402_1% 4
VCCP_TON 1 2
PR132 @ PR131 @
PC95
100K_0402_1% 2.2_0603_5% @
1 2 VCCP_EN BST_VCCP1 2BST_VCCP-1
1 2 @ @ @
<16,28,34,39,42,46> SUSP#

3
2
1
0.1U_0603_25V7K
1

PL9 @

15

14
1
PC96 2.2UH_PCMC063T-2R2MN_8A_20%
0.22U_0402_6.3V6K 1 2

EN_PSV

TP

VBST
+1.05VSP
2

1
UG_VCCP

220U_B2_2.5VM_R15M
2 TON DRVH 13

PR127 3 12 SW_VCCP PR181 @

VOUT LL

5
100_0603_1% 4.7_1206_5%

10U_0603_6.3V6M
1
+5VALW 1@ 2 VCCP_V5FILT 4 11 VCCP_TRIP
1 2 +5VALW

2
V5FILT TRIP

1
PR128 @ +

VCCP_SNB

PC136
VCCP_FB 5 10 23.7K_0402_1%
+3VS VFB V5DRV

PC137
2
1

LG_VCCP 2
6 PGOOD DRVL 9 4

PGND
B PC93 GND B
2

4.7U_0603_6.3V6K PC94 @
2

1
@ @ 47P_0402_50V8J PR126 @
1 2 100K_0402_1% PC92 PC135 @
7

3
2
1
PU9 @ 4.7U_0805_6.3V6K 680P_0402_50V7K

2
TPS51117RGYR_QFN14_3.5x3.5 @
1

1.05V_PGOOD <46> PQ40

PR129 SI7716ADN-T1-GE3_PAK1212-8
13.7K_0402_1% @ @
@
@1 2
1

PR130
+1.5V 31.6K_0402_1%
@
2
1

PJ17
1

@ JUMP_43X79
2

PJ21
PU13 2 1
+1.5VP +1.5V
2

0.75V_IN 2 1
1 VIN VCNTL 6 +3VALW
@ JUMP_43X118
2 GND NC 5
1

PC146
1

4.7U_0805_6.3V6K 3 7 PC151
PR239 VREF NC 1U_0402_6.3V6K
2

1K_0402_1% 4 8 PJ14 PJ19

@ PR250 VOUT NC
A
+1.05VSP 2 2 1 1 +1.05VS +0.75VSP 2 2 1 1 +0.75VS A
0_0402_5% 9
2

TP @ JUMP_43X118 @ JUMP_43X79
<5> S3_0.75V_EN 1 2
0.75V_REF G2992F1U_SO8
1

PR190 +0.75VSP
1

0_0402_5% D PR240
1 20.75V_EN 2 1K_0402_1% PC176
<8,39,45> SUSP Security Classification Compal Secret Data Compal Electronics, Inc.
1

G 0.1U_0402_16V7K
2
1

S PQ46 PC149
Issued Date 2009/01/06 Deciphered Date 2010/01/06 Title
3

PC147 SSM3K7002FU_SC70-3 10U_0603_6.3V6M

1.5V/VCCP/0.75V
2

@ 0.1U_0402_16V7K
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 30, 2009 Sheet 44 of 51
5 4 3 2 1
 5 4 3 2 1

PJ3
2 1 VGA_IN
B+ 2 1
@ JUMP_43X79 +3VS

UG_VGA

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K

10K_0402_5%
0.1U_0402_25V6
1

2
BST_VGA 1 2 BST_VGA-1 1 2

PC24

PC35

PR47
PR48 PC49

PC186

PC185
2.2_0603_5% 0.1U_0603_25V7K

1
+5VALW

1
D
PR49 D

5
0_0603_5%
PQ35
PR46
4.7_0603_5%

16

15

2
8

1
1 2 VGA_VCC
4

GND

PGOOD

PHASE

UG

BOOT
3 14 +VGA_PVCC
1 2
VIN PVCC TPCA8030-H_SOP-ADV8-5

3
2
1
PC52
2.2U_0603_6.3V6K
VGA_VCC 4 PU3 13 LG_VGA PL7
VCC ISL6268CAZ-T_SSOP16 LG 0.88UH_PCMB103E-R88MS_20A_20%
SW_VGA 1 2 +VGA_COREP

5
6
7
8

5
6
7
8

1
PC50

4.7_1206_5%
PGND 12
2.2U_0603_6.3V6K

SI4634DY-T1-E3_SO8

SI4634DY-T1-E3_SO8
2

PR164
1VGA_SNB

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M
<16> VGA_EN 1 2VGA_EN_2 5 11 ISEN_VGA 1 2

2
EN ISEN

1
+ +

PQ39

PQ36

100_0402_5%
PR62 4 4

COMP
1

1
FSET
2.2K_0402_5% PR63

PC17

PC133

PC19

PC18

PC20
VO
PC51 3.6K_0402_1%

680P_0402_50V7K
FB

2
2 2

PC126

PR70
1U_0402_6.3V6K
Rds=4.0mΩ

FSET_VGA9

10

3
2
1

3
2
1

2
VGA_FB
VGA_COMP

22.1K_0402_1%

0.01U_0402_25V7K
1
C C

42.2K_0402_1%
2
1
PR68
1VGA_COMP-1

PC55

PR69
2

2
22P_0402_50V8J
GPIO5 GPIO6

1
1

6800P_0402_25V7K
PC134

N11M-GE1/LP1 GPU_VID0 GPU_VID1 VGA_CORE

@ PR71
2

0 0 0.8V 0_0402_5%
PC54

2 1 VGA_FB-1 1 2
0 1 +VGASENSE <21>
0.85V PR179
N11M-GE1/LP1 PR620=22.6k 1 1 0.9V
1.82K_0402_1%
2

PR169
22.6K_0402_1%
1 2
GVID1-2 PJ2
6

1
VFB=0.6V +VGA_COREP 2 2 1 1 +VGA_CORE
PR180
5.36K_0402_1% @ JUMP_43X118
2 1GVID1-1
2 PQ37A
<19> GPU_VID1
1

PR166 2N7002KDW-2N_SOT363-6
2
1

10K_0402_1% PR67 PJ13

1
1

PR165 6.04K_0402_1% 2 1
10K_0402_5% 2 1
@ JUMP_43X118
2

3 2

PC127
2

0.01UF_0402_25V7K

2 1GVID0-1 5 PQ37B
B <19> GPU_VID0 PR170 2N7002KDW-2N_SOT363-6 PJ606 B
1

10K_0402_1% 1 2
+1.8VSP +1.8VS
4

1 2
1

PR72
10K_0402_5% PC129 @ JUMP_43X39
0.01UF_0402_25V7K
2
2

+3VS
1

PJ8
1

@ JUMP_43X39
2

PU6
LDO_1.8V_IN 1 6 +5VS
2

VIN VCNTL
2 GND NC 5
1

PC75
1

4.7U_0805_6.3V6K 3 7 PC79
PR104 VREF NC 1U_0402_6.3V6K
2

A 1K_0402_1% 4 8 A
VOUT NC
9
2

TP
LDO_1.8V_REF G2992F1U_SO8
1

PR103 +1.8VSP
1

100K_0402_1% D PR105
<8,39,44> SUSP 1 2LDO_1.8V_EN
2 1.24K_0402_1% PC77 Security Classification Compal Secret Data Compal Electronics, Inc.
1

G 0.1U_0402_16V7K 2009/01/06 2010/01/06 Title

Issued Date Deciphered Date
2
1

PC78
S
VGA_CORE/1.8VS/1.1VS
3

PC76 PQ22 10U_0603_6.3V6M

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.1U_0402_16V7K SSM3K7002FU_SC70-3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 29, 2009 Sheet 45 of 51
5 4 3 2 1
 5 4 3 2 1

D D

PJ9
2 1 VTT_B+
B+ 2 1
@ JUMP_43X118 +5VS

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
SW_VTT

0.1U_0402_25V6
1

1K_0402_5%
PC83

PC85
UG_VTT PR112

PC188

PC187

PR115
2.2_0603_5%
2

2
VTT_BOOT1 2 VTT_BOOT-1 1 2
PR114

2
0_0402_5% PC84
+5VALW 0.1U_0603_25V7K

1.1VS_PGOOD
<5> VCCP_POK 1 2

5
PR106
0_0603_5% PQ24

PR108

16

15
8

1
4.7_0603_5%

2
1 2 VTT_VCC 4

GND

PGOOD

PHASE

UG

BOOT
3 14 VTT_PVCC
1 2
VIN PVCC TPCA8030-H_SOP-ADV8-5

3
2
1
PC81
PR116 2.2U_0603_6.3V6K
0_0402_5% VTT_VCC 4 PU7 13 LG_VTT PL8
VCC ISL6268CAZ-T_SSOP16 LG 0.56UH_MMD-10CZ-R56M-M1_19A_20%
<16,28,34,39,42,44> SUSP# 1 2
1 2 +1.1V_VCCPP
1

C C

TPCA8028-H_SOP-ADVANCE8-5
5

1
PC86 12

TPCA8028-H_SOP-ADVANCE8-5
PGND

PQ23

PQ21
2.2U_0603_6.3V6K
2

PR117 PR107

330U_D2E_2.5VM

330U_D2E_2.5VM
1 1
@ 0_0402_5% 4.7_1206_5%
1 2 VTT_EN-1 5 11 VTT_ISEN 1 2 + +
<44> 1.05V_PGOOD

1 2
EN ISEN VTT_SNB
4 4

COMP

PC74

PC139
FSET
PR109
1

2 2

VO
3K_0402_1% PC80

FB
PC87 1000P_0603_50V7K
Rds=4.0mΩ

2
@ 0.1U_0402_16V7K @
2

10

3
2
1

3
2
1
1 VTT_FSET
VTT_FB

VTT_COMP
22.1K_0402_1%
1

42.2K_0402_1%

2
PR118
VTT_COMP-1

1
PR110
PR113

PC82 10_0402_5%
2

0.01U_0402_25V7K
22P_0402_50V8J

2
1

@
6800P_0402_25V7K

1
PC88

1
PC89

PR111
0_0402_5%
B 1 2 1 2 VTT_FB-1 2 1 B
<8> VTT_SELECT PR121 PR120 VTT_SENSE <8>
35.7K_0402_1% VFB=0.6V 1.58K_0402_1%
1

H_VTTVID1= Low, 1.1V PR119

1.96K_0402_1%
H_VTTVID1= High, 1.05V
2

PJ15
+1.1V_VCCPP 2 2 1 1 +VCCP
@ JUMP_43X118

PJ7
2 2 1 1

@ JUMP_43X118

PJ1
+1.1V_VCCPP 2 2 1 1 +1.05VS
@ JUMP_43X118
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.1VS_VTT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 29, 2009 Sheet 46 of 51
5 4 3 2 1
 5 4 3 2 1

D D

B+ PJ5
2 1 GFX_B+
2 1

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K

2
@ JUMP_43X118

0.1U_0402_25V6
PR95

1
0_0603_5%

0.22U_0603_25V7K
GFXVR_IMON <8>

PC61

PC59

PC160

PC161
PR96

0.22U_0402_6.3V6K
2 1 62881_VDD

22.6K_0402_1%
+5VALW

1 1

1
1

1
1_0603_5%

PR91
PC164

PC163
1 2
@
@ PC165 PR224

2
1U_0603_10V6K @ 0_0402_5%

2
PR101 @
10_0402_5% @ @
@ @ VSS_AXG_SENSE <8>
1 2 ISUM+

5
6
7
8
@
C ISUM- C

12 62881_VIN
1 2 @ BST_GFX 1 2BST_GFX1
1 2 PQ47
<8> VSS_AXG_SENSE PC166 @
@ @
1

1000P_0402_50V7K PR92 PC162 SI4686DY-T1-E3_SO8

@ PC72 2.2_0603_5% 0.22U_0603_16V7K 4
<8> VCC_AXG_SENSE 330P_0402_50V7K

29

10

11

13

14
1 2 @ @
2

9
PR102
+GFX_COREP 10_0402_5% PC167

AGND

RTN

ISUM+

VDD

VIN

IMON

BOOT
ISUM
1 2 330P_0402_50V7K @

3
2
1
@
7 15 UG_GFX PL12
VSEN UGATE 0.56UH_MMD-10CZ-R56M-M1_19A_20%
@
62881_FB 6 PU5 16 LX_GFX 1 2
FB ISL62881HRZ-T_QFN28_4X4 PHASE +GFX_COREP

5
62881_COMP 5 17 PC67 PC158
COMP VSSP
1 1

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M
62881_VW 4 18 LG_GFX @
VW LGATE + +

TPCA8028_PSO8
PR225

1
PR230 2 162881_RBIAS 3 19 62881_VCCP 1 2 +5VALW PR80
PR226 PR99 PC171 47K_0402_1% RBIAS VCCP 0_0603_5% 2.2_1206_5% PR82 PR81
4

1
10K_0402_1% 825K_0402_1% 1000P_0402_50V7K 2 20 3.65K_0402_1% 2 2
@ 0_0402_5%

2
PGOOD VID0
2GFX_FB-1 @

PQ19
2@ 1 1 1 2 2 1
1 21 PC66 GFX_SN

DPRSLPVR

2
2
CLK_EN# VID1
PC71 2.2U_0603_6.3V6K @ 1 2ISUM-2
1 2

3
2
1
100P_0402_50V8J +GFX_COREP PH4

VR_ON
PR227
@ @ @ 2.61K_0402_1% 10KB_0603_5%_ERTJ1VR103J
@

VID6

VID5

VID4

VID3

VID2
@

1
PC170 @ @ PC60
@ @

62881_VID0
22P_0402_50V8J 680P_0402_50V7K
@ @
2 1GFX_FB-2
2 1 1 2 2 1

62881_VID1
62881_DPRSLPVR 28

27

26

25

24

23

22
1 2
10K_0402_1%
1.91K_0402_1%

PC73 PR100 PR98 @ PR90

1

150P_0402_50V8J 17.8K_0402_1% 8.06K_0402_1% @ 11K_0402_1%

62881_VR_ON
PR97

PR238

@ @ @ @ @

62881_VID6

62881_VID5

62881_VID4

62881_VID3

62881_VID2
1 2
PC65
2

0.1U_0402_16V7K
B B

ISUM-1
@

GFXVR_PWRGD @ @
1 2
PC70
GFXVR_CLKEN#

2
0_0402_5% 2 1 PR228 0.068U_0402_10V6K
0_0402_5% PR229 GFXVR_VID_0 <8> PR93 PR89
2 1 @
0_0402_5% PR231 GFXVR_VID_1 <8> @ 100_0402_1%
2 @ 1 3.01K_0402_1%
0_0402_5% PR232 GFXVR_VID_2 <8> PR94
2 @ 1
GFXVR_VID_3 <8>

2ISUM-4
0_0402_5% 2 @ 1 PR233 82.5_0402_1%

1
GFXVR_VID_4 <8>
0_0402_5% 2 @ 1 PR234 1 2ISUM-3
1 2
0_0402_5% PR235 GFXVR_VID_5 <8>
2 @ 1
0_0402_5% PR236 GFXVR_VID_6 <8> PC68 @
2 @ 1
GFXVR_EN <8> 0.01U_0402_25V7K PC69
@
@ @ @ @ 180P_0402_50V8J

1
ISUM+
0_0402_5% 2 1 PR237
GFXVR_DPRSLPVR <8>
ISUM-
@

PJ18
+GFX_COREP 2 1 +GFX_CORE
2 1
@ JUMP_43X118

A PJ6 A
2 1
2 1
@ JUMP_43X118

(15A,600mils ,Via NO.= 30)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GFX_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 30, 2009 Sheet 47 of 51
5 4 3 2 1
 8 7 6 5 4 3 2 1

H H

+3VS

1
PR77 PR76
1.91K_0402_1% 1K_0402_5%

2
1 2
<15> VGATE PR199 0_0402_5%
G 1 2 G
<12> CLK_EN# PR200 0_0402_5% CPU_B+ PL1
<34> VR_ON 1 2 HCB4532KF-800T90_1812
PR209 0_0402_5% 1 2 B+
1 2
PR75
@ 1K_0402_5%

100U_25V_M

100U_25V_M
10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
0.1U_0402_25V6

2200P_0402_50V7K
+3VS

+5VS
+5VS
1 1

PC168

PC148
1

1
+ +

PC48

PC29

PC30

PC31
1 2

CPU_VREF
PC150

PC47
2.2U_0603_6.3V6K

2
5

5
2 2

@ 0_0402_5%
@

249K_0402_1%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
1
68P_0402_50V8J
2

5.11K_0402_1%

2
4 UGATE_CPU2 4
1

2
PC58

PR218
2
F PQ18 PQ17 F
@

CPU_TRIPSEL
TPCA8030-H_SOP-ADV8-5 PL10

3
2
1

3
2
1
CPU_CLK_EN#

PR197
CPU_OSRSEL
CPU_TONSEL
TPCA8030-H_SOP-ADV8-5 0.36UH_PCMC104T-R36MN1R17_30A_20%

CPU_PGOOD
CPU_DROOP

CPU_VR_ON
CPU_ISLEW1

1
PR74

PR210

PR78

PR79

PR198
CPU_VREF

1 2 1 4 +CPU_CORE
PC57

1
0.22U_0603_10V7K CPU_CSP2-1
2 3

5
+5VS PR184

1
PQ43 PQ42 4.7_1206_5%

17.8K_0402_1%
PR182
41

40

39

38

37

36

35

34

33

32

31

1CPU_SNB2
2
2
@ PR222
PD7 4 4 69.8K_0402_1%
TONSEL

CLK_EN#

OSRSEL

TRIPSEL
GND

VR_ON

PGOOD
VREF

V5FILT

ISLEW
DROOP

2
1SS355_SOD323-2 1 2
PH2
1 2CPU_MODE1 30 UGATE_CPU2 100K_0402_1%_TSM0B104F4251RZ

1
PR73 0_0402_5% MODE DRVH2 PC142 1 2CPU_SN-2
1 2

3
2
1

3
2
1
CPU_CSP2 2 1 2 29 BOOT_CPU2
1 2 BOOT_CPU2-1 1 2 680P_0402_50V7K PR183

2
PR223 470_0402_1% GND VBST2 PR189 2.2_0603_5% PC145 TPCA8028-H_SOP-ADVANCE8-5 TPCA8028-H_SOP-ADVANCE8-5 28.7K_0402_1%

CPU_CSN2
CPU_CSP2
E E
1

1 2 CPU_CSP2-2 3 28 PHASE_CPU2 0.22U_0603_10V7K 1 2

PC156 PC157 33P_0402_50V8J CSP2 LL2 PC56
100P_0402_50V8J 1 2 CPU_CSN2-1 4 27 LGATE_CPU2 0.033U_0402_16V7K
2

CPU_CSN2 2 PC155 33P_0402_50V8J CSN2 DRVL2

1 +5VS
PR221 470_0402_1% 1 2 CPU_CSN1-1 5 26 1 2
CPU_CSN1 2 PC154 33P_0402_50V8J CSN1 V5IN PC53 10U_0603_6.3V6M CPU_B+
1
PR220 470_0402_1% 1 2 CPU_CSP1-2 6 PU12 25
CSP1 PGND
1

PC152 33P_0402_50V8J TPS51621RHAR_QFN40_6X6

PC153 CPU_GNDSNS 7 24 LGATE_CPU1
100P_0402_50V8J GNDSNS DRVL1
2

CPU_CSP1 2 1 CPU_VSNS 8 23 PHASE_CPU1

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
0.1U_0402_25V6

2200P_0402_50V7K
PR219 470_0402_1% VSNS LL1
CPU_THERM 9 22 BOOT_CPU1
2 1 BOOT_CPU1-1 1 2

1
THERM VBST1 PR187 2.2_0603_5% PC144

PC46

PC33

PC32

PC34
DPRSLPVR

5
UGATE_CPU1 0.22U_0603_10V7K

PC45
10 21
2CPU_VR_TT#

VR_TT# DRVH1
1

1 2
20K_0402_1%

+5VS

2
IMON

PD6
0_0402_5%

0_0402_5%

0_0402_5%

68_0402_5%

VID6

VID5

VID4

VID3

VID2

VID1

VID0
PSI#

1SS355_SOD323-2
PR66

PR65

D D
4 UGATE_CPU1 4
2

11

12

13

14

15

16

17

18

19

20
2

PQ16 PQ15
VID6

VID5

VID4

VID3

VID2

VID1

VID0
2CPU_DPRSLPVR
CPU_IMON

CPU_PSI#

TPCA8030-H_SOP-ADV8-5 TPCA8030-H_SOP-ADV8-5 PL11

3
2
1

3
2
1
0.36UH_PCMC104T-R36MN1R17_30A_20%
PR53

PR217

PR216

@
1

1 4
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

1
CPU_CSP1-1
2 3

5
PR185
2

1
PQ44 PQ45 4.7_1206_5%

17.8K_0402_1%
PR186
@

1CPU_SNB1
+VCCP

2
PR64
<5,34>
H_PROCHOT#
<8>

<8>

4 4 69.8K_0402_1%
VSSSENSE

VCCSENSE

PROC_DPRSLPVR 1

2
PR215

PR214

PR213

PR208

PR207

PR206

PR205

PR196

PR195

PR194

1 2
PH3
100K_0402_1%_TSM0B104F4251RZ
C PC143 1 2CPU_SN-1
1 2 C

3
2
1

3
2
1
680P_0402_50V7K PR188

2
TPCA8028-H_SOP-ADVANCE8-5 TPCA8028-H_SOP-ADVANCE8-5 28.7K_0402_1%

CPU_CSN1
CPU_CSP1
H_VID6

H_VID5

H_VID4

H_VID3

H_VID2

H_VID1

H_VID0

1 2
PSI#

PC159
1

0.033U_0402_16V7K
0.22U_0402_6.3V6K
1
0_0402_5%

12.4K_0402_1%
PR45

PC44
PR212

<8>

<8>

<8>

<8>

<8>

<8>

<8>

<8>

<8>
<8>
IMVP_IMON

PSI#

H_VID6

H_VID5

H_VID4

H_VID3

H_VID2

H_VID1

H_VID0
2

PROC_DPRSLPVR

+VCCP

H_VID0 2 1PR61 @ 1K_0402_5% H_VID0 2 1PR191 1K_0402_5%

<8>

H_VID1 2 1PR60 @ 1K_0402_5% H_VID1 2 1PR192 1K_0402_5%

VSSSENSE

B B
H_VID2 2 1PR59 1K_0402_5% H_VID2 2 1PR193 @ 1K_0402_5%

H_VID3 2 1PR58 1K_0402_5% H_VID3 2 1PR201 @ 1K_0402_5%

H_VID4 2 1PR57 1K_0402_5% H_VID4 2 1PR202 @ 1K_0402_5%

H_VID5 2 1PR56 @ 1K_0402_5% H_VID5 2 1PR203 1K_0402_5%

H_VID6 2 1PR55 @ 1K_0402_5% H_VID6 2 1PR204 1K_0402_5%

PROC_DPRSLPVR 2 1PR54 10K_0402_5% PROC_DPRSLPVR 2 1PR211 @ 1K_0402_5%

Clarkfield: VID(0-5):001101
Auburndale: VID(0-5):001110
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/06 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, October 29, 2009 Sheet 48 of 51
8 7 6 5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Reason for change PG# Modify List Date Phase

D
1 D

6
C C

10

B B

11

12

13

14

15

16
A
17 20081022 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2009/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
<Doc>
Date: Thursday, October 29, 2009 Sheet 49 of 51
5 4 3 2 1
 5 4 3 2 1

NO DATE PAGE MODIFICATION LIST PURPOSE

------------------------------------------------------------------------------------------------------------- EVT TO DVT
1 P15 Add C638~C645 For UMA HDMI
2 P05 Add test point for BCLK_ITP,BCLK_ITP#,PRDY# For XDP connector
3 P32,P28 Change J6 size & unstuff ODD power control components Disable ODD power control circuit
D D
Change J4 size
4 P17 Stuff C262 For UMA CRT
5 P34 Change R291,R294 from +3VALW to +3VS
6 P38 Add R603 pull high to +3VS For PM_BTN#
7 P38 Change JP1 from 6 pin to 8 pin , For LED color changed
Change JP8 from 14 pin to 12 pin , unstuff R322 Remove CLK_48M_CR
8 P29,P34 Change EN_WOL to EN_WOL# For identify clearly
9 P34 EC pin26-> EC_FAN_PWM , pin75->PCH_TEMP_ALERT , EC GPIO arrangement
pin34->PROCHOT# , pin66->NOVO#
10 P31 Change JP12 pin define For EC FAN control
11 P16 Change U5 pin3,pin5 POWER , GND reversed
12 P15 Add U28 for ICH_POK & VGATE Reserved
C C
13 P12 Unstuff R278,stuff R269 and change U14 to SA00003HQ00 For low power CLK GEN
14 P13 Change U3 from 2MBytes to 4MBytes For 4MBytes SPI ROM for PCH
15 P29 Correct Q17 to P/N:SB000007600 For +3V_LAN power
16 P16 Add C646 for BUF_PLT_RST# Reserved for BUF_PLT_RST# overshoot problem
17 P36 Change U9 from 2MBytes to 256KBytes For 256KBytes SPI ROM for EC
18 P03 UMA_HDMI@ , HDMI@ , BT@ , 3G@ , ESATA@ , CMOS@ New BOM structure
19 P08 Add R608 For PSI# pull down
20 P37 Delete D18
21 P16 Unstuff R210,R212 Set Boot BIOS Strap to SPI
22 P22 Change & stuff R475 to 30K,R51 to 15K For N11M-GE1 QS sample
Unstuff R474,R50
23 P25 Unstuff R246 Level shift default setting
B B
24 P39 Change C373 to DIS@ for DIS power sequence
25 P15,P16,P17 Change R436 from 1K to 10K Check list Rev2.0 update
Change C447 from 0.1u to 1u
Delete R514
Unstuff C493,C494
Reserve R609
27 P34 Add R607 Reserved for KB926 SPI STRAP PIN
28 P36 Change LED1,LED3,LED4 to white color
LED2 to orang\white color and orage connect to +3VALW
29 P14 Change exp-card from PCIE port 1 to port 5 SW BIOS request
30 P38 Unstuff SW1
A
31 P13,P34 Change X1,X2 footprint A

32 P12 Change C348 to 22p,C349 to 22p For Crystal matching

33 P13,P20 Add C647~C650 12p, stuff C370->22p, R331->33 Reserved for RF team Compal Electronics, Inc.
34 P36 Delete JP6 SPI ROM socket Title

35 P37 Change C430,C615 footprint to B2 type HW PIR

Size Document Number Rev
36 P27,P32,P37 Change Q4,Q24,Q32,Q37 footprint to AO3413 B LA-5751 0.3

Date: Thursday, October 29, 2009 Sheet 50 of 51

5 4 3 2 1
 5 4 3 2 1

NO DATE PAGE MODIFICATION LIST PURPOSE

------------------------------------------------------------------------------------------------------------- EVT TO DVT
37 P34 Change C320 to 0805 type
38 P08 Unstuff C268 For CPU VDDQ (DDR3 1.5V rails)
Change C252,C258 from 10u to 22u
39 P34 Change ODD_power_on# from U13 pin28 to pin 76 EC GPIO arrangement
D
Add EC_TACH on U13 pin28 to JP12 D

40 P31 Change U20 to EMC1403, add C651 Change thermal sensor solution to EMC1403
41 P05 Add Q42,R610 Reserve for +0.75V enable option
42 P34,P35 Add C652,C653,C654 Reserve for NUM_LED#,CAPS_LED# ESD request
43 P34 Add R611,R612,R613 For EC_FAN_PWM, EC_TACH
NO DATE PAGE MODIFICATION LIST PURPOSE
------------------------------------------------------------------------------------------------------------- DVT TO PVT
1 P34 Reseve R614,R615. EC_ID to identify KB926 D or E
2 P34 Stuff R607 KB926 SPI STRAP PIN
3 P33 Stuff C632~C635 EMI request
4 P16 Stuff C646 For PLT_RST# singnal quality
C 5 P37 Add R616 100K, change R304 to 100K, C353 to 0.1u For +3VS_BT power on rising time C

6 P37 Changed R304 pin1 from +5VS to +5VALW For +3VS_BT power on leakage
7 P5 Stuff R283, C338 0.01u For S3 power reduction
8 P31 Add U29 Colay EMC2103/EMC1403 thermal sensor

B B

A A

Title
Compal Electronics, Inc.
HW PIR
Size Document Number Rev
B LA-5751 0.3

Date: Thursday, October 29, 2009 Sheet 51 of 51

5 4 3 2 1
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