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Front-to-Back Alignment Techniques in Microelectronics/MEMS

Fabrication: A Review

Article  in  Sensor Letters · March 2006

DOI: 10.1166/sl.2006.007

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 Copyright © 2006 American Scientific Publishers
All rights reserved SENSOR LETTERS
Printed in the United States of America Vol. 4, 1–10, 2006

Front-to-Back Alignment Techniques in

REVIEW
Microelectronics/MEMS Fabrication: A Review
Prem Pal,1 Yong-Jun Kim,1 and Sudhir Chandra2
∗
1
Yonsei Microsystems Laboratory, School of Mechanical Engineering, Yonsei University, Seoul, South Korea
2
Centre for Applied Research in Electronics, Indian Institute of Technology, Delhi, India

(Received: 1 December 2005. Accepted: 26 January 2006)

The front-to-back alignment technique in photolithography process is often required for registering
mutually aligned patterns on both the sides of the wafer in the fabrication process of power devices
such as power transistors and various kinds of
Delivered bymicroelectromechanical
Ingenta to: systems (MEMS) based
devices such as RF MEMS components, mechanical sensors, bio/chemical sensors, microcalorime-
Prem Pal
ters, and microfluidic devices etc. This paper reviews the progress made in the front-to-back align-
IP : 133.6.73.118
ment techniques in semiconductor processing for the realization of microstructures for MEMS and
Wed, 12 Mar
other microelectronics devices. Various techniques,2008which
03:33:47
are used in commercial front-to-back
mask aligners, are discussed in detail. Some other alternative methods, which use the conventional
contact/proximity single sided mask aligner for defining the mutually aligned patterns on both the
sides of the wafers, are also covered in this review. The principle and approach of various front-to-
back alignment techniques have been presented. The alignment accuracy and the source of errors
have been discussed. A list of the references which incorporate front-to-back alignment methods
for the development of MEMS/microelectronics devices such as, mechanical sensors, bio/chemical
sensors, microcalorimeters, RFMEMS components, microfluidic devices, power transistors is also
included.
Keywords: MEMS, Lithography, Front-to-Back Alignment, Mask Aligner, Mechanical Jig and
Projector.

CONTENTS formation and/or minority carrier life time tailoring

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. Front-to-Back Alignment Using Commercial Mask Aligner . . .
2.1. Infrared Mask Aligner . . . . . . . . . . . . . . . . . . . . . . .
2.2. Double Sided Mask Aligner . . . . . . . . . . . . . . . . . . .
2.3. Front-to-Back Alignment for Optical Projection . . . . . . .
3. Other Techniques for Front-to-Back Alignment . . . . . . . . . .
3.1. Mechanical Jig . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2. Silicon/Substrate Etching Method . . . . . . . . . . . . . . . .
3.3. Generation of Front-to-Back Alignment Marks by
Projector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4. Mechanical Jig and Mask . . . . . . . . . . . . . . . . . . . . .
3.5. Front-to-Back Alignment Using Mask Modification . . . .
4. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References and Notes . . . . . . . . . . . . . . . . . . . . . . . . . . .
1. INTRODUCTION
The integrated circuit (IC) fabrication requires lithography
only on the front-side of the wafer. The back-side of
the wafer is, at best, used for large area ohmic contact
∗
Corresponding author; E-mail: schandra@care.iitd.ernet.in
(both enhancing and reducing). However, the fabrication
1
3 of power devices1 and many kinds of microelectro-
3 mechanical systems (MEMS) based devices such as
4 RFMEMS components,2–6 mechanical sensors,7–18 thermal
4
sensors,19–21 micro and nano calorimeters,22–27 microfluidic
4
5 devices,28–30 microreaction engineering,31 and bio/chemical
5 sensors32–38 require process steps, including pattern trans-
fer, on both the sides of the wafer. In such cases, it is a
6
requirement that the patterns on the back-side of the wafer
6
8 are accurately aligned with respect to the features already
9 formed on the front-side. Figure 1 shows the schematic rep-
9 resentation of front-to-back alignment for the fabrication of
9
MEMS based devices using bulk micromachining process.
To illustrate the requirement of front-to-back alignment
for the realization of MEMS structures, the fabrication
of recessed proof mass (Fig. 1(b)) for accelerometer has
been taken as an example.11 The realization of proof
mass for accelerometer using bulk micromachining pro-
cess requires the lithography steps on both the sides of
the wafer for transferring the mutually aligned patterns.

Sensor Lett. 2006, Vol. 4, No. 1 1546-198X/2006/4/001/010 doi:10.1166/sl.2006.007 1

 Front-to-Back Alignment Techniques in Microelectronics/MEMS Fabrication: A Review Pal et al.

Figure 2 shows the schematic view of process steps used

for the realization of recessed proof mass. First, the oxi-
dized silicon wafer is patterned for square-shaped cavities
on both the sides of the wafer and the patterns are aligned
Air gap to each other using front-to-back alignment technique as
shown in Figure 2(a). The front-to-back alignment can be
REVIEW

performed using one of the techniques described in this

(a) RFMEMS component : Micromachined patch antenna formed
using bulk micromachining process [4]
article. After this step, silicon anisotropic etching is per-
formed to etch the cavity up to the required depth as shown
P + silicon supporting arm in Figure 2(b). This eventually defines the gap between the
seismic mass and the counter electrodes. The wafer is now
re-oxidized thermally to obtain about 1
m oxide thick-
(100)-Si (100)-Si
ness. The next masking step is carried out on the front-side
of the wafer to define the pattern for supporting arms for
seismic mass. Boron pre-deposition and driven steps are
carried out to make the supporting arms P+ . The thickness
(b) Recessed proof mass for accelerometer [11]
of the supporting arms (P+ diffusion depth) of the seismic
Fig. 1. Schematic representation of front-to-back alignment require- mass is controlled by the boron pre-deposition and drive-
ment for the fabrication of MEMS structures using bulk micromachining in cycles.39 After this step, front-to-back alignment tech-
process. Delivered by Ingenta to:
nique is used again for defining the seismic mass on the
Prem Pal
back-side of the wafer. The anisotropic etching of silicon
IP : 133.6.73.118
is then carried out for releasing the proof mass. Figure 3
Wed, 12 Mar 2008 03:33:47
Prem-Pal received the Bachelor of Science (B.Sc.) degree (Physics, Chemistry, Mathemat-
ics) and the Master of Science (M.Sc.) degree in Physics from Agra University Agra, India
in 1993 and 1995, respectively. He obtained Master of Technology (M.Tech.) degree in Solid
State Material (SSM) in December 1999 and Ph.D. in the area of MEMS/Microelectronics
technology in December 2004, both from Indian Institute of Technology Delhi (IIT Delhi),
India. Presently, he is working as postdoctoral researcher at Yonsei Microsystems Labora-
tory (YML), School of Mechanical Engineering, Yonsei University Seoul, South Korea. His
research interests include MEMS/Microelectronics technology, MEMS based bio/chemical
and mechanical sensors, and thin films for MEMS.

Yong-Jun Kim received the Bachelor of Engineering in electrical engineering from Yonsei
University, Seoul, Korea, in 1987. He received the Ph.D. degree in electrical engineering
from Georgia Institute of Technology in 1997. His thesis work involved the application of
polymer/metal multilayers to MEMS. From 1996 to 2000, he was with Samsung Electronics
Co. as a senior engineer and project leader working on electronic packaging and various
MEMS devices. Since 2000, he joined the faculty of Yonsei University as a Professor in the
School of Mechanical Engineering. His current research includes general micromachining,
bio and environmental sensors, RF-MEMS, and flexible electronic packaging.

Sudhir Chandra obtained M.Sc. (Physics) from Agra University in 1970. He did his M.Tech.
in Solid State Physics in 1972, and Ph.D. in the area of Microelectronics Technology in 1980,
both from Indian Institute of Technology, Delhi (IIT Delhi). He joined IIT Delhi as faculty in
1981 in Centre for Applied Research in Electronics (CARE). He contributed significantly in
setting up the Microelectronics Laboratory at IIT Delhi. He established various unit processes
and integrated the processes for MOS ICs. His research interests include SIMOX SOI tech-
nology, polycrystalline silicon TFTs, Laser Recrystallization of polysilicon, CVD/PECVD
processes, and Direct Wafer Bonding. Currently, he is working on various aspects of bulk
and surface micromachining technologies for MEMS, especially for RF applications.

2 Sensor Letters 4, 1–10, 2006

Pal et al. Front-to-Back Alignment Techniques in Microelectronics/MEMS Fabrication: A Review

Front-side

(100)-Si

Back-side
(a) Lithography using

REVIEW
front-to-back alignment
technique and etching of oxide

A A′

(b) Anisotropic etching for Top view of the mask

creating the cavities on both
the sides of the wafer (A-A′)

B B′
Fig. 3. SEM photograph exhibiting the tilted view of seismic mass
(c) Re-oxidation, lithography and P + supported by four symmetric beams. Reprinted with permission from
Top view of the mask
diffusion for supporting arms (B-B′) [11], P. Pal and S. Chandra, Sens. Lett. 2, 226 (2004). © 2004, American
Delivered by Ingenta to:
Scientific Publishers.
Supporting arms
Prem Pal
This paper reviews the progress made in the front-to-
IP : 133.6.73.118
back alignment techniques in semiconductor processing for
Wed, 12 Mar 2008 03:33:47
Proof
mass the realization of MEMS and microelectronics devices.
(d) Lithography on the back-side and
anisotropic etching 2. FRONT-TO-BACK ALIGNMENT USING
COMMERCIAL MASK ALIGNER
Three-dimensional (3-D)
view from the back-side
Front-to-back mask alignment techniques, which are com-
Silicon Silicon dioxide +
P Silicon monly used for the commercial production of mask
aligners, are described below:
Fig. 2. Process sequence for realizing the seismic mass for accelerom-
eter using bulk micromaching process. In this process, the front-to-back
alignment method is used at steps (a) and (d). Reprinted with permission 2.1. Infrared Mask Aligner
from [11], P. Pal and S. Chandra, Sens. Lett. 2, 226 (2004). © 2004,
American Scientific Publishers. Infrared mask aligner uses the infrared (IR) source to illu-
minate features on the back-side of the wafer so that these
shows the SEM photograph of recessed proof mass fabri- may be “viewed” from the front-side of the wafer, as silicon
cated using this process.11 Many examples can be found is somewhat transparent to IR radiation.40–42 The limitation
in the literature which use front-to-back alignment process of this IR mask aligner is that the wafer should not have any
for the realization of micro/nano devices based on MEMS IR-opaque layers (such as gold, aluminum metallization)
technology.2–38 on either side of the wafer in the alignment mark regions.
It is obvious that the mask aligner commonly used The region around the alignment marks should be trans-
in IC fabrication cannot be used for front-to-back align- parent to IR-radiation. Figure 4 shows the schematic rep-
ment in lithography process. Several companies, including resentation of front-to-back infrared mask aligner. Infrared
Suss MicroTech (Germany), EV Group (Austria), Canon
Inc. (Japan), OAI (California), Ultratech Inc. (California), Alignment marks on
the screen
ASML (Netherlands), provide mask aligners for aligning
the patterns on both sides of the wafer during lithography
process steps. These mask aligners are expensive in com- IR video system

parison to commonly used single sided mask aligners. Mask

Apart from the commercial front-to-back mask aligners,
Photoresist
some other techniques, which can be adapted for existing Silicon wafer Photo resist coated wafer
mask aligners, are also developed for prototyping devices
and demonstrating new ideas and concepts in an R&D envi- Pattern on the
back-side
ronment. To minimize the light scattering, double side pol-
IR radiation
ished wafers are used for performing the lithography on the
two sides of the wafer. Fig. 4. Schematic representation of infrared front-to-back mask aligner.

Sensor Letters 4, 1–10, 2006 3

 Front-to-Back Alignment Techniques in Microelectronics/MEMS Fabrication: A Review Pal et al.

U.V. light
Top Mask
REVIEW

Bottom Mask Photoresist coated wafer

U.V. light

Fig. 5. Schematic view of exposure system using double sided mask aligner. Reprinted with permission from [41], S. M. Sze, Semiconductor
Sensors (1994). © 1994, John Wiley and Sons Inc., New York.

alignment technique is also used in silicon wafer bonding (a) Mask Computer screen
process for aligning the patterns on the two wafers.43
The typical alignment accuracy of infrared mask aligners
is reported to be within 5
m.
Delivered by Ingenta to: Microscope
2.2. Double Sided Mask Aligner Prem Pal
IP : 133.6.73.118
The double sided mask aligner has two setsWed,
of alignment
12 Mar 2008 03:33:47 CCD
optics: one for the upper and the other for the lower side of
the wafer to perform the front-to-back alignment.40–42 In
this method, the two masks are first aligned to each other
and the mask assembly is securely fixed. The photoresist (b) Mask Computer screen

coated wafer is then inserted between the masks, and either Photoresist
the top or bottom mask is used for the mask-to-wafer align- coated
ment. The resist is exposed on both the sides of the wafer wafer

using UV light source. The alignment scheme is schemati- Microscope

cally shown in Figure 5.
In another approach, alignment marks on mask are
viewed from the back side and simultaneously stored elec-
tronically on computer screen as shown in Figure 6(a).
Thereafter, the photoresist coated wafer is loaded. The
alignment marks on the wafer are facing down. These
marks are then aligned with already stored image (elec-
tronically) of the alignment marks of the mask as shown in
Figure 6(b). After this step, the UV exposure is performed
from the front-side.
The front-to-back alignment accuracy of double sided
mask aligners is reported to be better than 1
m.
2.3. Front-to-Back Alignment for Optical Projection
Recently, a new method of front-to-back alignment has
been developed for optical projection lithography tools.44–45
Alignment principle of this method has been illustrated in
Figure 7. The existing Through-The-Lens (TTL) or Off-
Axis (OA) alignment system is used to demonstrate the
technique.44 45 The alignment marks on the backside of the
wafer are imaged to the front-side by two or more optical
modules that are embedded in the system just below the
wafer chuck as shown in Figure 7. The existing alignment
system is used to align the image of the backside marks.
CCD
Fig. 6. Double-sided alignment scheme (SUSS MA-6). (a) Viewing and
storing of mask alignment marks from the back side. (b) Alignment of
wafer back-side marks with electronically stored marks.
In this method, the alignment accuracy is claimed to be
better than 500 nm.
3. OTHER TECHNIQUES FOR
FRONT-TO-BACK ALIGNMENT
The commercial front-to-back mask aligners (IR and dou-
ble sided) are easy to use and give better alignment accu-
racy but these are quite expensive (typically 200,000 $ or
more). Some other methods for aligning the pattern on both
the sides of the wafer during photolithography steps are
also developed. These methods/techniques are low cost and
can be adopted on any type of one sided contact/proximity
mask aligners which are used for lithography process on
one side of the wafer in IC technology. The techniques are
very useful for those who do not have the access to com-
mercial front-to-back mask aligner for demonstrating new

4 Sensor Letters 4, 1–10, 2006

Pal et al. Front-to-Back Alignment Techniques in Microelectronics/MEMS Fabrication: A Review

Analyzer Pins, orthogonal

to the base of jig
50 KHz
Detector
Reticle

Alignment marks
Laser

REVIEW
Upper mask

Lower mask

Photoresist
coated wafer

Spatial
Filter Alignment jig

Fig. 8. Schematic view representing the transformation of front-to-back

Wafer alignment marks on both the sides of the wafer using mechanical jig
Image Grating Mark and two photo masks.
Delivered by Ingenta to:
16 µm
Prem Pal
directions.9 To align the mask patterns with respect to
IP : 133.6.73.118
crystallographic directions, the primary flat of the wafer is
Fig. 7. Schematic view of front-to-back alignment principle
Wed, for 12optical
Mar 2008 03:33:47
projection. Reprinted with permission from [44], C. Gui et al., Proc. generally taken as the reference. In this method, the regis-
SPIE 4688, 867 (2002). © 2002; [45], F. G. C. Bijnen et al., Proc. SPIE tration of alignment marks with respect to the primary flat
5037, 641 (2003). © 2003, SPIE, USA. is quite difficult because the wafer is sandwiched between
the masks.
research ideas and concepts. These methods/techniques are Alignment Accuracy: In this method the alignment
summarized below. accuracy is described theoretically only. The main sources
of misregistration of alignment marks are as follows:
3.1. Mechanical Jig (1) The pins are not orthogonal to the base of alignment
One possible and inexpensive method for front-to-back jig.
alignment is suggested by White and Wenzel.46 In this (2) The masks are not perfectly aligned and locked prop-
method, a mechanical jig with three orthogonally fixed pins erly with three pins of the jig during exposure.
and a set of two masks, having only the alignment marks, (3) Limited surface finish of the pins.
are used for creating mutually aligned reference marks on (4) Variation in the pins’ diameter.
the two sides of the wafer. The first mask is made using
the standard mask making process. The second mask is 3.2. Silicon/Substrate Etching Method
created using the first mask and the mechanical jig. For
this purpose, a photoresist coated blank mask plate and In this class of front-to-back alignment method, the
the first mask are aligned against the three pins of the jig. silicon/substrate etching is used for generating or revealing
In this position, the assembly is exposed. The alignment the alignment marks on to the wafer. Two methods have
marks on the second mask plate get delineated by usual been developed using silicon/substrate etching process.
developing and etching process. These two masks are then First method, developed by Kim et al., is based on forming
used for transferring the mutually aligned identical marks a small (30
m square) and very thin (2
m) diaphragms
on both the two sides of the wafer. To transfer the align- by silicon anisotropic etching process.47 These diaphragms
ment marks on two-sides of the wafer, a both-side photore- are used as reference for aligning the patterns on both the
sist coated wafer is sandwiched between these two masks. sides of the wafer. The front-to-back alignment accuracy is
This sandwiched assembly is set against the three orthogo- reported to be less than 1
m. Figure 9 shows the schematic
nally fixed pins on the mechanical jig as shown in Figure 8. view of formation of front-to-back alignment marks by sil-
In this position the wafer is exposed from the front-side. icon anisotropic etching.
On the back-side, it is exposed through a large hole in In the second method developed by Svetlana et. al., the
the jig. alignment marks are formed on the thin diaphragm so that
In bulk micromachining process, the microstructures are these can be viewed from both the sides of the wafer.48
created by anisotropic etching which requires accurate reg- This method has been used for fabricating the neurochip
istration of mask patterns with respect to crystallographic and the alignment accuracy has been measured to be less

Sensor Letters 4, 1–10, 2006 5

 Front-to-Back Alignment Techniques in Microelectronics/MEMS Fabrication: A Review
Mask
(100)-Si
REVIEW
Pattern on back-side
Alignment marks created by
anisotropic etching
Fig. 9. Schematic view of front-to-back alignment method using the
alignment marks generated by anisotropic etching.
than 2
m. Since the procedure relies on viewing of align-
ment marks on both the side of the wafer, the alignment
accuracy of the method is not affected by the misalignment
of device patterns from the crystallographic directions and
surface orientation offset of the (100)-Si wafer.49 50 How-
ever, both the techniques are destructive and require extra
time consuming process steps. Delivered by
Prem Pal
3.3. Generation of Front-to-Back IP :
133.6.73.118
Alignment Marks by Projector
Wed, 12 Mar 2008 03:33:47
In this technique, a separate equipment (referred as projec-
tor) is used for generating the fiducial marks on one side
of the wafer which are aligned with the patterns already
formed on the other side of the wafer.51 These fiducial
marks are then used for aligning the patterns on both the
sides of the wafer using any conventional single-sided mask
aligner. The schematic drawing shown in Figure 10 exhibits
the principle of this technique. In the design of the instru-
ment, the microscope is constraint to move only in the ver-
tical direction. The illumination of the fiducials is sufficient
to expose the photoresist. First, the fiducial is illuminated
and projected vertically upward on a predetermined line
of sight. Thereafter, the microscope is focused on the pro-
jected fiducial and an electronic filar on the video readout
is adjusted onto the centre of the fiducial’s image as shown
in Figure 10(a). The illumination of the projected fiducial
is then turned off. The one side patterned wafer/substrate
is used for demonstrating the technique. The photoresist is
coated on the unpatterned side and the wafer is placed on
the slide having the movement in x-y direction as shown
in Figure 10(b). In this position the photoresist coated side
is facing down. The microscope is focused with the pattern
on the top side of the wafer and x-y slide is adjusted to cen-
tre a selected feature/pattern onto the electronic filar on the
screen as shown in Figure 10(b). The fiducial is then illu-
minated to expose its projected image into the photoresist.
This will result in transferring the fiducials marks aligned
with the features/patterns of the opposite side of the wafer.
The same procedure may be repeated to generate the fidu-
cial marks on the photoresist coated side. The resist is then
developed. The fiducial marks generated by this method
can now be used for aligning the pattern on both the sides
of the wafer using any conventional mask aligner.
6 Sensor Letters 4, 1–10, 2006
Pal et al.
(a) (b)
Monitor
Video Filar centered Feature centered
microscope on Fiducial on filar
A A′ A A′
Projected
Fiducial
Projector Projector
Fig. 10. Alignment principle for transferring the aligned fiducial marks
on the other side of the wafer (a) Setup of the line of sight: Fiducial is
projected to plane A-A and simultaneously viewed on the screen. The
fiducial marks are aligned centrally with electronic filar. (b) Transfer of
fiducial marks: The photoresist coated substrate/wafer is inserted into
plane A-A . The patterns, which are already exist on the wafer, is fac-
ing up while the photoresist coated side is facing down. The selected
feature or alignment mark on the wafer is aligned with electronic filar.
Ingenta
The fiducialto:projector is then turned on to expose its pattern into the
photoresist to the lower side of the wafer. Reprinted with permission
from [51], P. N. Everett and W. F. Delaney, Appl. Opt. 31, 7292 (1992).
© 1992, Optical Society of America.
Authors claim the alignment accuracy within 1
m. The
main drawback of this method is that it requires separate
equipment for defining the fiducial marks on one of the
sides of the wafer.
3.4. Mechanical Jig and Mask
In this technique, a mechanical jig and a sheet metal mask
are used for front-to-back alignment.52, 53 This technique
enables the formation of a set of reference marks on the
two sides of the wafer which are mutually aligned. These
are subsequently used as the alignment marks for transfer-
ring the pattern on both the sides of the wafer using stan-
dard mask aligners. The optical photograph of mechanical
jig and mask is shown in Figure 11. The separation of the
two parallel ridges of mechanical jig is kept larger than the
wafer diameter. These are used for the purpose of align-
ment on the two sides of the wafer. Concentric circular
grooves are provided at the centre of the aligner for hold-
ing the wafer in position using vacuum. The jig also has
four threaded holes marked as T1 , T2 , T3 , and T4 as illus-
trated in Figure 11. The locations of these holes are cho-
sen such that these lie outside the periphery of the silicon
wafer during front- or back-side alignment as shown in
Figures 12(a) and (b). The metal mask plate has been made
from 1 mm thick stainless steel sheet. The width of the
rectangular-shaped mechanical mask plate is greater than
the wafer diameter but less than the separation of the two
parallel ridges of the jig. In the mask plate, four identical
through-holes (marked as h1 , h2 , h3 , and h4 in Fig. 11) are
made corresponding to the holes (T1 , T2 , T3 , and T4 ) in the
jig. The diameter of the mask plate holes h1 , h2 , h3 , and h4
Pal et al. Front-to-Back Alignment Techniques in Microelectronics/MEMS Fabrication: A Review
Ridges, orthogonal to
the base of jig
Circular grooves
Mask plate
Alignment marks
Through holes for
T1 T2
h1 h2
holding the mask For vacuum
plate with jig
during alignment
h4 h3 T4 T3 Jig or Fixture
Fig. 11. Photograph of the mechanical jig and metal sheet mask
used for front-to-back alignment. Reprinted with permission from [52],
A Low Cost Front-to-Back Alignment System Using Precision Metal
Sheet Mask and Mechanical Fixture Indian Patent Application No.
669/DEL/2003. © 2003; [53], Some Novel Processes and Techniques for
MEMS Design, Fabrication and Characeterization, Ph.D. Thesis, Indian
Institute of Technology, Delhi, India (2004). © 2004.
is larger than that of the jig. This is the essential
require- by Ingenta
Delivered
ment for alignment as explained in the next paragraph. The
Prem Pal
mask plate has four “+” shaped through holes asIPshown
: 133.6.73.118
in Figure 11. The separation of these alignment Wed,marks 12 Mar
is 2008
selected such that these fall close to the periphery of the
silicon wafer. The top and bottom sides of the sheet metal
mask are marked “F” and “B” to identify its front and back
sides respectively.
For transferring mutually aligned marks on the two sides
of the wafer, the both side photoresist coated wafer is
positioned on the aligner with its front-side facing up
and its primary flat towards the top ridge as shown in
Figure 12(a). The wafer is gently pushed in the direction of
the arrow as shown in Figure 12(a) so that its primary flat
rests against the top ridge and the periphery (or secondary
Silicon wafer
F1 F2 F2 F1
Jig or Fixture
F Mask plate B
(a) (b)
Fig. 12. Alignment procedure to generate the front-to-back alignment
marks on the wafer, (a) Front-side alignment: The wafer and metal sheet
mask are aligned with respect to the top and the right side of wafer
holder (jig) guides, (b) Back-side alignment: Mask and wafers are flipped
about the vertical axis. The alignment is now done with respect to the
top and the left side of the wafer holder (jig) guides. The arrow marks
are indicating the direction of gently pushing the wafer during alignment
process. The shaded area indicates the wafer location below the sheet
metal mask. F1 and F2 are the corner points on the wafer flat.Reprinted
with permission from [52], A Low Cost Front-to-Back Alignment Sys-
tem Using Precision Metal Sheet Mask and Mechanical Fixture, Indian
Patent Application No. 669/DEL/2003. © 2003; [53], Some Novel Pro-
cesses and Techniques for MEMS Design, Fabrication and Characeteri-
zation, Ph.D. Thesis, Indian Institute of Technology, Delhi, India (2004).
© 2004.
Sensor Letters 4, 1–10, 2006
flat if present) against the right side ridge of the aligner.
While maintaining this alignment, the vacuum is applied to
hold the wafer in position. F1 and F2 are the corner points
of the wafer flat. After this step, the mechanical mask plate
is placed on top of the wafer with its front-side facing up.
The mask plate is then pushed along the same direction
REVIEW
(Fig. 12(a)) so that it is aligned and held against the top and
right side ridges of the aligner. Maintaining this alignment,
the mask plate is secured in this position using the four
screws. In this position, the wafer is exposed by UV light.
During the UV exposure, only the “+” shaped alignment
marks are exposed as the rest of the wafer is covered by
the sheet metal mask. After UV exposure on the front-side,
the mask and the wafer are removed from the fixture and
filliped along the vertical axis so that the back-side of the
wafer and the mask are now facing up. Accordingly, F1 and
F2 positions of primary flat of the wafer are interchanged
as shown in Figure 12(b). The wafer and mask are again
aligned and
to: held in the same manner as was done for the
front-side alignment, but this time with respect to top and
left-sides of the aligner ridges, as shown in Figure 12(b).
The 03:33:47
wafer is again exposed by UV light. After UV expo-
sure on both the sides, the photoresist is developed and
post baked. Finally, to delineate the alignment marks on
the two sides of the wafer, etching of silicon oxide is car-
ried out followed by photoresist stripping. Thus, the four
“+” shaped alignment marks will be formed in the oxide
layer on both the sides of the wafer which are mutually
aligned. For transferring the device patterns on the wafer,
these marks work as reference for front-to-back alignment.
This technique of front-to-back alignment requires sim-
ple low-cost mechanical fixture and a metal sheet mask
for generation of alignment marks on both the sides of
the wafer. Once these marks are generated, any existing
contact/proximity mask aligner can be used for transferring
the pattern on the two sides of the wafer. As discussed in
Section 3.1, in bulk micromachining process using (100)-
silicon wafer, the primary flat is used as reference to define
rectangular cavities of precise dimensions by anisotropic
etching and also for releasing suspended structures.9 It is
advantageous to use the proposed technique for front-to-
back alignment as this also uses wafer flat as reference to
generate the marks on both sides of the wafer by mechan-
ical fixture and mask.
Alignment Accuracy: In this method of alignment, an
accuracy upto 4–5
m is achieved. The misalignment of
marks on the two sides of the wafer generated by this
method has the following possible reasons:
(1) The metal sheet mask or wafer (or both) are not per-
fectly aligned and locked along the ridges on the mechan-
ical fixture.
(2) Limited surface finish of the sides of the ridges (and
sheet metal mask) against which the wafer and the mask
are aligned and secured.
7
 Front-to-Back Alignment Techniques in Microelectronics/MEMS Fabrication: A Review Pal et al.

(3) Mechanical fixture’s ridges and the sides of sheet metal Reference frames
mask are not perfectly orthogonal.
Due to above mentioned reasons, the alignment accuracy
of the patterns on the two sides of the wafer may vary at (0,0)
Y
different location of the wafer. X
1 2 3
REVIEW

The proposed technique has limitation that it can be used B 7 8 9

only when well defined wafer flat is present. The align- 4 5 6
4 5 6
ment accuracy will be adversely affected if the wafer flat 7 8 9 B
is distorted. Furthermore, the technique cannot be used on 1 2 3
X
irregular shaped wafers. A
(0,0)
Y
A

3.5. Front-to-Back Alignment Using

Mask Modification Mask for back-side lithography Mask for front-side lithography

Fig. 13. The back-side and the front-side masks with the pattern side
In this technique, front-to-back alignment is performed by up. During lithography process, the masks will be rotated by 180 about
slight modification in the mask design.54 This method uses the vertical axis, as shown. Reprinted with permission from [54], P. Pal
identical square-shaped patterns called “reference frame,” et al., Sens. Lett. 2, 78 (2004). © 2004, American Scientific Publishers.
having sides greater than the wafer diameter, are created
on both the mask plates which are to be usedDelivered wafer is then
for patternby Ingenta to: moved upward till either the periphery or the
transfer on the two sides of the wafer. The regular device secondary
Prem Pal flat of the wafer (if present), touches the upper
patterns are placed within this reference frame using the arm
IP : 133.6.73.118 of the reference frame. F1 and F2 are the corner points
corners of the square as origin of coordinates. The detailed
Wed, of the
12 Mar 2008 03:33:47 wafer flat. The wafer is exposed in this aligned posi-
procedure of mask design and wafer to mask alignment is tion for the back-side mask. For the front-side alignment,
described below: the wafer is flipped along the horizontal axis as shown in
The technique is demonstrated using two mask pro- Figure 14 so that the front-side is now upwards. Accord-
cess with square shaped patterns. However, the technique ingly, F1 and F2 positions are interchanged. The wafer flat
is generic and can be used for more complex process is again aligned with right-side arm of the reference frame
sequence and with any kind of mask pattern. of the front-side mask. While maintaining this alignment,
Mask Design Methodology: For simplicity, a matrix of the wafer is now moved down till its periphery or the sec-
3×3 identical patterns has been considered for both the ondary flat (if present) touches the bottom side of the refer-
front and the back side masks. Two identical square shaped ence frame. The front-side alignment is now complete and
frames having inner side greater than the wafer diameter the wafer is exposed in this position. It can be easily under-
are formed on the masks which are to be aligned front-to- stood that the device patterns numbered 1 to 9 on either
back. The width of the frame-lines is not critical and can mask will overlap on the two sides of the wafers as shown
in Figure 15 and the alignment is achieved using reference
follow the design rules used in the process. These frames
frame and appropriate origin for the coordinates.
will be referred to as reference frames. The device related
This technique of front-to-back alignment requires sim-
structures are placed inside the frames. The origin of coor-
ple modifications in mask design and does not require any
dinates for the back-side mask is taken as left-hand top
inner corner of the frame and for the front-side mask, the
same is taken as the left-hand inner bottom corner. The lay-
out is illustrated in Figure 13. Accordingly, the coordinates 3 2 1
9 8 7
of the center of the square closest to the origin (marked F1 F2
1) are (X Y ) for the back-side mask. The center-to-center 6 5 4
6 5 4
spacing between neighboring squares is taken as A and B in 9 8 7
F2 F1
the x- and y-directions respectively. The coordinates of the 3 2 1

centers of all the 9 squares can be calculated accordingly.

Similarly, the front-side mask is drawn using left-hand
bottom corner of the reference frame as the origin. During
the lithography process, the masks will be flipped by 180
along the vertical axis as shown to bring the patterned side
of the mask face to face with the wafer surface.
Mask Alignment Procedure: During the alignment pro-
cedure for the back-side mask, the primary flat of the wafer
is aligned with right-hand side of the reference frame as
shown in Figure 14. While maintaining this alignment, the
Back-side wafer alignment Front-side alignment
with top/right sides of
the reference square
with bottom/right sides of
the reference square
Fig. 14. Alignment methodology: for the back-side, wafer is aligned
with the top/right sides of the reference square; for the front-side, the
alignment is with bottom/right sides of the reference square. F1, F2 are
the corners of the wafer flat which get inverted for the two sides of the
wafer. Reprinted with permission from [54], P. Pal et al., Sens. Lett. 2,
78 (2004). © 2004, American Scientific Publishers.

8 Sensor Letters 4, 1–10, 2006

Pal et al. Front-to-Back Alignment Techniques in Microelectronics/MEMS Fabrication: A Review

alignment give the alignment accuracy comparable to those

for IR and double side mask aligners. For the fabrication
of MEMS structures of controlled dimensions into (100)-Si
wafer using bulk micromachining process, the mask pat-
terns are aligned along the crystallographic directions. For
this purpose the primary flat of the wafer is taken as ref-

REVIEW
erence. Therefore, the techniques described in Sections 3.4
and 3.5 have an added advantage that the primary flat of the
wafer is being used as a reference for generation of front-
to-back alignment marks or aligning the patterns on both
the sides of the wafer.

Acknowledgment: The work is supported by KOSEF

Pattern on the back-side Pattern on the front-side through National Core Research Center (NCRC) for
Nanomedical Technology (R15-2004-024-00000-0).
Fig. 15. The aligned patterns as they appear on the silicon wafer look-
ing from front-side.
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