IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-13, NO.

5, OCTOBER 1978 703

6) Means for storing the personality of the repaired chip [6] D. Frohmann-Bentchkowsky, “A fully-decoded 2048-bit elec-
must be provided. trically programmable MOS-ROM,” in ZSSCC Dig., Feb. 1971,
pp. 80-81.
[7] R. H. Dennard and P. W. Cook, private communication.
ACKNOWLEDGMENT [8] R. H. Dennard, “Field-effect transistor memory;’ U.S. Patent
The helpful discussions with D. L. Critchlow, R. H. Dennard, 3387286, June 4, 1968.

and L. M. Terman and their contributions to the 16K design

are appreciated.

REFERENCES

[1] E. Tammaru and J. B. Angell, “Redundancy for LSI yield enhance- Stanley E. Schuster (S’61-M’65 ) received the
ment,” IEEE J. Solid-State CYr-cuits, vol. SC-2, pp. 172-182, Dec. B.S. and M.S. degrees in electrical engineering
1967. from New York University, New York, NY, in
[2] A. Chen, “Redundancy in LSI memory array:’ IEEE J. Solid-State 1962 and 1969, respectively.
Circuits, vol. SC-4, pp. 291-293, Oct. 1969. From 1962 to 1963 he was with the Bendix
[3] J. K. Ayling and R. D. Moore, “Monolithic main memory,” in Corporation, and from 1963 to 1965 he served
ISSCCDig., Feb. 1971, pp. 76-77. as an Officer in the U.S. Army Signal Corps.
[4] B. R. Ehner, W. E. Tchon, A. J. Denboer, and R. Fromer, “Fault In 1965 he joined IBM where he presently
tolerant 92160 bit multiphase CCD memory ,“ in ZSSCC’Dig., Feb. work S in the Semiconductor Science and Tech-
1977, pp. 116-117. nology Department, T. J. Watson Research
[5] L. Kuhn, S. E. Schuster, P. S. Zory, G. W. Lynch, and J. T. Parish, Center, Yorktown Heights, NY, on integrated
“Experimental study of laser formed connections for LSI wafer circuits and svstems. His activities at IBM have also included line con-
personalization,” IEEE J. Solid-State Circuits, vol. SC-1 O, pp. trol and err& recovery procedures for communications systems and
219-228, Aug. 1975. laser personalization of integrated circuits.

A Charge-Oriented Model for MOS Transistor

Capacitances
DONALD E. WARD, STUDENT MEMBER, IEEE, AND ROBERT W. DUTTON, MEMBER, lEEE

Abstract–A new model for computer simulation of capacitance it is inadequate for use with some newer device and circuit
effects in MOS transistors is presented. Transient currents are found technologies. In particular, it fails for circuits in which charge
directly from the charge distribution in the device rather than from
storage is important. Such is the case for many dynamic and
capacitances. The effective capacitances which result are nonreciprocal.
The model guarantees conservation of charge and includes bulk capaci-
silicon-on-sapphire (SOS) circuits. A model to handle circuits
tances. Severaf circuit examples are considered. in which charge is more important than capacitance will be
presented here.

INTRODUCTION THE CONVENTIONAL MODEL

HE successful computer simulation of MOS circuits
T requires an accurate model for transistor, capacitances.
While use of average capacitance values may suffice for some
Meyer’s
are defined
model is shown
in terms of the total
in Fig. 1. Three nonlinear
gate charge QG;
capacitors

devices or circuits, it is usually necessary to consider the varia- (1)

tion of capacitance with voltage. A model which does this
was developed by Meyer [ 1] , and is used in many modern The current through each capacitor is computed from
circuit simulators. While this model works well for most cases,

(2)
Manuscript received December 8, 1977; revised June 2, 1978. This
work was initially supported by Hewlett-Packard Corporate Engineering
and received continuing research support from the Advanced Research where the capacitance has been evaluated at some appropriate
Projects Agency under Contract DAA-B07-C-1 344. The work of one voltage V..
of the authors was supported by an NSF Fellowship.
The authors are with the Integrated Circuits Laboratory, Stanford Several problems can occur with this model, the most impor-
University, Stanford, CA 94305. tant being the omission of source-bulk and drain-bulk capaci-

0018 -9200 /78/1000 -0703 $00.75 01978 IEEE

704 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-13, NO. 5, OCTOBER 1978

VG
Ilk

v=,ck&_lkL
w CGB
B

Fig. 1. Meyer model.

P
1

tances. These problems lead to a nonconservation of charge I/iB

(charge pumping) in which the charge stored in a node is not
‘B
equal to the integrated net current flowing into the node.
Discontinuities in the capacitance functions can also cause Fig. 2. Charge-oriented model.
instabilities in the Newton-Raphson iteration procedure.
The partitioning of channel charge will be considered in more
THE CHARGE-ORIENTED MODEL
detail later. Note that gate overlap and substrate junction
The proposed model is based on the actual charge distribu- capacitances should be included in addition to the “intrinsic”
tion in the MOS structure (Fig. 2). For any region of space we charge discussed here.
can write Equations (3) and (4) are used to relate voltage and current
as follows. Let subscripts denote timepoints and superscripts
. dQ
denote Newton-Raphson iteration numbers. Thus, we have
1=%
V. = voltage at last timepoint (known)
where i is the net current flowing into the region and Q is the
V? = voltage at previous iteration, this timepoint (known)
total charge contained in the region. Thus, we can write
V: = voltage at next iteration, this timepoint (unknown).
._ d&, _ dQB d(Q~ + Q~)
i~+j~= (3) From (4)
lG - dt ‘B - dt dt “

For use in a circuit simulator we integrate these equations:

t,
.( to
i dt = Q(tJ - Q(tO). (4)
where the integral
trapezoidal integration
Expanding Q; (V) about V!,
of current
formula.
has been approximated by a

In general, Q is a complex function of time. The problem is

simplified by assuming that the charge at any time is deter- —V:l). (9)
mined by the terminal voltages at that instant. Then Q can be
determined from steady-state conditions.
Any theory of MOS transistor operation which predicts the The subscript x takes the values “D,” “G,” “S,” and “B,”
total gate and bulk charges can be used to find QG, QB, and denoting one of the terminals. Thus,

Qs + QD. The results given here are based on the simple

theory of Ihantola and Moll [2] . More sophisticated treat-
ments such as that of Sah and Pao [3] would give more accu-
rate results, but are not suited for use in circuit simulators (lo)
because of their complexity. Gate and bulk charges are calcu-
This equation for i; can be substituted into the nodal admitt-
lated from the one-dimensional Poisson equation applied ance matrix to obtain a solution V~l.
perpendicular to the surface. Channel charge is computed
It is clear that in this model charge is conserved since it is
from
computed directly from the voltages. Convergence problems
Qc = -(QG + QB) (5) are minimized by complete linearization of (4). The inclusion
of an equation for the bulk ensures that capacitance effects
and is related to the source and drain charges:
associated with the bulk will be modeled.
QC=QS+QD. (6) It is convenient to define the capacitances

Unfortunately, the drain and source charges are not as well aQy
Cyx Q — (11)
defined as the gate and bulk charges and must be obtained by avx”
partitioning the channel charge. The present model uses
Note that there are two capacitances between each pair of ter-
QS=QD = iQc. (7) minals. Thus, for example, we have c@ = dQG/d VB and
WARD AND DUTTON: CHARGE-ORIENTED MODEL

c I

co~

(a)

1, ~MEyER)f&BG
VFB VT
“G

-cuTwF+sAT”RA
1

— CUTOFF SATURATION LINEAR—

+ +

Fig.3. Gate-bulk capacitances. (

~-. . ------
(b) I z
I MEYER ‘ _________

/
/
/
/
I J/
Fig. 5. (a) Drain-gate and (b) source-gate capacitances.
‘FB VT VD+ vT~ VD+ VTD

— CUTOFF SATURATION LINEAR—

+ + model, the threshold voltage at the drain is computed from the
Fig.4. Gate-drtin capacitances. bulk charge at the source.
In order to find the drain and source currents from (3), we
CBG=aQB/aVG between gate and bulk. These cannot be must have an algorithm for partitioning Qc into QD and QS.
represented by a normal, two-terminal, reciprocal capacitor This splitting may be done in several ways.
since, in general, CYX#CXY. As an example, CGB and CBG 1) Divide the channel physically at some y. = aL where L is
are plotted as functions of gate voltage in Fig. 3. It is apparent the channel length. Then take
that the present model differs substantially from that of Meyer.
The Meyer model defines CGD, CGB, and CGS in the same ‘0 dQc L dQC
Qs . —dy and QD= —dy. (12)
manner as the present model, but assumes that CDG = CGD, Jo dy J ~0 dy
CBG = CGB, and C~G = CG~. Also, a simpler form for bulk
charge is assumed. Thus, as shown in Fig. 3, the gate-bulk Thus, the charge to the source side ofyo goes into Qs and the
capacitance for the Meyer model is zero above VT, while it charge on the drain side goes into QD. Then YO = aL can be
can be seen that the charge model gives capacitances which are found by the following.
significant. a) Take a = constant.
Fig. 4 compares CGD and CDG for the charge model and b) Take y. as the point where the surface potential is
that of Meyer. Here we can readily see a physical basis for the some constant fraction of the drain-to-source voltage.
difference between CGD and CDG in saturation. CGD describes c) Calculate the transient current in the channel 61(y)
the effect of the drain on the gate (a feedback effect). In satu- due to a change in a terminal voltage Vx. Take YO so that
ration, the drain voltage is isolated from the channel by the ~z(y~) = o. This gives the exact terminal currents. The
pinchoff condition and cannot affect the gate charge. Thus, point yO varies with bias and depends on which voltage Vx is
CGD is zero. A change in gate voltage, however, will produce a changed.
change in channel charge. Some of this change in charge will d) Take a = ye/L as any empirical function of the terminal
come about through a drain current. Thus, CDG, which de- voltages.
scribes the effect of gate voltage on drain charge (a feed- 2) Divide the channel charge mathematically, take QD =
forward effect), will not be zero. Fig. 4 also shows C’GDfor ~Qc, QS = (1 - b)Qc, and O ~b~ 1. In general, b may be a
the Meyer model. Although similar to CGD of the charge function of the terminal voltages. In this case, aQD/d vx =
706 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-13, NO. 5, OCTOBER 1978

+“c(v)%
(a)
F’__l

UC(V) (a) ‘IN rl=h

“T 7-’”’ 1-

‘Inn
‘b)“Nl__/aa
(b)

CA
(c)

“’OLDM’
--t

“P-D+-D-’
‘d)
‘;’’id’l--44$-1
Fig. 6. Circuit showing nonconservation
‘\
~.——.

of charge.
DATA
Fig. 7. Bootstrap circuit.

“s”
OUTPUT

l-l
11 I

b(dQC/d VX) + Qc (db/VX). Thus we must take derivatives of M;

b. The method chosen was method 2) with b = ~.
Although model 1c) gives the exact capacitances, it is diffi-
cult analytically. The method was used in a numerical analysis
M2
to find the capacitances CDG and CSG. These are compared
Fig. 8. Circuit of SOS flip-flop,
with the results using method 2), b = $, and with the Meyer
model in Fig. 5. Thus the charge model assigns half the chan-
nel charge in saturation to the source and half to the drain, Fig. 7(a) shows a more realistic version of the previous exam-
while the Meyer model assigns all the charge to the source. ple. In this bootstrap circuit, the variable capacitor has been
The exact result assigns ~ of the channel charge to the source replaced by the gate-source and gate-drain capacitance of an
and ~ to the drain. MOS transistor, and a load capacitance was added. The simu-
lated output using the Meyer model is shown in Fig. 7(c).
EXAMPLES Note that the dc levels are in error by several volts. Also, the
Several examples which illustrate the importance of the result depends on the timestep used. Even with 64 timesteps
charge-oriented model applied in circuit simulation are now in the risetime of the input, the output is in error by 0.5 V
considered. Fig. 6(a) shows a nonlinear capacitance driven by after two cycles, As seen in Fig. 7(d), the charge-oriented
the voltage waveform of Fig. 6(b). Fig. 6(c) shows the capaci- model gives accurate dc levels even for a timestep equal to the
tance as a function of time. The Meyer model approximates risetime of the input. Thus, we can greatly reduce simulation
this capacitance by the stairstep shown in the dotted line. The time while maintaining increased accuracy.
size of the step depends on the timestep h used in the simula- Fig. 8 is the circuit of a D-type latch fabricated with CMOS-
tion. The current entering the capacitor is shown in Fig. 6(d). on-sapphire technology. When the clock goes high, M2 turns
Note that in the simulated (dotted) waveform, more current off, breaking the feedback path, and the input data are con-
flows out of the capacitor than flows in. This represents a nected to the inverter pair through Ml, an n-channel, floating-
charge loss, as shown in Fig. 6(e). In many practical circuits, bulk device. When the clock again goes low, Ml turns off and
this charge loss would result in a voltage error. iW2 turns on, latching the data.
WARD AND DUTTON: CHARGE-ORIENTED MODEL 707

(a) DATA

‘21-m_L DATA “s “

(b) CLOCK

‘21!l_nIL CLOCK
(a)

(c) OUTPUT

“:-
6VP NODE “S”

(d) OLD MODEL

o \ A I
CLOCK
BULK (b)
OF Ml
-9v -
Fig. 10. Meyer and charge representations for Ml of Fig. 8.

~NODE l’S”
channel capacitance in saturation. The model is especially
suited to circuits where charge conservation is importmt, such
(e) NEW MODEL
as in dynamic and SOS circuits. Examples have been given for
[ml
I \ 1 which the charge-oriented model gives correct results, while
o I \
L
the conventional model is inadequate.
BULK
OF Ml
REFERENCES
Fig.9. Waveforms forcircuitof Fig.8.
[1] J. E. Meyer, “MOS models and circuit sirnulation~’ RCA Rep., vol.
32, pp. 42-63, Mar. 1971.
Fig. 9(c) shows the output of a simulation for the inputs of [2] H. K. J. Ihantola and J. M. Moll, “Design theory of a surface field-
Fig. 9(a) and (b). According to the old model, the output effect transistor,” Solid-State Electron., vol. 7, pp. 423-430, June
1964.
never goes high. The results predicted by the new model are [3] C. T. Sah and H. C. Pao, “The effects of fried bulk charge on the
correct. characteristics of metal-oxide-semiconductor transistors,” IEEE
The discrepancy isdueto thedifference ineapacitance mod- Trans. Electron Devices, vol. ED-13, pp. 393-409, Apr. 1966.

els during the rising clock. Fig. 10(a) shows the Meyer model
for Ml at this time. The bulk is coupled to node “S” through
Donald E. Ward (S’72) received the B.E.E. de-
a capacitive divider chain consisting of the junction capaci- gree from the Georgia Institute of Technology,
tances CJSB and CYDB. Fig. 9(d) shows that while the bulk of Atlanta, in 1975, and the M. S.E.E. degree from
Stanford University, Stanford, CA, in 1976.
IWl follows node “5’” to some extent, a back-bias of 5 V still
He is currently a Ph.D. candidate at Stanford,
develops to turn off the device. An approximate equivalent doing research on MOS models for computer-
circuit using the new model, Fig. 10(b), has two more capaci- aided design.
tances in the divider network. The bulk-gate capacitance C’BG
couples the rising clock signal to the bulk, while the bulk-
source capacitance CBS couples the bulk to node “S.” The
result, seen in Fig. 9(e), is that only 1 V of back-bias is pro-
duced and node “S” ~ises to a voltage capable of setting the Robert W. Dutton (S’67-M’70) received the
latch. B. S., M. S., and Ph.D. degrees from the Univer-
sity of California, Berkeley, in 1966, 1967, and
1970, respectively. He was the 1966-1967
CONCLUSIONS
Fairchild FeUow and a NationaJ Science Foun-
A model for MOS capacitance which is based on charge has dation Fellow from 1967 to 1970.
During the summer of 1967 he was employed
been presented. It is shown that the capacitive effects cannot
by Fairchild Semiconductor Laboratory, Palo
be modeled by simple capacitors, but that nonreciprocal ele- Alto, CA, and studied p-n-n+ high-low junc-
ments are required. Thus, while a change in drain voltage in tions. In his graduate thesis work he studied
deuosited thin-film Te-CdS diodes amd Te tran-
saturation cannot affect the gate, a change in gate voltage will
sistors. During the 1970~1971 academic year he was an Acting Assis-
cause a drain current. Numerical results indicate that this tant Professor at the University of CaHfornia, Berkeley. In 1971 he
gate-to-drain capacitance accounts for # of the total gate-to- joined the Faculty of Electrical Engineering at Stanford University,
 708 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-13, NO. 5, OCTOBER 1978

Stanford, CA, where he is presentJy an Associate Professor. During the performance IC devices. His present research interests focus on process
summer of 1973 he was a member of the Technical Staff at Bell Labo- sirnulation, device modeling, and IC characterization using minicom-
ratories, Hohndel, NJ, and worked on the modeling of saturation and puters. During the summer of 1977 he was a visiting member of the
avalanche in bipolar transistors for application in circuit simulation. Technicaf Staff at the IBM Thomas J. Watson Research Center, York-
During the summer of 1975 he was a member of the TechnicaJ Staff at town Heights, NY, studying two-dimensional implanted profile
Hewlett-Packard Laboratories, developing test structures for two- structures.
dimensional profiie measurements. In 1975 he received a NATO Senior Dr. Dutton is a member of Tau Beta Pi, Eta Kappa Nu, and Sigma Xi.
Fellowship in science to study computer tools for design of high- He is also a member of the IEEE CANDE Committee.

Special Correspondence

An 8 rnmz, 5 V 16K Dynamic RAM Using a New Memory Cell

GUNT’E-IliR MEUSBURGER, KARLHEINRICIi Cs

=– STORAGE CAPACITOR
HORNING13R, AND GEROLD LINDERT
, SELECTOR
T TRANSISTORS

Ab$tract–A mail 16K dynamic RAM utilizing a new memory cell ?

configuration is described. The new cell has two selector transistors and ‘) $fA SELECTOR LINE

makes a very short bit line possible. The memory on 8 mmz is built in BL
– BITLINE
a scaled double polysilicon technology with 3.5 vm line width. First T;
samples achieved an access time of 160 ns. JYB SELECTOR LINE

\
T;– SELECTOR
I. INTRODUCTION :/, ,“ m-% .~
TRANSISTORS
To date two technologies are prime candidates for the fab- ~j ; j ,3
c~- STORAGE CAPACITOR
rication of 65K RAM’s–the double polysilicon technology [ 1]
and the VMOS technology [2] . 10 ,,(11

In this paper a very small 16K RAM in double polysilicon ~ \ //~

---- //
technology is described which can be quadrupled to build a WL
~ WOROLINES
65K RAM not much larger than some 16K dynamic memories
now on the market. This realized 16K RAM has a chip size of (a) (b)
only 8 mmz and uses supply voltages of +5 and -5 V. First
experimental samples achieved an access time of 160 ns.
WOROLINE
The high performance of this memory was achieved by uti-
lizing a new memory cell configuration in conjunction with a
slightly scaled technology. This advanced technology uses
3.5 pm line width and spacing, a gate oxide thickness of 60 c
——— —____

nm, arsenic implantation for shallow diffusions, and a high-

ilFFu SEO !
ohmic substrate (20 f2 . cm). The following sections will
BITLINE
describe the new memory cell, the design and operation fea-
tures of the memory, as well as the first experimental results. SELECTOR STORAGE
TRANSISTORS CAPACITOR
II. MEMORY ChLL r T,

The size of the storage capacitor of a memory cell is, among (c)
other parameters, mainly determined by the magnitude of the Fig. 1. (a) Circuit configuration. (b) SEM micrograph. (c) Cross sec-
signal on the bit line, which must be higher than the sensitivity tion of the new memory cell.
of the sense/refresh amplifier. The signal magnitude is often
expressed as a ratio of storage capacitance Cs to the bit line
mined by the lithography and technological parameters (line
capacitance CB. The specific lmt line capacitance CB is deter-
width, substrate doping), whereas the total value of CB is
strongly determined by the number of storage cells and the
Manuscript received ApriJ 5, 1978; revised May 31, 1978. This work length of the bit line per cell. For a small memory cell, there-
was supported by the Technical Program of the Federal Department of
fore, a short bit line is a prerequisite. The new memory cell
Research and Technology of the Federaf Republic of Germany. The
shown in Fig. 1 leads to very short bit lines. The cell is basically
authors alone are responsible for the contents.
G. Meusburger was with Siemens AG Research Laboratories, Munich, a single transistor cell [ 3 ] with an additional selector transistor.
Germany. He k now with Eurosil GmbH, Munich, Germany. Because of this additional transistor, cells sharing the same
K. Horninger and G. Ihkrt are with Siemens AG Research Labora- word line WL can therefore be placed vis-~.-vis the bit line BL.
tories, Munich, Germany. The word line WL is connected to the selector transistors T2

0018 -9200 /78/1000-0708 $00.75 Q 1978 IEEE