294
1,FEBRUARY 1988
vi
GI\D
Fig. 3. MOS Schmitt trigger.
again as for the bipolar case. From (6) and (17) the hysteresis is
given by
where ++ is given by (15). (Notice also that g > K *
rna(/3/2)++ R > 2). Thus, from (19), the answer to the question
posed above is that, unlike the bipolar case, 2’cannot easily be
made PTAT, and depends on I,, 8, and R.
Previous analysis of this MOS Schmitt trigger circuit [9, ap-
pendix 111neglects the current flowing in the device which is just
turning on at switching with respect to the differential pair
current I,. Using Abidi’s approximation (for m a = 1)
whereas the analysis presented here, using (1) and (16), gives
8
V , + = E , - - +I,R- t“
--+:. +
(21) R/r
2 2
For 8 = 200 pA/V2, I, =10 pA and R =lo0 k0, Abidi’s ap-
proximate method outlined above gives E, - V,+ = 25 mV and
the analysis presented here gives E, - V,+= 35.5 mV; errors in
the calculation of the switching points of relaxation oscillators,
even as small as these, are important as they effect our ability to
determine the effects of oscillator noise and expected jitter [9].
The error of the approximate method increases further with
decreasing G.
V. CONCLUSION
An exact and general analysis has been given for the trigger
circuit originally proposed by Schmitt. The simplicity of the
equations presented here give us greater insight into the oper-
ation of such circuits. Bipolar versions of Schmitt’s original
trigger circuit have been exploited for their thermal properties,
despite the problems of errors introduced by base currents. (Note
added in proof: For a recent analysis of the error due to bipolar
device base current see [lo].) The MOS version of Schmitt’s
trigger does not suffer from this problem, but it was shown that
the thermal behavior is not as straightforward as the bipolar
version.
Finally it should be pointed out that the “exact” analysis
presented here is only as accurate as the equations used to model
the active devices. For bipolar devices the error due to ignoring
base current has already been pointed out. For modem MOS
devices operating in the saturation region the ideal square law
0018-9200/88/0200-0294$01.00 01988 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO.
approximation is valid only for long-channel devices with zero
body-source voltage.
REFERENCES
0. H. Schmitt, “A thermionic trigger,” J. Sri. Instrum., vol. XV, pp.
24-26, Jan. 1938.
J. F. Kukieka and R. G. Meyer, “A high-frequency temperature-stable
monolithic VCO,” IEEE J. Solid-Stare Circuits, vol. SC-16, pp. 639-647,
Dec. 1981.
M. J. S . Smith and J. D. Meindl, “Exact analysis of the Schmitt trigger
oscillator,” IEEE J. Solid-state Circuits, vol. SC-19, pp. 1043-1046, Dec.
1984.
M. J. S . Smith, L. Bowman, and J. D. Meindl, “Analysis, design, and
performance of micropower circuits for a capacitive pressure sensor IC,”
IEEE J. Solid-state CirnUts, vol. SC-21, pp. 1045-1056, Dec.1986.
E. J. Dickes and D. E. Carlton, “A graphical analysis of the Schmitt
trigger circuit,” IEEE . ISolid-state
. Circuits, vol. SC-17, pp. 1194-1197,
Dec. 1982.
C. J. F. Ridders, “Accurate determination of threshold voltage levels of a
Schmitt trigger,” IEEE Trans. Circuits Syst., vol. CAS-32, pp. 969-970,
Sept. 1985.
S . C. Dutta Roy, “Comments on ‘Accurate determination of threshold
voltage levels of a Schmitt trigger,”’ IEEE Trans. Circuits Syst., vol.
CAS-33, pp. 734-735, July 1986.
P. R. Gray, “Basic MOS operational amplifier design-An overview,” in
Analog MOS Integrated Circuits. New York: IEEE Press, 1980, pp.
28-49.
A. A. Abidi and R. G. Meyer, “Noise in relaxation oscillators,” IEEE J.
Solid-Stare Circuits. vol. SC-18. DD. 794-802. Dec. 1983.
[lo] H-U. Lauer, “Comments on ‘Ac’cirate determination of threshold voltage
levels of a Schmitt trigger,”’ IEEE Trans. Circuits Syst., vol. CAS-34, pp.
1252-1253, Oct. 1987.
A Comment on “Characterization and Modeling of
Mismatch in MOS Transistorsfor Precision
Analog Design”
CORMAC S.G. CONROY, WILLIAM A. LANE, AND
MICHAEL A. MORAN
This comment relates to a recently published paper [l]in which
the yield of a digital-to-analog converter (DAC) as a function of
component matching is estimated analytically. An assumption
inherent to that derivation, namely that the DAC outputs are
independent, is questioned and is demonstrated to be incon-
sistent with Monte-Carlo simulations.
Recently some work has been reported [l] in which an analyti-
cal expression for the yield of an 8-bit DAC is derived. This
expression is repeated here for convenience, using the nomencla-
ture of [l]:
where
G=fraction of die having maximum integral nonlinearity
(INL) within the limits & 1/2 LSB;
z =x/(x + y ) = normalized DAC output; z is a function of
the digital code i , 0 d i < 255;
x = DAC output current =
Manuscript received July 15, 1987.
C. S . G. Conroy and W. A. Lane are with the National Microelectronics
Research Centre, University College, Cork, Ireland.
M. A. Moran is with the Department of Statistics, University College, Cork,
Ireland.
IEEE Log Number 8718657.
IEEE JOURNAL OF SOLID-SlATE CIRCUITS, VOL. 23, NO 1, FEBRIJARY 19x8

Fig. 1 8-bit DAC network using same architecture as in [ l ]

y = DAC complementary output current = YIELD

c
1<J<X
(1-D,N

I, =value of individual bit current;

D, =value of binary input bit; l . 0 ~
2 =expected (i.e., mean) value of z ;
U=' =variance of z =

2(1-z)
0,
j(F+j)

j =mean value of a unit current source; and

U' =variance of a unit current source.
A plot of G evaluated from (I) is shown in [l, fig. 81, as a
function of ( u / I ) .
It should be noted that the DAC circuit described in [l],
although comprising an array of unit current sources, is essen-
tially a binarily-weighted topology: the individual current sources
are aggregated in powers of 2 and each digital input bit directly Fig. 2. DAC yield as a function of resistor matching ( o / R ): ( U ) as predicted
drives a group of unit currents- there is no segment decoding. In by (1)and. ( h ) as obtained from Monte-Carlo simulations.
general for an n-bit DAC consisting of statistically independent
binarily-weighted current sources I,, I,, . . . , I,, the normalized
output at digital input code Q may be written as independent. However, because of the correlations between the
DAC outputs, (1) will underestimate the true yield. Note that the
+
DIIl t D z I , t D31, . . . D,,I,+ values of these correlation coefficients may be obtained analyti-
Il+I,+'.'+I,, cally using the method of propagation of errors [2], [3].
The above was confirmed by Monte-Carlo simulations of the
where D,, D, ,. . . ,On are the digital bits ( D , MSB, D, LSB). DAC resistor network shown in Fig. 1 using the DAC simulation
Thus z ( Q ) is a function of I, - I,, and it is clear that for any two program " DACSIM' [4]. This circuit is topologically identical to
digital input words Q, and Qz the covariance of z ( Q , ) and that in [l]. The link resistor R , ~which has nominal value R is the
z ( Q z ) will depend on: a) the variances of the currents I,; . .,I,?, equivalent of the current-dividing network in [l].It is actually a
and b) the values of the binary signals D,; . ., D,, corresponding series-parallel combination of 16 R's, i.e., four R's in parallel, in
to Q , and Q2. series four times. This is to ensure that the circuit is not sensitive
If two codes Q, and Q , have many equal binary signals they to variations in R,, since it was not included in the derivation of
will have a relatively high correlation. For example, if n = 8 and (1). The output current lines are assumed to be at ground
Q , =11110000, Q , =11110001, then potential. The resultant yield curve is shown in Fig. 2 along with
a reproduction of the curve given in [ l , fig. 81.
Il + I , + I3 + 1, The values of the resistors in the network were generated as
= Il + I , + ' ' ' + I , independent normal random numbers having mean value R and
coefficient of variation (o/R).' For a range of values of ( o / R )
and the yield (i.e., the fraction of circuits having INL withn the
I, + I, + I? + I, + I ,
= 1, + + . . . + I8 'The fact that the quantity being simulated IS unit resistance rather than
unit current (essentially its reciprocal) is o f no consequence, since if .T -
N ( p , u 2 )and if ( o / p ) ~ 1 percent,
0 then
It is clear that since z ( Q , ) and z ( Q z ) are sharing common bit
currents their correlation will be nonzero. (o/Ph/r= (o/P)t
From the form of (1)-direct multiplication of probabilities-it to a very good approximation. This was confirmed by some test Monte-Carlo
is apparent that the random va.ables { z ( i ) } are assumed to be simulations.
296 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23, NO. 1, FEBRUARY 1988

bounds *1/2 LSB) was calculated from 2000 Monte-Carlo Y I EL0

trials. It is clear that for a given resistor matching the yield

obtained via Monte-Carlo simulations is significantly higher than
that in [l], as expected.
Finally it should be noted that this Comment applies equally
well to [5] in which (1) is applied to the yield of a resistor-string
DAC again without taking into account the correlations between 0.6 -
DAC outputs.
0.5 -
REFERENCES 0.4-

0.3-
[l) K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, “Characteri-
zation and modeling of mismatch in MOS transistors for precision analog
design,” IEEE J . Solid-State Circuits, vol. SC-21, no. 6, pp. 1057-1066, 0.2 -
Dec. 1986.
0.4 -
[2] A. Papoulis, Probability, Random Variables and Stochastic Processes, 2nd
ed. New York: McGraw-Hill, 1984, p. 154. 01 I 1 1 J
[3] G . J. Hahn and S. S. Shapiro, Statistical Models in Engineering. New 0 0.5 4.0 4.5 2.0 2.p 3.0
York: Wiley, 1967, pp. 228-236.
[4] C. S. G. Conroy and W. A. Lane, “Statistical modeling and simulation RESISTOR STD. DEV. / [ X]
for DAC design,” in Proc. 12th European Solid-State Circuits Conf.,
ESSCIRC’86 (Delft, The Netherlands), Sept. 16-18, 1986, pp. 214-216. Fig. 1. DAC yield versus current source mismatch (a) as predicted by [l, eq.
[5] S. Kuboki et ol,, “Nonlinearity analysis of resistor string A/D con- (35)], (b) as obtained from Monte-Carlo simulations, and (c) as given by (1).
verters,” IEEE Trans. Circuits Syst., vol. CAS-29, no. 6, pp. 383-390
June 1982.
full scale and that the error probability decreases towards zero
for both minimum and maximum input word combinations. Thus
we may regard the input words 011 . . . l and 10 * . . O as the most
likely combinations that cause errors. As these codes are uncorre-
lated, the yield may be approximated as
Reply to “Comment on ‘Characterizationand Modeling
of Mismatch in MOS Transistors for
Precision Analog Design”’
KADABA R. LAKSHMIKUMAR, MEMBER, IEEE,
MILES A. COPELAND, SENIOR MEMBER,IEEE, AND
ROBERT A. HADAWAY

We have derived an analytical expression for the parametric

yield of a DAC as a function of the matching accuracy of the
unit current sources [l, eq. (35)]. Subsequently,it was pointed out
in [2] that the DAC outputs are not statistically independent and
hence the analytical expression is an underestimate of the true
yield. This has been demonstrated by performing a Monte-Carlo
simulation. The object of this reply is to modify the analytical
expression given in [l] to make it agree with Monte-Carlo simula-
tions.
To arrive at an exact expression for the yield requires the
determination of the joint probability density function of the
overall nonlinearity of the DAC. This in turn requires the evalua-
tion of a 256 X 256-element covariance matrix [3]! Thus it is not
possible to present a simple analytical expression for the exact
yield of the DAC. However, an approximate expression that
agrees well with Monte-Carlo simulations can be obtained as
follows.
We have shown in [l] that the probability of occurrence of
error is maximum when the DAC output is halfway through the
Manuscript received August 24, 1987.
K. R. Lakshmikumar is with AT&T Bell Laboratories, Murray Hill, NJ
07974.
M. A. Copeland is with the Department of Electronics, Carleton University,
Ottawa, Ont. K1S 5B6, Canada.
R. A. Hadaway is with Northern Telecom Electronics Ltd., Ottawa, Ont.,
Canada.
IEEE Log Number 8718658.
where 1/512 is the normalized 1/2 LSB value and
The yield as obtained from (1) is superimposed on [2, fig. 21. This
is shown in Fig. 1 here. The agreement with Monte-Carlo simula-
tions is excellent at high yield levels. At low yield values, (1) is an
overestimate. It should be noted that in practical situations one is
interested in high yield levels as the DAC is more likely to be a
subcircuit in a more complex chip rather than being a stand-alone
part. Thus, (1) may be used to get a good estimate of the yield.
REFERENCES
[ l ] K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, “Character-
ization and modeling of mismatch in MOS transistors for precision
analog design,” IEEE J. Solid-State Circuits, vol. SC-21, no. 6, pp.
1057-1066, Dec. 1986.
[2] C. S. G. Conroy, W. A. Lane, and M. A. Moran, “A Comment on
‘Characterization and modeling of mismatch in MOS transistors for
precision analog design,”’ IEEE J. Solid-State Circuits, vol. SC-23, no. 1,
pp. 294-296, Feb. 1988.
[3] A. Papoulis, Probability, Rondom Variables and Stochastic Processes, 2nd
ed. New York: McGraw-Hill, 1984, ch. 8.

0018-9200/88/0200-0296$01.00 01988 IEEE